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charset="utf-8" This brings us (back) closer to the original Linux source. While touching mwait_idle_state_table_update() also drop a stray leading blank. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -61,6 +61,7 @@ #include #include #include +#include #include #include #include @@ -996,48 +997,49 @@ static const struct idle_cpu idle_cpu_sn }; =20 #define ICPU(model, cpu) \ - { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ALWAYS, &idle_cpu_##cpu} + { X86_VENDOR_INTEL, 6, INTEL_FAM6_ ## model, X86_FEATURE_ALWAYS, \ + &idle_cpu_ ## cpu} =20 static const struct x86_cpu_id intel_idle_ids[] __initconstrel =3D { - ICPU(0x1a, nehalem), - ICPU(0x1e, nehalem), - ICPU(0x1f, nehalem), - ICPU(0x25, nehalem), - ICPU(0x2c, nehalem), - ICPU(0x2e, nehalem), - ICPU(0x2f, nehalem), - ICPU(0x1c, atom), - ICPU(0x26, lincroft), - ICPU(0x2a, snb), - ICPU(0x2d, snb), - ICPU(0x36, atom), - ICPU(0x37, byt), - ICPU(0x4a, tangier), - ICPU(0x4c, cht), - ICPU(0x3a, ivb), - ICPU(0x3e, ivt), - ICPU(0x3c, hsw), - ICPU(0x3f, hsw), - ICPU(0x45, hsw), - ICPU(0x46, hsw), - ICPU(0x4d, avn), - ICPU(0x3d, bdw), - ICPU(0x47, bdw), - ICPU(0x4f, bdw), - ICPU(0x56, bdw), - ICPU(0x4e, skl), - ICPU(0x5e, skl), - ICPU(0x8e, skl), - ICPU(0x9e, skl), - ICPU(0x55, skx), - ICPU(0x6a, icx), - ICPU(0x6c, icx), - ICPU(0x57, knl), - ICPU(0x85, knl), - ICPU(0x5c, bxt), - ICPU(0x7a, bxt), - ICPU(0x5f, dnv), - ICPU(0x86, snr), + ICPU(NEHALEM_EP, nehalem), + ICPU(NEHALEM, nehalem), + ICPU(NEHALEM_G, nehalem), + ICPU(WESTMERE, nehalem), + ICPU(WESTMERE_EP, nehalem), + ICPU(NEHALEM_EX, nehalem), + ICPU(WESTMERE_EX, nehalem), + ICPU(ATOM_BONNELL, atom), + ICPU(ATOM_BONNELL_MID, lincroft), + ICPU(SANDYBRIDGE, snb), + ICPU(SANDYBRIDGE_X, snb), + ICPU(ATOM_SALTWELL, atom), + ICPU(ATOM_SILVERMONT, byt), + ICPU(ATOM_SILVERMONT_MID, tangier), + ICPU(ATOM_AIRMONT, cht), + ICPU(IVYBRIDGE, ivb), + ICPU(IVYBRIDGE_X, ivt), + ICPU(HASWELL, hsw), + ICPU(HASWELL_X, hsw), + ICPU(HASWELL_L, hsw), + ICPU(HASWELL_G, hsw), + ICPU(ATOM_SILVERMONT_D, avn), + ICPU(BROADWELL, bdw), + ICPU(BROADWELL_G, bdw), + ICPU(BROADWELL_X, bdw), + ICPU(BROADWELL_D, bdw), + ICPU(SKYLAKE_L, skl), + ICPU(SKYLAKE, skl), + ICPU(KABYLAKE_L, skl), + ICPU(KABYLAKE, skl), + ICPU(SKYLAKE_X, skx), + ICPU(ICELAKE_X, icx), + ICPU(ICELAKE_D, icx), + ICPU(XEON_PHI_KNL, knl), + ICPU(XEON_PHI_KNM, knl), + ICPU(ATOM_GOLDMONT, bxt), + ICPU(ATOM_GOLDMONT_PLUS, bxt), + ICPU(ATOM_GOLDMONT_D, dnv), + ICPU(ATOM_TREMONT_D, snr), {} }; =20 @@ -1208,20 +1210,20 @@ static void __init skx_idle_state_table_ static void __init mwait_idle_state_table_update(void) { switch (boot_cpu_data.x86_model) { - case 0x3e: /* IVT */ + case INTEL_FAM6_IVYBRIDGE_X: ivt_idle_state_table_update(); break; - case 0x5c: /* BXT */ - case 0x7a: + case INTEL_FAM6_ATOM_GOLDMONT: + case INTEL_FAM6_ATOM_GOLDMONT_PLUS: bxt_idle_state_table_update(); break; - case 0x5e: /* SKL-H */ + case INTEL_FAM6_SKYLAKE: sklh_idle_state_table_update(); break; - case 0x55: /* SKL-X */ + case INTEL_FAM6_SKYLAKE_X: skx_idle_state_table_update(); break; - } + } } =20 static int __init mwait_idle_probe(void) From nobody Fri Nov 29 02:51:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" From: Artem Bityutskiy Add Sapphire Rapids Xeon support. Up until very recently, the C1 and C1E C-states were independent, but this has changed in some new chips, including Sapphire Rapids Xeon (SPR). In the= se chips the C1 and C1E states cannot be enabled at the same time. The "C1E promotion" bit in 'MSR_IA32_POWER_CTL' also has its semantics changed a bit. Here are the C1, C1E, and "C1E promotion" bit rules on Xeons before SPR. 1. If C1E promotion bit is disabled. a. C1 requests end up with C1 C-state. b. C1E requests end up with C1E C-state. 2. If C1E promotion bit is enabled. a. C1 requests end up with C1E C-state. b. C1E requests end up with C1E C-state. Here are the C1, C1E, and "C1E promotion" bit rules on Sapphire Rapids Xeon. 1. If C1E promotion bit is disabled. a. C1 requests end up with C1 C-state. b. C1E requests end up with C1 C-state. 2. If C1E promotion bit is enabled. a. C1 requests end up with C1E C-state. b. C1E requests end up with C1E C-state. Before SPR Xeon, the 'intel_idle' driver was disabling C1E promotion and was exposing C1 and C1E as independent C-states. But on SPR, C1 and C1E cannot = be enabled at the same time. This patch adds both C1 and C1E states. However, C1E is marked as with the "CPUIDLE_FLAG_UNUSABLE" flag, which means that in won't be registered by default. The C1E promotion bit will be cleared, which means that by default only C1 and C6 will be registered on SPR. The next patch will add an option for enabling C1E and disabling C1 on SPR. Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 9e= df3c0ffef0 Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- unstable.orig/xen/arch/x86/cpu/mwait-idle.c 2022-04-25 16:48:58.0000000= 00 +0200 +++ unstable/xen/arch/x86/cpu/mwait-idle.c 2022-04-25 17:17:05.000000000 +0= 200 @@ -586,6 +586,38 @@ static const struct cpuidle_state icx_cs {} }; =20 +/* + * On Sapphire Rapids Xeon C1 has to be disabled if C1E is enabled, and vi= ce + * versa. On SPR C1E is enabled only if "C1E promotion" bit is set in + * MSR_IA32_POWER_CTL. But in this case there effectively no C1, because C1 + * requests are promoted to C1E. If the "C1E promotion" bit is cleared, th= en + * both C1 and C1E requests end up with C1, so there is effectively no C1E. + * + * By default we enable C1 and disable C1E by marking it with + * 'CPUIDLE_FLAG_DISABLED'. + */ +static struct cpuidle_state __read_mostly spr_cstates[] =3D { + { + .name =3D "C1", + .flags =3D MWAIT2flg(0x00), + .exit_latency =3D 1, + .target_residency =3D 1, + }, + { + .name =3D "C1E", + .flags =3D MWAIT2flg(0x01) | CPUIDLE_FLAG_DISABLED, + .exit_latency =3D 2, + .target_residency =3D 4, + }, + { + .name =3D "C6", + .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .exit_latency =3D 290, + .target_residency =3D 800, + }, + {} +}; + static const struct cpuidle_state atom_cstates[] =3D { { .name =3D "C1E", @@ -972,6 +1004,11 @@ static const struct idle_cpu idle_cpu_ic .disable_promotion_to_c1e =3D true, }; =20 +static struct idle_cpu __read_mostly idle_cpu_spr =3D { + .state_table =3D spr_cstates, + .disable_promotion_to_c1e =3D true, +}; + static const struct idle_cpu idle_cpu_avn =3D { .state_table =3D avn_cstates, .disable_promotion_to_c1e =3D true, @@ -1034,6 +1071,7 @@ static const struct x86_cpu_id intel_idl ICPU(SKYLAKE_X, skx), ICPU(ICELAKE_X, icx), ICPU(ICELAKE_D, icx), + ICPU(SAPPHIRERAPIDS_X, spr), ICPU(XEON_PHI_KNL, knl), ICPU(XEON_PHI_KNM, knl), ICPU(ATOM_GOLDMONT, bxt), From nobody Fri Nov 29 02:51:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=suse.com; Message-ID: <7c15016f-cc57-f128-4b79-79c820f3196c@suse.com> Date: Tue, 26 Apr 2022 12:05:28 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.8.1 Subject: [PATCH 3/4] mwait-idle: add 'preferred_cstates' module argument Content-Language: en-US From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <4eae5ab3-361c-4eac-619c-160147220be4@suse.com> In-Reply-To: <4eae5ab3-361c-4eac-619c-160147220be4@suse.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AS8PR04CA0176.eurprd04.prod.outlook.com (2603:10a6:20b:331::31) To DU2PR04MB8616.eurprd04.prod.outlook.com (2603:10a6:10:2db::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 97e59483-66da-4853-cc83-08da276c4b08 X-MS-TrafficTypeDiagnostic: VE1PR04MB7358:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" From: Artem Bityutskiy On Sapphire Rapids Xeon (SPR) the C1 and C1E states are basically mutually exclusive - only one of them can be enabled. By default, 'intel_idle' driver enables C1 and disables C1E. However, some users prefer to use C1E instead = of C1, because it saves more energy. This patch adds a new module parameter ('preferred_cstates') for enabling C= 1E and disabling C1. Here is the idea behind it. 1. This option has effect only for "mutually exclusive" C-states like C1 and C1E on SPR. 2. It does not have any effect on independent C-states, which do not require other C-states to be disabled (most states on most platforms as of today= ). 3. For mutually exclusive C-states, the 'intel_idle' driver always has a reasonable default, such as enabling C1 on SPR by default. On other platforms, the default may be different. 4. Users can override the default using the 'preferred_cstates' parameter. 5. The parameter accepts the preferred C-states bit-mask, similarly to the existing 'states_off' parameter. 6. This parameter is not limited to C1/C1E, and leaves room for supporting other mutually exclusive C-states, if they come in the future. Today 'intel_idle' can only be compiled-in, which means that on SPR, in ord= er to disable C1 and enable C1E, users should boot with the following kernel argument: intel_idle.preferred_cstates=3D4 Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git da= 0e58c038e6 Enable C1E (if requested) not only on the BSP's socket / package. Signed-off-by: Jan Beulich --- unstable.orig/docs/misc/xen-command-line.pandoc 2022-04-25 17:59:42.123= 387258 +0200 +++ unstable/docs/misc/xen-command-line.pandoc 2022-04-25 17:36:00.00000000= 0 +0200 @@ -1884,6 +1884,12 @@ paging controls access to usermode addre ### ple_window (Intel) > `=3D ` =20 +### preferred-cstates (x86) +> `=3D ` + +This is a mask of C-states which are to be use preferably. This option is +applicable only oh hardware were certain C-states are exlusive of one anot= her. + ### psr (Intel) > `=3D List of ( cmt: | rmid_max: | cat: | cos_= max: | cdp: )` =20 --- unstable.orig/xen/arch/x86/cpu/mwait-idle.c 2022-04-25 17:17:05.0000000= 00 +0200 +++ unstable/xen/arch/x86/cpu/mwait-idle.c 2022-04-25 17:33:47.000000000 +0= 200 @@ -82,6 +82,18 @@ boolean_param("mwait-idle", opt_mwait_id =20 static unsigned int mwait_substates; =20 +/* + * Some platforms come with mutually exclusive C-states, so that if one is + * enabled, the other C-states must not be used. Example: C1 and C1E on + * Sapphire Rapids platform. This parameter allows for selecting the + * preferred C-states among the groups of mutually exclusive C-states - the + * selected C-states will be registered, the other C-states from the mutua= lly + * exclusive group won't be registered. If the platform has no mutually + * exclusive C-states, this parameter has no effect. + */ +static unsigned int __ro_after_init preferred_states_mask; +integer_param("preferred-cstates", preferred_states_mask); + #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF /* Reliable LAPIC Timer States, bit 1 for C1 etc. Default to only C1. */ static unsigned int lapic_timer_reliable_states =3D (1 << 1); @@ -96,6 +108,7 @@ struct idle_cpu { unsigned long auto_demotion_disable_flags; bool byt_auto_demotion_disable_flag; bool disable_promotion_to_c1e; + bool enable_promotion_to_c1e; }; =20 static const struct idle_cpu *icpu; @@ -924,6 +937,15 @@ static void cf_check byt_auto_demotion_d wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0); } =20 +static void cf_check c1e_promotion_enable(void *dummy) +{ + uint64_t msr_bits; + + rdmsrl(MSR_IA32_POWER_CTL, msr_bits); + msr_bits |=3D 0x2; + wrmsrl(MSR_IA32_POWER_CTL, msr_bits); +} + static void cf_check c1e_promotion_disable(void *dummy) { u64 msr_bits; @@ -1241,6 +1263,26 @@ static void __init skx_idle_state_table_ } =20 /* + * spr_idle_state_table_update - Adjust Sapphire Rapids idle states table. + */ +static void __init spr_idle_state_table_update(void) +{ + /* Check if user prefers C1E over C1. */ + if (preferred_states_mask & BIT(2, U)) { + if (preferred_states_mask & BIT(1, U)) + /* Both can't be enabled, stick to the defaults. */ + return; + + spr_cstates[0].flags |=3D CPUIDLE_FLAG_DISABLED; + spr_cstates[1].flags &=3D ~CPUIDLE_FLAG_DISABLED; + + /* Request enabling C1E using the "C1E promotion" bit. */ + idle_cpu_spr.disable_promotion_to_c1e =3D false; + idle_cpu_spr.enable_promotion_to_c1e =3D true; + } +} + +/* * mwait_idle_state_table_update() * * Update the default state_table for this CPU-id @@ -1261,6 +1303,9 @@ static void __init mwait_idle_state_tabl case INTEL_FAM6_SKYLAKE_X: skx_idle_state_table_update(); break; + case INTEL_FAM6_SAPPHIRERAPIDS_X: + spr_idle_state_table_update(); + break; } } =20 @@ -1402,6 +1447,8 @@ static int cf_check mwait_idle_cpu_init( =20 if (icpu->disable_promotion_to_c1e) on_selected_cpus(cpumask_of(cpu), c1e_promotion_disable, NULL, 1); + else if (icpu->enable_promotion_to_c1e) + on_selected_cpus(cpumask_of(cpu), c1e_promotion_enable, NULL, 1); =20 return NOTIFY_DONE; } From nobody Fri Nov 29 02:51:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" From: Artem Bityutskiy Add a Sapphire Rapids Xeon C6 optimization, similar to what we have for Sky= Lake Xeon: if package C6 is disabled, adjust C6 exit latency and target residenc= y to match core C6 values, instead of using the default package C6 values. Signed-off-by: Artem Bityutskiy Signed-off-by: Rafael J. Wysocki Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 3a= 9cf77b60dc Make sure a contradictory "preferred-cstates" wouldn't cause bypassing of the added logic. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1267,12 +1267,12 @@ static void __init skx_idle_state_table_ */ static void __init spr_idle_state_table_update(void) { - /* Check if user prefers C1E over C1. */ - if (preferred_states_mask & BIT(2, U)) { - if (preferred_states_mask & BIT(1, U)) - /* Both can't be enabled, stick to the defaults. */ - return; + uint64_t msr; =20 + /* Check if user prefers C1E over C1. */ + if (preferred_states_mask & BIT(2, U) && + /* Both can't be enabled, stick to the defaults. */ + !(preferred_states_mask & BIT(1, U))) { spr_cstates[0].flags |=3D CPUIDLE_FLAG_DISABLED; spr_cstates[1].flags &=3D ~CPUIDLE_FLAG_DISABLED; =20 @@ -1280,6 +1280,19 @@ static void __init spr_idle_state_table_ idle_cpu_spr.disable_promotion_to_c1e =3D false; idle_cpu_spr.enable_promotion_to_c1e =3D true; } + + /* + * By default, the C6 state assumes the worst-case scenario of package + * C6. However, if PC6 is disabled, we update the numbers to match + * core C6. + */ + rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr); + + /* Limit value 2 and above allow for PC6. */ + if ((msr & 0x7) < 2) { + spr_cstates[2].exit_latency =3D 190; + spr_cstates[2].target_residency =3D 600; + } } =20 /*