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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id z8-20020a2e8e88000000b002d0ae22ff6fsm920883ljk.60.2024.02.26.09.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Feb 2024 09:39:31 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 00810cc9-d4ce-11ee-98f5-efadbce2ee36 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708969172; x=1709573972; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZCwX2BCVLI3lXZG2aWqhyu9yA4jHT6KSlCqY/yiMy5E=; b=K/kySB9bH365FzkmKtciJtjl/bChluXtD5NzaZUBJOnrbnsA13m1v/u0lm3yFwmVdT cI8MzwEZDkBcSS2shR7UwfxYY2iilMxrx4aegYCn1sIJRU9Nt9y/sAYAE/DT6G/FJxyX pVryFglifIHpUKh2cioHqHHS2KCPgZHxxuCAHwUZ8a9oGoQQ562d3kGLcddz5otTujyZ mYamKUxar86TzD4ESrMbBgSNrnvaPxcnJ1PkaTWAH1VvrJQsnnABpQDBVvlDZs4xcHtY R/m6BRuoufVY6/fDHvzmkfVT+zu8HrZF5RAnmtP5uxCOD/Bbq13a5/AqZvGVL+bE6h2/ AxlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708969172; x=1709573972; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZCwX2BCVLI3lXZG2aWqhyu9yA4jHT6KSlCqY/yiMy5E=; b=XWQrz3KhfBvE03ETxFDFUqPzOUAaN1RM7/vEGftFCc3VO/KSdOv8iEvdS5F6p/orft NAD/sONDJT8RnE8Zh8e0XM0004OH4V9HLH4dfEsG0DA+3G1VApTZd+07AUGrZMUKTC1F Sf7vw4jVNhO9zFCMOg5ihq+EyMGxs+vr8k0EpmGtpd86eG4gvPV98gzw+28xFcEBhWi1 GH4pxjKEEtTO7UXbJeV+yAiq7rYc5jdve0TsW+9SCCeDW/e9R7WJgiuMbasXo1xfuUk+ DDpsbAa5vQRlIC3baJWA4F7b/VtHYs5Mlguiq9WwnANhBPoSQHj2KWbrRJYuJeGAswos jc0g== X-Gm-Message-State: AOJu0YzJs+LhGhInKPNcXf1m+Hj9/1DkmFYaCsXsKvwZs6D27Sq+czz2 74QCbwnSYvKhzbIh2S7Xq+SriFeUzG9yX+tQBPluqjg98H/qhytkx05lWfSX X-Google-Smtp-Source: AGHT+IEahFH9d60CghpPN5UMUuIMNVwUJdv5YNlsA9M0tIHLvik4uJbaD6X9+1X5KU3flXH9J58e1g== X-Received: by 2002:a05:651c:2019:b0:2d2:29c2:e7ea with SMTP id s25-20020a05651c201900b002d229c2e7eamr4101847ljo.24.1708969172528; Mon, 26 Feb 2024 09:39:32 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu , Alistair Francis , Bob Eshleman , Connor Davis Subject: [PATCH v5 18/23] xen/riscv: add minimal stuff to processor.h to build full Xen Date: Mon, 26 Feb 2024 18:39:00 +0100 Message-ID: <4e1ee99a9ad71015b5e8860d20b63337b526d0e9.1708962629.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1708969934154100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Oleksii Kurochko --- Changes in V5: - Code style fixes. - drop introduced TOOLCHAIN_HAS_ZIHINTPAUSE and use as-insn instead and use as-insn istead. --- Changes in V4: - Change message -> subject in "Changes in V3" - Documentation about system requirement was added. In the future, it can = be checked if the extension is supported by system __riscv_isa_extension_available() ( https://gitlab.com/xen-pro= ject/people/olkur/xen/-/commit/737998e89ed305eb92059300c374dfa53d2143fa ) - update cpu_relax() function to check if __riscv_zihintpause is supported= by a toolchain - add conditional _zihintpause to -march if it is supported by a toolchain Changes in V3: - update the commit subject - rename get_processor_id to smp_processor_id - code style fixes - update the cpu_relax instruction: use pause instruction instead of div %= 0, %0, zero --- Changes in V2: - Nothing changed. Only rebase. --- docs/misc/riscv/booting.txt | 8 ++++++++ xen/arch/riscv/arch.mk | 8 +++++++- xen/arch/riscv/include/asm/processor.h | 23 +++++++++++++++++++++++ 3 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 docs/misc/riscv/booting.txt diff --git a/docs/misc/riscv/booting.txt b/docs/misc/riscv/booting.txt new file mode 100644 index 0000000000..38fad74956 --- /dev/null +++ b/docs/misc/riscv/booting.txt @@ -0,0 +1,8 @@ +System requirements +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The following extensions are expected to be supported by a system on which +Xen is run: +- Zihintpause: + On a system that doesn't have this extension, cpu_relax() should be + implemented properly. Otherwise, an illegal instruction exception will a= rise. diff --git a/xen/arch/riscv/arch.mk b/xen/arch/riscv/arch.mk index 8403f96b6f..fabe323ec5 100644 --- a/xen/arch/riscv/arch.mk +++ b/xen/arch/riscv/arch.mk @@ -5,6 +5,12 @@ $(call cc-options-add,CFLAGS,CC,$(EMBEDDED_EXTRA_CFLAGS)) =20 CFLAGS-$(CONFIG_RISCV_64) +=3D -mabi=3Dlp64 =20 +ifeq ($(CONFIG_RISCV_64),y) +has_zihintpause =3D $(call as-insn,$(CC) -mabi=3Dlp64 -march=3Drv64i_zihin= tpause, "pause",_zihintpause,) +else +has_zihintpause =3D $(call as-insn,$(CC) -mabi=3Dilp32 -march=3Drv32i_zihi= ntpause, "pause",_zihintpause,) +endif + riscv-march-$(CONFIG_RISCV_ISA_RV64G) :=3D rv64g riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c =20 @@ -12,7 +18,7 @@ riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-marc= h-y)c # into the upper half _or_ the lower half of the address space. # -mcmodel=3Dmedlow would force Xen into the lower half. =20 -CFLAGS +=3D -march=3D$(riscv-march-y) -mstrict-align -mcmodel=3Dmedany +CFLAGS +=3D -march=3D$(riscv-march-y)$(has_zihintpause) -mstrict-align -mc= model=3Dmedany =20 # TODO: Drop override when more of the build is working override ALL_OBJS-y =3D arch/$(SRCARCH)/built_in.o diff --git a/xen/arch/riscv/include/asm/processor.h b/xen/arch/riscv/includ= e/asm/processor.h index 6db681d805..b96af07660 100644 --- a/xen/arch/riscv/include/asm/processor.h +++ b/xen/arch/riscv/include/asm/processor.h @@ -12,6 +12,9 @@ =20 #ifndef __ASSEMBLY__ =20 +/* TODO: need to be implemeted */ +#define smp_processor_id() 0 + /* On stack VCPU state */ struct cpu_user_regs { @@ -53,6 +56,26 @@ struct cpu_user_regs unsigned long pregs; }; =20 +/* TODO: need to implement */ +#define cpu_to_core(cpu) (0) +#define cpu_to_socket(cpu) (0) + +static inline void cpu_relax(void) +{ +#ifdef __riscv_zihintpause + /* + * Reduce instruction retirement. + * This assumes the PC changes. + */ + __asm__ __volatile__ ( "pause" ); +#else + /* Encoding of the pause instruction */ + __asm__ __volatile__ ( ".insn 0x100000F" ); +#endif + + barrier(); +} + static inline void wfi(void) { __asm__ __volatile__ ("wfi"); --=20 2.43.0