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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4834d5ebd1bsm303288185e9.6.2026.02.13.08.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Feb 2026 08:29:16 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 244823da-08f9-11f1-b163-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1771000157; x=1771604957; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g8aUJGUOJbQQ949TKJQepHTgKcmZAnEVr+LIZcPPPBc=; b=KkL7LK5dQ5g8FSkC6xwQI1ZqKu2evG06cl65FD/eGd6huINpxEtHMABnYwejVV5bFM PedOhtEbYOkEzcsCDtQyaoiNQrH+zsoA3C/8Xc/H5Z8BphJbswnezVQ1NXHsYTTwWZby vIFXVCjl6sWHkASFas1x2urQQTIoIB/VFhUt15uRbR1jkwhD3DjgiesWjVf81LVMt7Sn og6kA8D0bGSuMjdCAGJXkUYtrOvt9WXy91CgYLm7hPuNS3Gi6Z7KMLzXgKQJNhYgSn0c RMDsITiMTlPgY0S5zc6w7GNQ018qw+FvDjf4y897LEJi+j8L0l+uhTr8lVNkwWmczUVs xeiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771000157; x=1771604957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=g8aUJGUOJbQQ949TKJQepHTgKcmZAnEVr+LIZcPPPBc=; b=g2U541nKNuUhbGzKFTRkvkUbc7W7ZgPf/tbKWIA1bZF6pycmUnSSDIox34ztqcbYOK uxsx545SPZdH8IMKuX2pFKcTlLY2uBJ45bATrld+gtzbeg7GCBwT5Ie67x+Ix1jxxIgg yuunn7bcE4tXGK3VxhrjZJ5gGxPnX9t8RNpeeCljGm0ea+O/9NTkRv+qmA4BSyV+j2V5 joZyAYg/ha+iGH6divNyDGySosxZdqCypxcVjvIk9eqia0jl9M+Y2bXfMkNWM9VeAW/n QVPQ2Eaz6L4FxPnwxKlgSAkrp0d55nr//Mt8fo6H60AfFUXBwhWJohXoKxdu+ojsIyu0 Oxmg== X-Gm-Message-State: AOJu0YwxanxZ8lSkDeaSiM4kV7Rnfc0BazuioEp6ZkmsTdIraNQJ7B2/ acK6rKjt7GSiG0gjRiZYlwi4t2J5XOSMONeFQAeqt6Csk0bxbibDUw/7qvCH1mJS X-Gm-Gg: AZuq6aIfnIZGLNvbGgGVzPQNDOOcw/nl8DBDgWPrfReGyab9lnHMs4a/SsvVLtXnb5q 3xl1ighMHKS5I0SWK9pRH3PSIWlGfWJGo8LISFCovnLZYp4ju0zqabsiMS0Jow+34taVYm7Ud52 4bGDWydH7vtsJuwEcWURzM7tzBk/aQgrvVki4H/naeXw+PhlJQdmhJA9aBjRUJkMp0uSSVeLgk1 PzZkfpolEnFMpTQO9yZ+CrhxocpCctcsaC+I1hMnm7RnmqnQz/FTRQ667DANwKEgegESE2OUuza iFkcqwhtBaRr0eVpd43mZ0dJisFDysTXaOfcTjPLF0P9GQeAGlryA/0DWm6xEvm3osh1LKwy6Lu nOZ4raD2kggsjYMso1HF1M4dTwDvb1GOthyPrgUc/L16x9pfpDjqI9oX20+z4s8o/HGdqDKvv+g uZghj8uJv6HmISMAw5j26kWAtFowy1a15Sf0rgpcV5PCUN1Celvmw/UfFi2duDfSo/+Q== X-Received: by 2002:a05:600c:19cc:b0:477:7f4a:44b4 with SMTP id 5b1f17b1804b1-483739fc385mr40414865e9.1.1771000156728; Fri, 13 Feb 2026 08:29:16 -0800 (PST) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v4 06/16] xen/riscv: introduce tracking of pending vCPU interrupts, part 2 Date: Fri, 13 Feb 2026 17:28:52 +0100 Message-ID: <4e10c95d883c0d447b9e33a6d6a92e911aed6a23.1770999383.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1771000187538154100 Content-Type: text/plain; charset="utf-8" This patch is based on Linux kernel 6.16.0. Add the consumer side (vcpu_flush_interrupts()) of the lockless pending interrupt tracking introduced in part 1 (for producers). According, to the design only one consumer is possible, and it is vCPU itself. vcpu_flush_interrupts() is expected to be ran (as guests aren't ran now due to the lack of functionality) before the hypervisor returns control to the guest. Producers may set bits in irqs_pending_mask without a lock. Clearing bits in irqs_pending_mask is performed only by the consumer via xchg() (with aquire semantics). The consumer must not write to irqs_pending and must not act on bits that are not set in the mask. Otherwise, extra synchronization should be provided. The worst thing which could happen with such approach is that a new pending bit will be set to irqs_pending bitmap during update of hvip variable in vcpu_flush_interrupt() but it isn't problem as the new pending bit won't be lost and just be proceded during the next flush. As AIA specs introduced hviph register which would want to be updated when guest related AIA code vcpu_update_hvip() is introduced instead of just open-code it in vcpu_flush_interrupts(). Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v4: - Move defintion of hvip local variable to narrower space in vcpu_flush_interrupts(). - Use initializers for mask and val variables. - Use local variable c as an argument of vcpu_flush_interrupts() in check_for_pcpu_work(). --- Changes in v3: - Update the error message in case of RV32 from "hviph" to v->arch.hviph. - Make const argument of vcpu_update_hvip. - Move local variables mask and val inside if() in vcpu_flush_interrupts(). - Call vcpu_flush_interrupts() in check_pcpu_work(). - Move vcpu_update_hvip() inside if() in vcpu_flush_interrupts(). --- Changes in v2: - New patch. --- xen/arch/riscv/domain.c | 31 +++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/domain.h | 1 + xen/arch/riscv/traps.c | 2 ++ 3 files changed, 34 insertions(+) diff --git a/xen/arch/riscv/domain.c b/xen/arch/riscv/domain.c index edbac39a0b18..35d8d5db02d0 100644 --- a/xen/arch/riscv/domain.c +++ b/xen/arch/riscv/domain.c @@ -198,3 +198,34 @@ void vcpu_sync_interrupts(struct vcpu *v) # error "Update v->arch.vsieh" #endif } + +static void vcpu_update_hvip(const struct vcpu *v) +{ + csr_write(CSR_HVIP, v->arch.hvip); +} + +void vcpu_flush_interrupts(struct vcpu *v) +{ + if ( ACCESS_ONCE(v->arch.irqs_pending_mask[0]) ) + { + register_t *hvip =3D &v->arch.hvip; + + unsigned long mask =3D xchg(&v->arch.irqs_pending_mask[0], 0UL); + unsigned long val =3D ACCESS_ONCE(v->arch.irqs_pending[0]) & mask; + + *hvip &=3D ~mask; + *hvip |=3D val; + + vcpu_update_hvip(v); + } + +/* + * Flush AIA high interrupts. + * + * It is necessary to do only for CONFIG_RISCV_32 which isn't + * supported now. + */ +#ifdef CONFIG_RISCV_32 +# error "Update v->arch.hviph" +#endif +} diff --git a/xen/arch/riscv/include/asm/domain.h b/xen/arch/riscv/include/a= sm/domain.h index 2793f694d36f..5d25a884eea6 100644 --- a/xen/arch/riscv/include/asm/domain.h +++ b/xen/arch/riscv/include/asm/domain.h @@ -115,6 +115,7 @@ int vcpu_set_interrupt(struct vcpu *v, unsigned int irq= ); int vcpu_unset_interrupt(struct vcpu *v, unsigned int irq); =20 void vcpu_sync_interrupts(struct vcpu *v); +void vcpu_flush_interrupts(struct vcpu *v); =20 #endif /* ASM__RISCV__DOMAIN_H */ =20 diff --git a/xen/arch/riscv/traps.c b/xen/arch/riscv/traps.c index 366c3ff23e76..77738a01c8b5 100644 --- a/xen/arch/riscv/traps.c +++ b/xen/arch/riscv/traps.c @@ -174,6 +174,8 @@ static void check_for_pcpu_work(void) struct vcpu *c =3D current; =20 vcpu_sync_interrupts(c); + + vcpu_flush_interrupts(c); } =20 void do_trap(struct cpu_user_regs *cpu_regs) --=20 2.52.0