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([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a93c27d47a2sm150697966b.89.2024.09.27.09.33.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2024 09:33:27 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3a1fa2eb-7cee-11ef-a0ba-8be0dac302b0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1727454808; x=1728059608; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A74SThhYGpNGHbuzB0A5PnKvSwX2Icc/uEq6ULocwYc=; b=cdE5UvzGChYE8qVGYWnfGjM6SllAXULZWeL+6x4DFRMoO4656qsLwR7wHvlc0Af/J4 SpzfDR1k9QgGutqOmIgdahTYWbNxz6o/yQrxJ3/fOFUTzT5f3AmiEfeEHoCyc9G40ef3 WAF2Wz6rYN7JKQS/RxwbBFD1g7eQzV3mk+cHAeovjBwhc/x1y5mt3ZIJ7jraJMCAwr8V Nr7QuSQM1u0Fuwk0P2tHEM77oPbSpXBz17WorFqqBwa4asUj8nf53A1jMA/Lo0ICUUa2 1HFac829xkXKiv76dKR62EZQ2jh9upNJAvBzxIj5lpRbXYwMg9kHVSF5z8vuPhTvBQPT evmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1727454808; x=1728059608; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A74SThhYGpNGHbuzB0A5PnKvSwX2Icc/uEq6ULocwYc=; b=Ut5lENH2JUvHAfK5TXgSLYsfo/SwI3GFYY1miBugZ3F7L1Xrel5xb7+27l9ER9dwZ+ P9VopHJqGYs7Oyx/Zi+EeN9KAFKodYE/2X+FKun+rcKeAyqJLLk89A9McIGJG627zNIt cikTm1gQPRbks0Gn2M6fXTTOjNKRCLXPkWJ6e5pd7OlkWqwg4Cd/6yS+tyrhLaBkYXUB KPIRI3oixmbSJhkrgELh2gBw+JgINKZb7IAhT00zqUOMRuyE/cihe6phC8sPzgenSuaU Y1gy+sRQ9AVy3gJ6pdhmUSXFNs6JeqCloY4qXjulKlFily9UMKGGPx/srbUTUzWT/NWo CjOw== X-Gm-Message-State: AOJu0YwroomWKy4A/s30muaOJg4ZbrXEFR4IjYKKjTTpmm1ozo6O7mBp UhiCcUBsgaPNzpysnbnFnVl8NEDkYIehJcsEEFgXejMUS+XPDCedxmTL1w== X-Google-Smtp-Source: AGHT+IF051dFpVO8XlpMXfYgtd4R1pf5U3XwDtozp0fFwnpFoF7v1vlaYdcetKSqUDFEJlyAz0s5jQ== X-Received: by 2002:a5d:6310:0:b0:37c:cdbf:2cc0 with SMTP id ffacd0b85a97d-37cd5b15489mr3003878f8f.53.1727454807921; Fri, 27 Sep 2024 09:33:27 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Bob Eshleman , Connor Davis , Andrew Cooper , Jan Beulich , Julien Grall , Stefano Stabellini Subject: [PATCH v8 3/7] xen/riscv: introduce asm/pmap.h header Date: Fri, 27 Sep 2024 18:33:15 +0200 Message-ID: <4bfd2bfdb276f982420bac85c4b6f2da8c5f5367.1727449154.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.46.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1727454852232116600 Content-Type: text/plain; charset="utf-8" Introduce arch_pmap_{un}map functions and select HAS_PMAP for CONFIG_RISCV. Add pte_from_mfn() for use in arch_pmap_map(). Introduce flush_xen_tlb_one_local() and use it in arch_pmap_{un}map(). Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- xen/arch/riscv/Kconfig | 1 + xen/arch/riscv/include/asm/flushtlb.h | 6 +++++ xen/arch/riscv/include/asm/page.h | 6 +++++ xen/arch/riscv/include/asm/pmap.h | 36 +++++++++++++++++++++++++++ 4 files changed, 49 insertions(+) create mode 100644 xen/arch/riscv/include/asm/pmap.h diff --git a/xen/arch/riscv/Kconfig b/xen/arch/riscv/Kconfig index 7a113c7774..1858004676 100644 --- a/xen/arch/riscv/Kconfig +++ b/xen/arch/riscv/Kconfig @@ -3,6 +3,7 @@ config RISCV select FUNCTION_ALIGNMENT_16B select GENERIC_BUG_FRAME select HAS_DEVICE_TREE + select HAS_PMAP select HAS_VMAP =20 config RISCV_64 diff --git a/xen/arch/riscv/include/asm/flushtlb.h b/xen/arch/riscv/include= /asm/flushtlb.h index 7ce32bea0b..f4a735fd6c 100644 --- a/xen/arch/riscv/include/asm/flushtlb.h +++ b/xen/arch/riscv/include/asm/flushtlb.h @@ -5,6 +5,12 @@ #include #include =20 +/* Flush TLB of local processor for address va. */ +static inline void flush_tlb_one_local(vaddr_t va) +{ + asm volatile ( "sfence.vma %0" :: "r" (va) : "memory" ); +} + /* * Filter the given set of CPUs, removing those that definitely flushed th= eir * TLB since @page_timestamp. diff --git a/xen/arch/riscv/include/asm/page.h b/xen/arch/riscv/include/asm= /page.h index d4a5009823..eb79cb9409 100644 --- a/xen/arch/riscv/include/asm/page.h +++ b/xen/arch/riscv/include/asm/page.h @@ -94,6 +94,12 @@ static inline pte_t read_pte(const pte_t *p) return read_atomic(p); } =20 +static inline pte_t pte_from_mfn(mfn_t mfn, unsigned int flags) +{ + unsigned long pte =3D (mfn_x(mfn) << PTE_PPN_SHIFT) | flags; + return (pte_t){ .pte =3D pte }; +} + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PAGE_H */ diff --git a/xen/arch/riscv/include/asm/pmap.h b/xen/arch/riscv/include/asm= /pmap.h new file mode 100644 index 0000000000..60065c996f --- /dev/null +++ b/xen/arch/riscv/include/asm/pmap.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef ASM_PMAP_H +#define ASM_PMAP_H + +#include +#include +#include +#include + +#include +#include +#include + +static inline void __init arch_pmap_map(unsigned int slot, mfn_t mfn) +{ + pte_t *entry =3D &xen_fixmap[slot]; + pte_t pte; + + ASSERT(!pte_is_valid(*entry)); + + pte =3D pte_from_mfn(mfn, PAGE_HYPERVISOR_RW); + write_pte(entry, pte); + + flush_tlb_one_local(FIXMAP_ADDR(slot)); +} + +static inline void __init arch_pmap_unmap(unsigned int slot) +{ + pte_t pte =3D {}; + + write_pte(&xen_fixmap[slot], pte); + + flush_tlb_one_local(FIXMAP_ADDR(slot)); +} + +#endif /* ASM_PMAP_H */ --=20 2.46.1