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Wed, 7 Aug 2019 09:25:37 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 01/26] configure: Define TARGET_ALIGNED_ONLY Thread-Index: AQHVTPmwA9I8SFw7ZEyFe+TCySKK0g== Date: Wed, 7 Aug 2019 08:25:37 +0000 Message-ID: <1565166336833.46550@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.74 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 01/26] configure: Define TARGET_ALIGNED_ONLY X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Rename ALIGNED_ONLY to TARGET_ALIGNED_ONLY for clarity and move defines out of target/foo/cpu.h into configure, as we do with TARGET_WORDS_BIGENDIAN, so that it is always defined early. Poisoned TARGET_ALIGNED_ONLY to prevent use in common code. Signed-off-by: Tony Nguyen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Aleksandar Markovic Reviewed-by: Cornelia Huck --- configure | 10 +++++++++- include/exec/poison.h | 1 + include/qom/cpu.h | 2 +- target/alpha/cpu.h | 2 -- target/hppa/cpu.h | 1 - target/mips/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- tcg/tcg.c | 2 +- tcg/tcg.h | 8 +++++--- 11 files changed, 17 insertions(+), 17 deletions(-) diff --git a/configure b/configure index 714e7fb..482ba0b 100755 --- a/configure +++ b/configure @@ -7431,8 +7431,13 @@ for target in $target_list; do target_dir=3D"$target" config_target_mak=3D$target_dir/config-target.mak target_name=3D$(echo $target | cut -d '-' -f 1) +target_aligned_only=3D"no" +case "$target_name" in + alpha|hppa|mips64el|mips64|mipsel|mips|mipsn32|mipsn32el|sh4|sh4eb|sparc= |sparc64|sparc32plus|xtensa|xtensaeb) + target_aligned_only=3D"yes" + ;; +esac target_bigendian=3D"no" - case "$target_name" in armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1= k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb) target_bigendian=3Dyes @@ -7717,6 +7722,9 @@ fi if supported_whpx_target $target; then echo "CONFIG_WHPX=3Dy" >> $config_target_mak fi +if test "$target_aligned_only" =3D "yes" ; then + echo "TARGET_ALIGNED_ONLY=3Dy" >> $config_target_mak +fi if test "$target_bigendian" =3D "yes" ; then echo "TARGET_WORDS_BIGENDIAN=3Dy" >> $config_target_mak fi diff --git a/include/exec/poison.h b/include/exec/poison.h index b862320..955eb86 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,6 +35,7 @@ #pragma GCC poison TARGET_UNICORE32 #pragma GCC poison TARGET_XTENSA +#pragma GCC poison TARGET_ALIGNED_ONLY #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_SUPPORTS_MTTCG diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 5ee0046..9b50b73 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -89,7 +89,7 @@ struct TranslationBlock; * @do_unassigned_access: Callback for unassigned access handling. * (this is deprecated: new targets should use do_transaction_failed inste= ad) * @do_unaligned_access: Callback for unaligned access handling, if - * the target defines #ALIGNED_ONLY. + * the target defines #TARGET_ALIGNED_ONLY. * @do_transaction_failed: Callback for handling failed memory transactions * (ie bus faults or external aborts; not MMU faults) * @virtio_is_big_endian: Callback to return %true if a CPU which supports diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index b3e8a82..16eb804 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -23,8 +23,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define ALIGNED_ONLY - /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index aab251b..2be67c2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -30,7 +30,6 @@ basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL -#define ALIGNED_ONLY #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 #define MMU_PHYS_IDX 4 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 21c0615..c13cd4e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1,8 +1,6 @@ #ifndef MIPS_CPU_H #define MIPS_CPU_H -#define ALIGNED_ONLY - #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index aee733e..ecaa7a1 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -23,8 +23,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define ALIGNED_ONLY - /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) #define SH_CPU_SH7750S (1 << 1) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 8ed2250..1406f0b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -5,8 +5,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define ALIGNED_ONLY - #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 #else diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 2c27713..0459243 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -32,8 +32,6 @@ #include "exec/cpu-defs.h" #include "xtensa-isa.h" -#define ALIGNED_ONLY - /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/tcg/tcg.c b/tcg/tcg.c index be2c33c..8d23fb0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1926,7 +1926,7 @@ static const char * const ldst_name[] =3D }; static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] =3D { -#ifdef ALIGNED_ONLY +#ifdef TARGET_ALIGNED_ONLY [MO_UNALN >> MO_ASHIFT] =3D "un+", [MO_ALIGN >> MO_ASHIFT] =3D "", #else diff --git a/tcg/tcg.h b/tcg/tcg.h index b411e17..529acb2 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -333,10 +333,12 @@ typedef enum TCGMemOp { MO_TE =3D MO_LE, #endif - /* MO_UNALN accesses are never checked for alignment. + /* + * MO_UNALN accesses are never checked for alignment. * MO_ALIGN accesses will result in a call to the CPU's * do_unaligned_access hook if the guest address is not aligned. - * The default depends on whether the target CPU defines ALIGNED_ONLY. + * The default depends on whether the target CPU defines + * TARGET_ALIGNED_ONLY. * * Some architectures (e.g. ARMv8) need the address which is aligned * to a size more than the size of the memory access. @@ -353,7 +355,7 @@ typedef enum TCGMemOp { */ MO_ASHIFT =3D 4, MO_AMASK =3D 7 << MO_ASHIFT, -#ifdef ALIGNED_ONLY +#ifdef TARGET_ALIGNED_ONLY MO_ALIGN =3D 0, MO_UNALN =3D MO_AMASK, #else -- 1.8.3.1 From nobody Sat Apr 20 01:08:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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X-Received-From: 62.239.224.237 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 02/26] tcg: TCGMemOp is now accelerator independent MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Preparation for collapsing the two byte swaps, adjust_endianness and handle_bswap, along the I/O path. Target dependant attributes are conditionalize upon NEED_CPU_H. Signed-off-by: Tony Nguyen Acked-by: David Gibson Reviewed-by: Richard Henderson Acked-by: Cornelia Huck --- MAINTAINERS | 1 + accel/tcg/cputlb.c | 2 +- include/exec/memop.h | 110 ++++++++++++++++++++++++++ target/alpha/translate.c | 2 +- target/arm/translate-a64.c | 48 ++++++------ target/arm/translate-a64.h | 2 +- target/arm/translate-sve.c | 2 +- target/arm/translate.c | 32 ++++---- target/arm/translate.h | 2 +- target/hppa/translate.c | 14 ++-- target/i386/translate.c | 132 ++++++++++++++++------------= ---- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 4 +- target/mips/translate.c | 8 +- target/openrisc/translate.c | 4 +- target/ppc/translate.c | 12 +-- target/riscv/insn_trans/trans_rva.inc.c | 8 +- target/riscv/insn_trans/trans_rvi.inc.c | 4 +- target/s390x/translate.c | 6 +- target/s390x/translate_vx.inc.c | 10 +-- target/sparc/translate.c | 14 ++-- target/tilegx/translate.c | 10 +-- target/tricore/translate.c | 8 +- tcg/README | 2 +- tcg/aarch64/tcg-target.inc.c | 26 +++---- tcg/arm/tcg-target.inc.c | 26 +++---- tcg/i386/tcg-target.inc.c | 24 +++--- tcg/mips/tcg-target.inc.c | 16 ++-- tcg/optimize.c | 2 +- tcg/ppc/tcg-target.inc.c | 12 +-- tcg/riscv/tcg-target.inc.c | 20 ++--- tcg/s390/tcg-target.inc.c | 14 ++-- tcg/sparc/tcg-target.inc.c | 6 +- tcg/tcg-op.c | 38 ++++----- tcg/tcg-op.h | 86 ++++++++++----------- tcg/tcg.c | 2 +- tcg/tcg.h | 101 ++---------------------- trace/mem-internal.h | 4 +- trace/mem.h | 4 +- 39 files changed, 421 insertions(+), 399 deletions(-) create mode 100644 include/exec/memop.h diff --git a/MAINTAINERS b/MAINTAINERS index d6de200..c7cf84a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1889,6 +1889,7 @@ M: Paolo Bonzini S: Supported F: include/exec/ioport.h F: ioport.c +F: include/exec/memop.h F: include/exec/memory.h F: include/exec/ram_addr.h F: memory.c diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index bb9897b..523be4c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1133,7 +1133,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, uintptr_t index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); target_ulong tlb_addr =3D tlb_addr_write(tlbe); - TCGMemOp mop =3D get_memop(oi); + MemOp mop =3D get_memop(oi); int a_bits =3D get_alignment_bits(mop); int s_bits =3D mop & MO_SIZE; void *hostaddr; diff --git a/include/exec/memop.h b/include/exec/memop.h new file mode 100644 index 0000000..7262ca3 --- /dev/null +++ b/include/exec/memop.h @@ -0,0 +1,110 @@ +/* + * Constants for memory operations + * + * Authors: + * Richard Henderson + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef MEMOP_H +#define MEMOP_H + +typedef enum MemOp { + MO_8 =3D 0, + MO_16 =3D 1, + MO_32 =3D 2, + MO_64 =3D 3, + MO_SIZE =3D 3, /* Mask for the above. */ + + MO_SIGN =3D 4, /* Sign-extended, otherwise zero-extended. */ + + MO_BSWAP =3D 8, /* Host reverse endian. */ +#ifdef HOST_WORDS_BIGENDIAN + MO_LE =3D MO_BSWAP, + MO_BE =3D 0, +#else + MO_LE =3D 0, + MO_BE =3D MO_BSWAP, +#endif +#ifdef NEED_CPU_H +#ifdef TARGET_WORDS_BIGENDIAN + MO_TE =3D MO_BE, +#else + MO_TE =3D MO_LE, +#endif +#endif + + /* + * MO_UNALN accesses are never checked for alignment. + * MO_ALIGN accesses will result in a call to the CPU's + * do_unaligned_access hook if the guest address is not aligned. + * The default depends on whether the target CPU defines + * TARGET_ALIGNED_ONLY. + * + * Some architectures (e.g. ARMv8) need the address which is aligned + * to a size more than the size of the memory access. + * Some architectures (e.g. SPARCv9) need an address which is aligned, + * but less strictly than the natural alignment. + * + * MO_ALIGN supposes the alignment size is the size of a memory access. + * + * There are three options: + * - unaligned access permitted (MO_UNALN). + * - an alignment to the size of an access (MO_ALIGN); + * - an alignment to a specified size, which may be more or less than + * the access size (MO_ALIGN_x where 'x' is a size in bytes); + */ + MO_ASHIFT =3D 4, + MO_AMASK =3D 7 << MO_ASHIFT, +#ifdef NEED_CPU_H +#ifdef TARGET_ALIGNED_ONLY + MO_ALIGN =3D 0, + MO_UNALN =3D MO_AMASK, +#else + MO_ALIGN =3D MO_AMASK, + MO_UNALN =3D 0, +#endif +#endif + MO_ALIGN_2 =3D 1 << MO_ASHIFT, + MO_ALIGN_4 =3D 2 << MO_ASHIFT, + MO_ALIGN_8 =3D 3 << MO_ASHIFT, + MO_ALIGN_16 =3D 4 << MO_ASHIFT, + MO_ALIGN_32 =3D 5 << MO_ASHIFT, + MO_ALIGN_64 =3D 6 << MO_ASHIFT, + + /* Combinations of the above, for ease of use. */ + MO_UB =3D MO_8, + MO_UW =3D MO_16, + MO_UL =3D MO_32, + MO_SB =3D MO_SIGN | MO_8, + MO_SW =3D MO_SIGN | MO_16, + MO_SL =3D MO_SIGN | MO_32, + MO_Q =3D MO_64, + + MO_LEUW =3D MO_LE | MO_UW, + MO_LEUL =3D MO_LE | MO_UL, + MO_LESW =3D MO_LE | MO_SW, + MO_LESL =3D MO_LE | MO_SL, + MO_LEQ =3D MO_LE | MO_Q, + + MO_BEUW =3D MO_BE | MO_UW, + MO_BEUL =3D MO_BE | MO_UL, + MO_BESW =3D MO_BE | MO_SW, + MO_BESL =3D MO_BE | MO_SL, + MO_BEQ =3D MO_BE | MO_Q, + +#ifdef NEED_CPU_H + MO_TEUW =3D MO_TE | MO_UW, + MO_TEUL =3D MO_TE | MO_UL, + MO_TESW =3D MO_TE | MO_SW, + MO_TESL =3D MO_TE | MO_SL, + MO_TEQ =3D MO_TE | MO_Q, +#endif + + MO_SSIZE =3D MO_SIZE | MO_SIGN, +} MemOp; + +#endif diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 2c9cccf..d5d4888 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -403,7 +403,7 @@ static inline void gen_store_mem(DisasContext *ctx, static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int = rb, int32_t disp16, int mem_idx, - TCGMemOp op) + MemOp op) { TCGLabel *lab_fail, *lab_done; TCGv addr, val; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d323147..b6c07d6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -85,7 +85,7 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); -typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemO= p); +typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); /* initialize TCG globals. */ void a64_translate_init(void) @@ -455,7 +455,7 @@ TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int = sf) * Dn, Sn, Hn or Bn). * (Note that this is not the same mapping as for A32; see cpu.h) */ -static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) +static inline int fp_reg_offset(DisasContext *s, int regno, MemOp size) { return vec_reg_offset(s, regno, 0, size); } @@ -871,7 +871,7 @@ static void do_gpr_ld_memidx(DisasContext *s, bool iss_valid, unsigned int iss_srt, bool iss_sf, bool iss_ar) { - TCGMemOp memop =3D s->be_data + size; + MemOp memop =3D s->be_data + size; g_assert(size <=3D 3); @@ -948,7 +948,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv= _i64 tcg_addr, int size) TCGv_i64 tmphi; if (size < 4) { - TCGMemOp memop =3D s->be_data + size; + MemOp memop =3D s->be_data + size; tmphi =3D tcg_const_i64(0); tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); } else { @@ -989,7 +989,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv= _i64 tcg_addr, int size) /* Get value of an element within a vector register */ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcid= x, - int element, TCGMemOp memop) + int element, MemOp memop) { int vect_off =3D vec_reg_offset(s, srcidx, element, memop & MO_SIZE); switch (memop) { @@ -1021,7 +1021,7 @@ static void read_vec_element(DisasContext *s, TCGv_i6= 4 tcg_dest, int srcidx, } static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int s= rcidx, - int element, TCGMemOp memop) + int element, MemOp memop) { int vect_off =3D vec_reg_offset(s, srcidx, element, memop & MO_SIZE); switch (memop) { @@ -1048,7 +1048,7 @@ static void read_vec_element_i32(DisasContext *s, TCG= v_i32 tcg_dest, int srcidx, /* Set value of an element within a vector register */ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int desti= dx, - int element, TCGMemOp memop) + int element, MemOp memop) { int vect_off =3D vec_reg_offset(s, destidx, element, memop & MO_SIZE); switch (memop) { @@ -1070,7 +1070,7 @@ static void write_vec_element(DisasContext *s, TCGv_i= 64 tcg_src, int destidx, } static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, - int destidx, int element, TCGMemOp memop) + int destidx, int element, MemOp memop) { int vect_off =3D vec_reg_offset(s, destidx, element, memop & MO_SIZE); switch (memop) { @@ -1090,7 +1090,7 @@ static void write_vec_element_i32(DisasContext *s, TC= Gv_i32 tcg_src, /* Store from vector register to memory */ static void do_vec_st(DisasContext *s, int srcidx, int element, - TCGv_i64 tcg_addr, int size, TCGMemOp endian) + TCGv_i64 tcg_addr, int size, MemOp endian) { TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); @@ -1102,7 +1102,7 @@ static void do_vec_st(DisasContext *s, int srcidx, in= t element, /* Load from memory to vector register */ static void do_vec_ld(DisasContext *s, int destidx, int element, - TCGv_i64 tcg_addr, int size, TCGMemOp endian) + TCGv_i64 tcg_addr, int size, MemOp endian) { TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); @@ -2200,7 +2200,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, TCGv_i64 addr, int size, bool is_pair) { int idx =3D get_mem_index(s); - TCGMemOp memop =3D s->be_data; + MemOp memop =3D s->be_data; g_assert(size <=3D 3); if (is_pair) { @@ -3286,7 +3286,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) bool is_postidx =3D extract32(insn, 23, 1); bool is_q =3D extract32(insn, 30, 1); TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; - TCGMemOp endian =3D s->be_data; + MemOp endian =3D s->be_data; int ebytes; /* bytes per element */ int elements; /* elements per vector */ @@ -5455,7 +5455,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t i= nsn) unsigned int mos, type, rm, cond, rn, rd; TCGv_i64 t_true, t_false, t_zero; DisasCompare64 c; - TCGMemOp sz; + MemOp sz; mos =3D extract32(insn, 29, 3); type =3D extract32(insn, 22, 2); @@ -6267,7 +6267,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t in= sn) int mos =3D extract32(insn, 29, 3); uint64_t imm; TCGv_i64 tcg_res; - TCGMemOp sz; + MemOp sz; if (mos || imm5) { unallocated_encoding(s); @@ -7030,7 +7030,7 @@ static TCGv_i32 do_reduction_op(DisasContext *s, int = fpopcode, int rn, { if (esize =3D=3D size) { int element; - TCGMemOp msize =3D esize =3D=3D 16 ? MO_16 : MO_32; + MemOp msize =3D esize =3D=3D 16 ? MO_16 : MO_32; TCGv_i32 tcg_elem; /* We should have one register left here */ @@ -8022,7 +8022,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, int shift =3D (2 * esize) - immhb; int elements =3D is_scalar ? 1 : (64 / esize); bool round =3D extract32(opcode, 0, 1); - TCGMemOp ldop =3D (size + 1) | (is_u_shift ? 0 : MO_SIGN); + MemOp ldop =3D (size + 1) | (is_u_shift ? 0 : MO_SIGN); TCGv_i64 tcg_rn, tcg_rd, tcg_round; TCGv_i32 tcg_rd_narrowed; TCGv_i64 tcg_final; @@ -8181,7 +8181,7 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, } }; NeonGenTwoOpEnvFn *genfn =3D fns[src_unsigned][dst_unsigned][size]; - TCGMemOp memop =3D scalar ? size : MO_32; + MemOp memop =3D scalar ? size : MO_32; int maxpass =3D scalar ? 1 : is_q ? 4 : 2; for (pass =3D 0; pass < maxpass; pass++) { @@ -8225,7 +8225,7 @@ static void handle_simd_intfp_conv(DisasContext *s, i= nt rd, int rn, TCGv_ptr tcg_fpst =3D get_fpstatus_ptr(size =3D=3D MO_16); TCGv_i32 tcg_shift =3D NULL; - TCGMemOp mop =3D size | (is_signed ? MO_SIGN : 0); + MemOp mop =3D size | (is_signed ? MO_SIGN : 0); int pass; if (fracbits || size =3D=3D MO_64) { @@ -10004,7 +10004,7 @@ static void handle_vec_simd_shri(DisasContext *s, b= ool is_q, bool is_u, int dsize =3D is_q ? 128 : 64; int esize =3D 8 << size; int elements =3D dsize/esize; - TCGMemOp memop =3D size | (is_u ? 0 : MO_SIGN); + MemOp memop =3D size | (is_u ? 0 : MO_SIGN); TCGv_i64 tcg_rn =3D new_tmp_a64(s); TCGv_i64 tcg_rd =3D new_tmp_a64(s); TCGv_i64 tcg_round; @@ -10347,7 +10347,7 @@ static void handle_3rd_widening(DisasContext *s, in= t is_q, int is_u, int size, TCGv_i64 tcg_op1 =3D tcg_temp_new_i64(); TCGv_i64 tcg_op2 =3D tcg_temp_new_i64(); TCGv_i64 tcg_passres; - TCGMemOp memop =3D MO_32 | (is_u ? 0 : MO_SIGN); + MemOp memop =3D MO_32 | (is_u ? 0 : MO_SIGN); int elt =3D pass + is_q * 2; @@ -11827,7 +11827,7 @@ static void handle_2misc_pairwise(DisasContext *s, = int opcode, bool u, if (size =3D=3D 2) { /* 32 + 32 -> 64 op */ - TCGMemOp memop =3D size + (u ? 0 : MO_SIGN); + MemOp memop =3D size + (u ? 0 : MO_SIGN); for (pass =3D 0; pass < maxpass; pass++) { TCGv_i64 tcg_op1 =3D tcg_temp_new_i64(); @@ -12849,7 +12849,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) switch (is_fp) { case 1: /* normal fp */ - /* convert insn encoded size to TCGMemOp size */ + /* convert insn encoded size to MemOp size */ switch (size) { case 0: /* half-precision */ size =3D MO_16; @@ -12897,7 +12897,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) return; } - /* Given TCGMemOp size, adjust register and indexing. */ + /* Given MemOp size, adjust register and indexing. */ switch (size) { case MO_16: index =3D h << 2 | l << 1 | m; @@ -13194,7 +13194,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) TCGv_i64 tcg_res[2]; int pass; bool satop =3D extract32(opcode, 0, 1); - TCGMemOp memop =3D MO_32; + MemOp memop =3D MO_32; if (satop || !u) { memop |=3D MO_SIGN; diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 9ab4087..f1246b7 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -64,7 +64,7 @@ static inline void assert_fp_access_checked(DisasContext = *s) * the FP/vector register Qn. */ static inline int vec_reg_offset(DisasContext *s, int regno, - int element, TCGMemOp size) + int element, MemOp size) { int element_size =3D 1 << size; int offs =3D element * element_size; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index fa068b0..5d7edd0 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4567,7 +4567,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a) */ /* The memory mode of the dtype. */ -static const TCGMemOp dtype_mop[16] =3D { +static const MemOp dtype_mop[16] =3D { MO_UB, MO_UB, MO_UB, MO_UB, MO_SL, MO_UW, MO_UW, MO_UW, MO_SW, MO_SW, MO_UL, MO_UL, diff --git a/target/arm/translate.c b/target/arm/translate.c index 7853462..d116c8c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -114,7 +114,7 @@ typedef enum ISSInfo { } ISSInfo; /* Save the syndrome information for a Data Abort */ -static void disas_set_da_iss(DisasContext *s, TCGMemOp memop, ISSInfo issi= nfo) +static void disas_set_da_iss(DisasContext *s, MemOp memop, ISSInfo issinfo) { uint32_t syn; int sas =3D memop & MO_SIZE; @@ -1079,7 +1079,7 @@ static inline void store_reg_from_load(DisasContext *= s, int reg, TCGv_i32 var) * that the address argument is TCGv_i32 rather than TCGv. */ -static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp o= p) +static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op) { TCGv addr =3D tcg_temp_new(); tcg_gen_extu_i32_tl(addr, a32); @@ -1092,7 +1092,7 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCG= v_i32 a32, TCGMemOp op) } static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, - int index, TCGMemOp opc) + int index, MemOp opc) { TCGv addr; @@ -1107,7 +1107,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32= val, TCGv_i32 a32, } static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, - int index, TCGMemOp opc) + int index, MemOp opc) { TCGv addr; @@ -1160,7 +1160,7 @@ static inline void gen_aa32_frob64(DisasContext *s, T= CGv_i64 val) } static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, TCGMemOp opc) + int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); tcg_gen_qemu_ld_i64(val, addr, index, opc); @@ -1175,7 +1175,7 @@ static inline void gen_aa32_ld64(DisasContext *s, TCG= v_i64 val, } static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32, - int index, TCGMemOp opc) + int index, MemOp opc) { TCGv addr =3D gen_aa32_addr(s, a32, opc); @@ -1400,7 +1400,7 @@ neon_reg_offset (int reg, int n) * where 0 is the least significant end of the register. */ static inline long -neon_element_offset(int reg, int element, TCGMemOp size) +neon_element_offset(int reg, int element, MemOp size) { int element_size =3D 1 << size; int ofs =3D element * element_size; @@ -1422,7 +1422,7 @@ static TCGv_i32 neon_load_reg(int reg, int pass) return tmp; } -static void neon_load_element(TCGv_i32 var, int reg, int ele, TCGMemOp mop) +static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) { long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); @@ -1441,7 +1441,7 @@ static void neon_load_element(TCGv_i32 var, int reg, = int ele, TCGMemOp mop) } } -static void neon_load_element64(TCGv_i64 var, int reg, int ele, TCGMemOp m= op) +static void neon_load_element64(TCGv_i64 var, int reg, int ele, MemOp mop) { long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); @@ -1469,7 +1469,7 @@ static void neon_store_reg(int reg, int pass, TCGv_i3= 2 var) tcg_temp_free_i32(var); } -static void neon_store_element(int reg, int ele, TCGMemOp size, TCGv_i32 v= ar) +static void neon_store_element(int reg, int ele, MemOp size, TCGv_i32 var) { long offset =3D neon_element_offset(reg, ele, size); @@ -1488,7 +1488,7 @@ static void neon_store_element(int reg, int ele, TCGM= emOp size, TCGv_i32 var) } } -static void neon_store_element64(int reg, int ele, TCGMemOp size, TCGv_i64= var) +static void neon_store_element64(int reg, int ele, MemOp size, TCGv_i64 va= r) { long offset =3D neon_element_offset(reg, ele, size); @@ -3558,7 +3558,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32= _t insn) int n; int vec_size; int mmu_idx; - TCGMemOp endian; + MemOp endian; TCGv_i32 addr; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -6867,7 +6867,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } else if ((insn & 0x380) =3D=3D 0) { /* VDUP */ int element; - TCGMemOp size; + MemOp size; if ((insn & (7 << 16)) =3D=3D 0 || (q && (rd & 1))) { return 1; @@ -7435,7 +7435,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, TCGv_i32 addr, int size) { TCGv_i32 tmp =3D tcg_temp_new_i32(); - TCGMemOp opc =3D size | MO_ALIGN | s->be_data; + MemOp opc =3D size | MO_ALIGN | s->be_data; s->is_ldex =3D true; @@ -7489,7 +7489,7 @@ static void gen_store_exclusive(DisasContext *s, int = rd, int rt, int rt2, TCGv taddr; TCGLabel *done_label; TCGLabel *fail_label; - TCGMemOp opc =3D size | MO_ALIGN | s->be_data; + MemOp opc =3D size | MO_ALIGN | s->be_data; /* if (env->exclusive_addr =3D=3D addr && env->exclusive_val =3D=3D [a= ddr]) { [addr] =3D {Rt}; @@ -8603,7 +8603,7 @@ static void disas_arm_insn(DisasContext *s, unsigned = int insn) */ TCGv taddr; - TCGMemOp opc =3D s->be_data; + MemOp opc =3D s->be_data; rm =3D (insn) & 0xf; diff --git a/target/arm/translate.h b/target/arm/translate.h index a20f6e2..284c510 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -21,7 +21,7 @@ typedef struct DisasContext { int condexec_cond; int thumb; int sctlr_b; - TCGMemOp be_data; + MemOp be_data; #if !defined(CONFIG_USER_ONLY) int user; #endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 188fe68..ff4802a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1500,7 +1500,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, unsigned rx, int scale, target_sreg disp, - unsigned sp, int modify, TCGMemOp mop) + unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; TCGv_tl addr; @@ -1518,7 +1518,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, unsigned rx, int scale, target_sreg disp, - unsigned sp, int modify, TCGMemOp mop) + unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; TCGv_tl addr; @@ -1536,7 +1536,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, unsigned rx, int scale, target_sreg disp, - unsigned sp, int modify, TCGMemOp mop) + unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; TCGv_tl addr; @@ -1554,7 +1554,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, unsigned rx, int scale, target_sreg disp, - unsigned sp, int modify, TCGMemOp mop) + unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; TCGv_tl addr; @@ -1580,7 +1580,7 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, target_sreg disp, - unsigned sp, int modify, TCGMemOp mop) + unsigned sp, int modify, MemOp mop) { TCGv_reg dest; @@ -1653,7 +1653,7 @@ static bool trans_fldd(DisasContext *ctx, arg_ldst *a) static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb, target_sreg disp, unsigned sp, - int modify, TCGMemOp mop) + int modify, MemOp mop) { nullify_over(ctx); do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); @@ -2940,7 +2940,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a) static bool trans_ldc(DisasContext *ctx, arg_ldst *a) { - TCGMemOp mop =3D MO_TEUL | MO_ALIGN_16 | a->size; + MemOp mop =3D MO_TEUL | MO_ALIGN_16 | a->size; TCGv_reg zero, dest, ofs; TCGv_tl addr; diff --git a/target/i386/translate.c b/target/i386/translate.c index 03150a8..def9867 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -87,8 +87,8 @@ typedef struct DisasContext { /* current insn context */ int override; /* -1 if no override */ int prefix; - TCGMemOp aflag; - TCGMemOp dflag; + MemOp aflag; + MemOp dflag; target_ulong pc_start; target_ulong pc; /* pc =3D eip + cs_base */ /* current block context */ @@ -149,7 +149,7 @@ static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); static void gen_jmp(DisasContext *s, target_ulong eip); static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); -static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d); +static void gen_op(DisasContext *s1, int op, MemOp ot, int d); /* i386 arith/logic operations */ enum { @@ -320,7 +320,7 @@ static inline bool byte_reg_is_xH(DisasContext *s, int = reg) } /* Select the size of a push/pop operation. */ -static inline TCGMemOp mo_pushpop(DisasContext *s, TCGMemOp ot) +static inline MemOp mo_pushpop(DisasContext *s, MemOp ot) { if (CODE64(s)) { return ot =3D=3D MO_16 ? MO_16 : MO_64; @@ -330,13 +330,13 @@ static inline TCGMemOp mo_pushpop(DisasContext *s, TC= GMemOp ot) } /* Select the size of the stack pointer. */ -static inline TCGMemOp mo_stacksize(DisasContext *s) +static inline MemOp mo_stacksize(DisasContext *s) { return CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16; } /* Select only size 64 else 32. Used for SSE operand sizes. */ -static inline TCGMemOp mo_64_32(TCGMemOp ot) +static inline MemOp mo_64_32(MemOp ot) { #ifdef TARGET_X86_64 return ot =3D=3D MO_64 ? MO_64 : MO_32; @@ -347,19 +347,19 @@ static inline TCGMemOp mo_64_32(TCGMemOp ot) /* Select size 8 if lsb of B is clear, else OT. Used for decoding byte vs word opcodes. */ -static inline TCGMemOp mo_b_d(int b, TCGMemOp ot) +static inline MemOp mo_b_d(int b, MemOp ot) { return b & 1 ? ot : MO_8; } /* Select size 8 if lsb of B is clear, else OT capped at 32. Used for decoding operand size of port opcodes. */ -static inline TCGMemOp mo_b_d32(int b, TCGMemOp ot) +static inline MemOp mo_b_d32(int b, MemOp ot) { return b & 1 ? (ot =3D=3D MO_16 ? MO_16 : MO_32) : MO_8; } -static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp ot, int reg, TCGv t= 0) +static void gen_op_mov_reg_v(DisasContext *s, MemOp ot, int reg, TCGv t0) { switch(ot) { case MO_8: @@ -388,7 +388,7 @@ static void gen_op_mov_reg_v(DisasContext *s, TCGMemOp = ot, int reg, TCGv t0) } static inline -void gen_op_mov_v_reg(DisasContext *s, TCGMemOp ot, TCGv t0, int reg) +void gen_op_mov_v_reg(DisasContext *s, MemOp ot, TCGv t0, int reg) { if (ot =3D=3D MO_8 && byte_reg_is_xH(s, reg)) { tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8); @@ -411,13 +411,13 @@ static inline void gen_op_jmp_v(TCGv dest) } static inline -void gen_op_add_reg_im(DisasContext *s, TCGMemOp size, int reg, int32_t va= l) +void gen_op_add_reg_im(DisasContext *s, MemOp size, int reg, int32_t val) { tcg_gen_addi_tl(s->tmp0, cpu_regs[reg], val); gen_op_mov_reg_v(s, size, reg, s->tmp0); } -static inline void gen_op_add_reg_T0(DisasContext *s, TCGMemOp size, int r= eg) +static inline void gen_op_add_reg_T0(DisasContext *s, MemOp size, int reg) { tcg_gen_add_tl(s->tmp0, cpu_regs[reg], s->T0); gen_op_mov_reg_v(s, size, reg, s->tmp0); @@ -451,7 +451,7 @@ static inline void gen_jmp_im(DisasContext *s, target_u= long pc) /* Compute SEG:REG into A0. SEG is selected from the override segment (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to indicate no override. */ -static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0, +static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0, int def_seg, int ovr_seg) { switch (aflag) { @@ -514,13 +514,13 @@ static inline void gen_string_movl_A0_EDI(DisasContex= t *s) gen_lea_v_seg(s, s->aflag, cpu_regs[R_EDI], R_ES, -1); } -static inline void gen_op_movl_T0_Dshift(DisasContext *s, TCGMemOp ot) +static inline void gen_op_movl_T0_Dshift(DisasContext *s, MemOp ot) { tcg_gen_ld32s_tl(s->T0, cpu_env, offsetof(CPUX86State, df)); tcg_gen_shli_tl(s->T0, s->T0, ot); }; -static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp size, bool sign) +static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, bool sign) { switch (size) { case MO_8: @@ -551,18 +551,18 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, TCGMemOp s= ize, bool sign) } } -static void gen_extu(TCGMemOp ot, TCGv reg) +static void gen_extu(MemOp ot, TCGv reg) { gen_ext_tl(reg, reg, ot, false); } -static void gen_exts(TCGMemOp ot, TCGv reg) +static void gen_exts(MemOp ot, TCGv reg) { gen_ext_tl(reg, reg, ot, true); } static inline -void gen_op_jnz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1) +void gen_op_jnz_ecx(DisasContext *s, MemOp size, TCGLabel *label1) { tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]); gen_extu(size, s->tmp0); @@ -570,14 +570,14 @@ void gen_op_jnz_ecx(DisasContext *s, TCGMemOp size, T= CGLabel *label1) } static inline -void gen_op_jz_ecx(DisasContext *s, TCGMemOp size, TCGLabel *label1) +void gen_op_jz_ecx(DisasContext *s, MemOp size, TCGLabel *label1) { tcg_gen_mov_tl(s->tmp0, cpu_regs[R_ECX]); gen_extu(size, s->tmp0); tcg_gen_brcondi_tl(TCG_COND_EQ, s->tmp0, 0, label1); } -static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCGv_i32 n) +static void gen_helper_in_func(MemOp ot, TCGv v, TCGv_i32 n) { switch (ot) { case MO_8: @@ -594,7 +594,7 @@ static void gen_helper_in_func(TCGMemOp ot, TCGv v, TCG= v_i32 n) } } -static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v, TCGv_i32 n) +static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n) { switch (ot) { case MO_8: @@ -611,7 +611,7 @@ static void gen_helper_out_func(TCGMemOp ot, TCGv_i32 v= , TCGv_i32 n) } } -static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_ei= p, +static void gen_check_io(DisasContext *s, MemOp ot, target_ulong cur_eip, uint32_t svm_flags) { target_ulong next_eip; @@ -644,7 +644,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, = target_ulong cur_eip, } } -static inline void gen_movs(DisasContext *s, TCGMemOp ot) +static inline void gen_movs(DisasContext *s, MemOp ot) { gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, s->T0, s->A0); @@ -840,7 +840,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, = TCGv reg) return (CCPrepare) { .cond =3D TCG_COND_NEVER, .mask =3D -1 }; default: { - TCGMemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; + MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; TCGv t0 =3D gen_ext_tl(reg, cpu_cc_dst, size, true); return (CCPrepare) { .cond =3D TCG_COND_LT, .reg =3D t0, .mask= =3D -1 }; } @@ -885,7 +885,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, = TCGv reg) .mask =3D -1 }; default: { - TCGMemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; + MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; TCGv t0 =3D gen_ext_tl(reg, cpu_cc_dst, size, false); return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D t0, .mask= =3D -1 }; } @@ -897,7 +897,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, = TCGv reg) static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) { int inv, jcc_op, cond; - TCGMemOp size; + MemOp size; CCPrepare cc; TCGv t0; @@ -1075,7 +1075,7 @@ static TCGLabel *gen_jz_ecx_string(DisasContext *s, t= arget_ulong next_eip) return l2; } -static inline void gen_stos(DisasContext *s, TCGMemOp ot) +static inline void gen_stos(DisasContext *s, MemOp ot) { gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX); gen_string_movl_A0_EDI(s); @@ -1084,7 +1084,7 @@ static inline void gen_stos(DisasContext *s, TCGMemOp= ot) gen_op_add_reg_T0(s, s->aflag, R_EDI); } -static inline void gen_lods(DisasContext *s, TCGMemOp ot) +static inline void gen_lods(DisasContext *s, MemOp ot) { gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, s->T0, s->A0); @@ -1093,7 +1093,7 @@ static inline void gen_lods(DisasContext *s, TCGMemOp= ot) gen_op_add_reg_T0(s, s->aflag, R_ESI); } -static inline void gen_scas(DisasContext *s, TCGMemOp ot) +static inline void gen_scas(DisasContext *s, MemOp ot) { gen_string_movl_A0_EDI(s); gen_op_ld_v(s, ot, s->T1, s->A0); @@ -1102,7 +1102,7 @@ static inline void gen_scas(DisasContext *s, TCGMemOp= ot) gen_op_add_reg_T0(s, s->aflag, R_EDI); } -static inline void gen_cmps(DisasContext *s, TCGMemOp ot) +static inline void gen_cmps(DisasContext *s, MemOp ot) { gen_string_movl_A0_EDI(s); gen_op_ld_v(s, ot, s->T1, s->A0); @@ -1126,7 +1126,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po= rt, int ot) } -static inline void gen_ins(DisasContext *s, TCGMemOp ot) +static inline void gen_ins(DisasContext *s, MemOp ot) { if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -1148,7 +1148,7 @@ static inline void gen_ins(DisasContext *s, TCGMemOp = ot) } } -static inline void gen_outs(DisasContext *s, TCGMemOp ot) +static inline void gen_outs(DisasContext *s, MemOp ot) { if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); @@ -1171,7 +1171,7 @@ static inline void gen_outs(DisasContext *s, TCGMemOp= ot) /* same method as Valgrind : we generate jumps to current or next instruction */ #define GEN_REPZ(op) = \ -static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, = \ +static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, = \ target_ulong cur_eip, target_ulong next_e= ip) \ { = \ TCGLabel *l2; = \ @@ -1187,7 +1187,7 @@ static inline void gen_repz_ ## op(DisasContext *s, T= CGMemOp ot, \ } #define GEN_REPZ2(op) = \ -static inline void gen_repz_ ## op(DisasContext *s, TCGMemOp ot, = \ +static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, = \ target_ulong cur_eip, = \ target_ulong next_eip, = \ int nz) = \ @@ -1284,7 +1284,7 @@ static void gen_illegal_opcode(DisasContext *s) } /* if d =3D=3D OR_TMP0, it means memory operand (address in A0) */ -static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d) +static void gen_op(DisasContext *s1, int op, MemOp ot, int d) { if (d !=3D OR_TMP0) { if (s1->prefix & PREFIX_LOCK) { @@ -1395,7 +1395,7 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp= ot, int d) } /* if d =3D=3D OR_TMP0, it means memory operand (address in A0) */ -static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c) +static void gen_inc(DisasContext *s1, MemOp ot, int d, int c) { if (s1->prefix & PREFIX_LOCK) { if (d !=3D OR_TMP0) { @@ -1421,7 +1421,7 @@ static void gen_inc(DisasContext *s1, TCGMemOp ot, in= t d, int c) set_cc_op(s1, (c > 0 ? CC_OP_INCB : CC_OP_DECB) + ot); } -static void gen_shift_flags(DisasContext *s, TCGMemOp ot, TCGv result, +static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result, TCGv shm1, TCGv count, bool is_right) { TCGv_i32 z32, s32, oldop; @@ -1466,7 +1466,7 @@ static void gen_shift_flags(DisasContext *s, TCGMemOp= ot, TCGv result, set_cc_op(s, CC_OP_DYNAMIC); } -static void gen_shift_rm_T1(DisasContext *s, TCGMemOp ot, int op1, +static void gen_shift_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right, int is_arith) { target_ulong mask =3D (ot =3D=3D MO_64 ? 0x3f : 0x1f); @@ -1502,7 +1502,7 @@ static void gen_shift_rm_T1(DisasContext *s, TCGMemOp= ot, int op1, gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, is_right); } -static void gen_shift_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, +static void gen_shift_rm_im(DisasContext *s, MemOp ot, int op1, int op2, int is_right, int is_arith) { int mask =3D (ot =3D=3D MO_64 ? 0x3f : 0x1f); @@ -1542,7 +1542,7 @@ static void gen_shift_rm_im(DisasContext *s, TCGMemOp= ot, int op1, int op2, } } -static void gen_rot_rm_T1(DisasContext *s, TCGMemOp ot, int op1, int is_ri= ght) +static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right) { target_ulong mask =3D (ot =3D=3D MO_64 ? 0x3f : 0x1f); TCGv_i32 t0, t1; @@ -1627,7 +1627,7 @@ static void gen_rot_rm_T1(DisasContext *s, TCGMemOp o= t, int op1, int is_right) set_cc_op(s, CC_OP_DYNAMIC); } -static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2, +static void gen_rot_rm_im(DisasContext *s, MemOp ot, int op1, int op2, int is_right) { int mask =3D (ot =3D=3D MO_64 ? 0x3f : 0x1f); @@ -1705,7 +1705,7 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp o= t, int op1, int op2, } /* XXX: add faster immediate =3D 1 case */ -static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1, +static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right) { gen_compute_eflags(s); @@ -1761,7 +1761,7 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp = ot, int op1, } /* XXX: add faster immediate case */ -static void gen_shiftd_rm_T1(DisasContext *s, TCGMemOp ot, int op1, +static void gen_shiftd_rm_T1(DisasContext *s, MemOp ot, int op1, bool is_right, TCGv count_in) { target_ulong mask =3D (ot =3D=3D MO_64 ? 63 : 31); @@ -1842,7 +1842,7 @@ static void gen_shiftd_rm_T1(DisasContext *s, TCGMemO= p ot, int op1, tcg_temp_free(count); } -static void gen_shift(DisasContext *s1, int op, TCGMemOp ot, int d, int s) +static void gen_shift(DisasContext *s1, int op, MemOp ot, int d, int s) { if (s !=3D OR_TMP1) gen_op_mov_v_reg(s1, ot, s1->T1, s); @@ -1872,7 +1872,7 @@ static void gen_shift(DisasContext *s1, int op, TCGMe= mOp ot, int d, int s) } } -static void gen_shifti(DisasContext *s1, int op, TCGMemOp ot, int d, int c) +static void gen_shifti(DisasContext *s1, int op, MemOp ot, int d, int c) { switch(op) { case OP_ROL: @@ -2149,7 +2149,7 @@ static void gen_add_A0_ds_seg(DisasContext *s) /* generate modrm memory load or store of 'reg'. TMP0 is used if reg =3D= =3D OR_TMP0 */ static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, - TCGMemOp ot, int reg, int is_store) + MemOp ot, int reg, int is_store) { int mod, rm; @@ -2179,7 +2179,7 @@ static void gen_ldst_modrm(CPUX86State *env, DisasCon= text *s, int modrm, } } -static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, TCGMemO= p ot) +static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp o= t) { uint32_t ret; @@ -2202,7 +2202,7 @@ static inline uint32_t insn_get(CPUX86State *env, Dis= asContext *s, TCGMemOp ot) return ret; } -static inline int insn_const_size(TCGMemOp ot) +static inline int insn_const_size(MemOp ot) { if (ot <=3D MO_32) { return 1 << ot; @@ -2266,7 +2266,7 @@ static inline void gen_jcc(DisasContext *s, int b, } } -static void gen_cmovcc1(CPUX86State *env, DisasContext *s, TCGMemOp ot, in= t b, +static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b, int modrm, int reg) { CCPrepare cc; @@ -2363,8 +2363,8 @@ static inline void gen_stack_update(DisasContext *s, = int addend) /* Generate a push. It depends on ss32, addseg and dflag. */ static void gen_push_v(DisasContext *s, TCGv val) { - TCGMemOp d_ot =3D mo_pushpop(s, s->dflag); - TCGMemOp a_ot =3D mo_stacksize(s); + MemOp d_ot =3D mo_pushpop(s, s->dflag); + MemOp a_ot =3D mo_stacksize(s); int size =3D 1 << d_ot; TCGv new_esp =3D s->A0; @@ -2383,9 +2383,9 @@ static void gen_push_v(DisasContext *s, TCGv val) } /* two step pop is necessary for precise exceptions */ -static TCGMemOp gen_pop_T0(DisasContext *s) +static MemOp gen_pop_T0(DisasContext *s) { - TCGMemOp d_ot =3D mo_pushpop(s, s->dflag); + MemOp d_ot =3D mo_pushpop(s, s->dflag); gen_lea_v_seg(s, mo_stacksize(s), cpu_regs[R_ESP], R_SS, -1); gen_op_ld_v(s, d_ot, s->T0, s->A0); @@ -2393,7 +2393,7 @@ static TCGMemOp gen_pop_T0(DisasContext *s) return d_ot; } -static inline void gen_pop_update(DisasContext *s, TCGMemOp ot) +static inline void gen_pop_update(DisasContext *s, MemOp ot) { gen_stack_update(s, 1 << ot); } @@ -2405,8 +2405,8 @@ static inline void gen_stack_A0(DisasContext *s) static void gen_pusha(DisasContext *s) { - TCGMemOp s_ot =3D s->ss32 ? MO_32 : MO_16; - TCGMemOp d_ot =3D s->dflag; + MemOp s_ot =3D s->ss32 ? MO_32 : MO_16; + MemOp d_ot =3D s->dflag; int size =3D 1 << d_ot; int i; @@ -2421,8 +2421,8 @@ static void gen_pusha(DisasContext *s) static void gen_popa(DisasContext *s) { - TCGMemOp s_ot =3D s->ss32 ? MO_32 : MO_16; - TCGMemOp d_ot =3D s->dflag; + MemOp s_ot =3D s->ss32 ? MO_32 : MO_16; + MemOp d_ot =3D s->dflag; int size =3D 1 << d_ot; int i; @@ -2442,8 +2442,8 @@ static void gen_popa(DisasContext *s) static void gen_enter(DisasContext *s, int esp_addend, int level) { - TCGMemOp d_ot =3D mo_pushpop(s, s->dflag); - TCGMemOp a_ot =3D CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16; + MemOp d_ot =3D mo_pushpop(s, s->dflag); + MemOp a_ot =3D CODE64(s) ? MO_64 : s->ss32 ? MO_32 : MO_16; int size =3D 1 << d_ot; /* Push BP; compute FrameTemp into T1. */ @@ -2482,8 +2482,8 @@ static void gen_enter(DisasContext *s, int esp_addend= , int level) static void gen_leave(DisasContext *s) { - TCGMemOp d_ot =3D mo_pushpop(s, s->dflag); - TCGMemOp a_ot =3D mo_stacksize(s); + MemOp d_ot =3D mo_pushpop(s, s->dflag); + MemOp a_ot =3D mo_stacksize(s); gen_lea_v_seg(s, a_ot, cpu_regs[R_EBP], R_SS, -1); gen_op_ld_v(s, d_ot, s->T0, s->A0); @@ -3045,7 +3045,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s= , int b, SSEFunc_0_eppi sse_fn_eppi; SSEFunc_0_ppi sse_fn_ppi; SSEFunc_0_eppt sse_fn_eppt; - TCGMemOp ot; + MemOp ot; b &=3D 0xff; if (s->prefix & PREFIX_DATA) @@ -4488,7 +4488,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) CPUX86State *env =3D cpu->env_ptr; int b, prefixes; int shift; - TCGMemOp ot, aflag, dflag; + MemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; int rex_w, rex_r; @@ -5567,8 +5567,8 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) case 0x1be: /* movsbS Gv, Eb */ case 0x1bf: /* movswS Gv, Eb */ { - TCGMemOp d_ot; - TCGMemOp s_ot; + MemOp d_ot; + MemOp s_ot; /* d_ot is the size of destination */ d_ot =3D dflag; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 60bcfb7..24c1dd3 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -2414,7 +2414,7 @@ DISAS_INSN(cas) uint16_t ext; TCGv load; TCGv cmp; - TCGMemOp opc; + MemOp opc; switch ((insn >> 9) & 3) { case 1: diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 9ce65f3..41d1b8b 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -919,7 +919,7 @@ static void dec_load(DisasContext *dc) unsigned int size; bool rev =3D false, ex =3D false, ea =3D false; int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - TCGMemOp mop; + MemOp mop; mop =3D dc->opcode & 3; size =3D 1 << mop; @@ -1035,7 +1035,7 @@ static void dec_store(DisasContext *dc) unsigned int size; bool rev =3D false, ex =3D false, ea =3D false; int mem_index =3D cpu_mmu_index(&dc->cpu->env, false); - TCGMemOp mop; + MemOp mop; mop =3D dc->opcode & 3; size =3D 1 << mop; diff --git a/target/mips/translate.c b/target/mips/translate.c index ca62800..59b5d85 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2526,7 +2526,7 @@ typedef struct DisasContext { int32_t CP0_Config5; /* Routine used to access memory */ int mem_idx; - TCGMemOp default_tcg_memop_mask; + MemOp default_tcg_memop_mask; uint32_t hflags, saved_hflags; target_ulong btarget; bool ulri; @@ -3706,7 +3706,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, i= nt rt, /* Store conditional */ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset, - TCGMemOp tcg_mo, bool eva) + MemOp tcg_mo, bool eva) { TCGv addr, t0, val; TCGLabel *l1 =3D gen_new_label(); @@ -4546,7 +4546,7 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc,= int acc, int reg) } static inline void gen_r6_ld(target_long addr, int reg, int memidx, - TCGMemOp memop) + MemOp memop) { TCGv t0 =3D tcg_const_tl(addr); tcg_gen_qemu_ld_tl(t0, t0, memidx, memop); @@ -21828,7 +21828,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *= env, DisasContext *ctx) extract32(ctx->opcode, 0, 8); TCGv va =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGMemOp memop =3D (extract32(ctx->opcode, 8, 3)) =3D= =3D + MemOp memop =3D (extract32(ctx->opcode, 8, 3)) =3D=3D NM_P_LS_UAWM ? MO_UNALN : 0; count =3D (count =3D=3D 0) ? 8 : count; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 4360ce4..b189c50 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -681,7 +681,7 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a) return true; } -static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop) +static void do_load(DisasContext *dc, arg_load *a, MemOp mop) { TCGv ea; @@ -763,7 +763,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) return true; } -static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop) +static void do_store(DisasContext *dc, arg_store *a, MemOp mop) { TCGv t0 =3D tcg_temp_new(); tcg_gen_addi_tl(t0, cpu_R[a->a], a->i); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4a5de28..31800ed 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -162,7 +162,7 @@ struct DisasContext { int mem_idx; int access_type; /* Translation flags */ - TCGMemOp default_tcg_memop_mask; + MemOp default_tcg_memop_mask; #if defined(TARGET_PPC64) bool sf_mode; bool has_cfar; @@ -3142,7 +3142,7 @@ static void gen_isync(DisasContext *ctx) #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) -static void gen_load_locked(DisasContext *ctx, TCGMemOp memop) +static void gen_load_locked(DisasContext *ctx, MemOp memop) { TCGv gpr =3D cpu_gpr[rD(ctx->opcode)]; TCGv t0 =3D tcg_temp_new(); @@ -3167,7 +3167,7 @@ LARX(lbarx, DEF_MEMOP(MO_UB)) LARX(lharx, DEF_MEMOP(MO_UW)) LARX(lwarx, DEF_MEMOP(MO_UL)) -static void gen_fetch_inc_conditional(DisasContext *ctx, TCGMemOp memop, +static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, TCGv EA, TCGCond cond, int addend) { TCGv t =3D tcg_temp_new(); @@ -3193,7 +3193,7 @@ static void gen_fetch_inc_conditional(DisasContext *c= tx, TCGMemOp memop, tcg_temp_free(u); } -static void gen_ld_atomic(DisasContext *ctx, TCGMemOp memop) +static void gen_ld_atomic(DisasContext *ctx, MemOp memop) { uint32_t gpr_FC =3D FC(ctx->opcode); TCGv EA =3D tcg_temp_new(); @@ -3306,7 +3306,7 @@ static void gen_ldat(DisasContext *ctx) } #endif -static void gen_st_atomic(DisasContext *ctx, TCGMemOp memop) +static void gen_st_atomic(DisasContext *ctx, MemOp memop) { uint32_t gpr_FC =3D FC(ctx->opcode); TCGv EA =3D tcg_temp_new(); @@ -3389,7 +3389,7 @@ static void gen_stdat(DisasContext *ctx) } #endif -static void gen_conditional_store(DisasContext *ctx, TCGMemOp memop) +static void gen_conditional_store(DisasContext *ctx, MemOp memop) { TCGLabel *l1 =3D gen_new_label(); TCGLabel *l2 =3D gen_new_label(); diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_tr= ans/trans_rva.inc.c index fadd888..be8a9f0 100644 --- a/target/riscv/insn_trans/trans_rva.inc.c +++ b/target/riscv/insn_trans/trans_rva.inc.c @@ -18,7 +18,7 @@ * this program. If not, see . */ -static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, TCGMemOp mop) +static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv src1 =3D tcg_temp_new(); /* Put addr in load_res, data in load_val. */ @@ -37,7 +37,7 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *= a, TCGMemOp mop) return true; } -static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, TCGMemOp mop) +static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv src1 =3D tcg_temp_new(); TCGv src2 =3D tcg_temp_new(); @@ -82,8 +82,8 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *= a, TCGMemOp mop) } static bool gen_amo(DisasContext *ctx, arg_atomic *a, - void(*func)(TCGv, TCGv, TCGv, TCGArg, TCGMemOp), - TCGMemOp mop) + void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), + MemOp mop) { TCGv src1 =3D tcg_temp_new(); TCGv src2 =3D tcg_temp_new(); diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_tr= ans/trans_rvi.inc.c index ea64731..cf440d1 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.inc.c @@ -135,7 +135,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a) return gen_branch(ctx, a, TCG_COND_GEU); } -static bool gen_load(DisasContext *ctx, arg_lb *a, TCGMemOp memop) +static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); @@ -174,7 +174,7 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a) return gen_load(ctx, a, MO_TEUW); } -static bool gen_store(DisasContext *ctx, arg_sb *a, TCGMemOp memop) +static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index ac0d8b6..2927247 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -152,7 +152,7 @@ static inline int vec_full_reg_offset(uint8_t reg) return offsetof(CPUS390XState, vregs[reg][0]); } -static inline int vec_reg_offset(uint8_t reg, uint8_t enr, TCGMemOp es) +static inline int vec_reg_offset(uint8_t reg, uint8_t enr, MemOp es) { /* Convert element size (es) - e.g. MO_8 - to bytes */ const uint8_t bytes =3D 1 << es; @@ -2262,7 +2262,7 @@ static DisasJumpType op_csst(DisasContext *s, DisasOp= s *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_csp(DisasContext *s, DisasOps *o) { - TCGMemOp mop =3D s->insn->data; + MemOp mop =3D s->insn->data; TCGv_i64 addr, old, cc; TCGLabel *lab =3D gen_new_label(); @@ -3228,7 +3228,7 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) static DisasJumpType op_lpd(DisasContext *s, DisasOps *o) { TCGv_i64 a1, a2; - TCGMemOp mop =3D s->insn->data; + MemOp mop =3D s->insn->data; /* In a parallel context, stop the world and single step. */ if (tb_cflags(s->base.tb) & CF_PARALLEL) { diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.in= c.c index 41d5cf8..4c56bbb 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -57,13 +57,13 @@ #define FPF_LONG 3 #define FPF_EXT 4 -static inline bool valid_vec_element(uint8_t enr, TCGMemOp es) +static inline bool valid_vec_element(uint8_t enr, MemOp es) { return !(enr & ~(NUM_VEC_ELEMENTS(es) - 1)); } static void read_vec_element_i64(TCGv_i64 dst, uint8_t reg, uint8_t enr, - TCGMemOp memop) + MemOp memop) { const int offs =3D vec_reg_offset(reg, enr, memop & MO_SIZE); @@ -96,7 +96,7 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t re= g, uint8_t enr, } static void read_vec_element_i32(TCGv_i32 dst, uint8_t reg, uint8_t enr, - TCGMemOp memop) + MemOp memop) { const int offs =3D vec_reg_offset(reg, enr, memop & MO_SIZE); @@ -123,7 +123,7 @@ static void read_vec_element_i32(TCGv_i32 dst, uint8_t = reg, uint8_t enr, } static void write_vec_element_i64(TCGv_i64 src, int reg, uint8_t enr, - TCGMemOp memop) + MemOp memop) { const int offs =3D vec_reg_offset(reg, enr, memop & MO_SIZE); @@ -146,7 +146,7 @@ static void write_vec_element_i64(TCGv_i64 src, int reg= , uint8_t enr, } static void write_vec_element_i32(TCGv_i32 src, int reg, uint8_t enr, - TCGMemOp memop) + MemOp memop) { const int offs =3D vec_reg_offset(reg, enr, memop & MO_SIZE); diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 091bab5..bef9ce6 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2019,7 +2019,7 @@ static inline void gen_ne_fop_QD(DisasContext *dc, in= t rd, int rs, } static void gen_swap(DisasContext *dc, TCGv dst, TCGv src, - TCGv addr, int mmu_idx, TCGMemOp memop) + TCGv addr, int mmu_idx, MemOp memop) { gen_address_mask(dc, addr); tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop); @@ -2050,10 +2050,10 @@ typedef struct { ASIType type; int asi; int mem_idx; - TCGMemOp memop; + MemOp memop; } DisasASI; -static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop) +static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) { int asi =3D GET_FIELD(insn, 19, 26); ASIType type =3D GET_ASI_HELPER; @@ -2267,7 +2267,7 @@ static DisasASI get_asi(DisasContext *dc, int insn, T= CGMemOp memop) } static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, - int insn, TCGMemOp memop) + int insn, MemOp memop) { DisasASI da =3D get_asi(dc, insn, memop); @@ -2305,7 +2305,7 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TC= Gv addr, } static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, - int insn, TCGMemOp memop) + int insn, MemOp memop) { DisasASI da =3D get_asi(dc, insn, memop); @@ -2511,7 +2511,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, case GET_ASI_BLOCK: /* Valid for lddfa on aligned registers only. */ if (size =3D=3D 8 && (rd & 7) =3D=3D 0) { - TCGMemOp memop; + MemOp memop; TCGv eight; int i; @@ -2625,7 +2625,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, case GET_ASI_BLOCK: /* Valid for stdfa on aligned registers only. */ if (size =3D=3D 8 && (rd & 7) =3D=3D 0) { - TCGMemOp memop; + MemOp memop; TCGv eight; int i; diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c index c46a4ab..68dd4aa 100644 --- a/target/tilegx/translate.c +++ b/target/tilegx/translate.c @@ -290,7 +290,7 @@ static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrc= b, int sh, int rd) } static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned sr= ca, - unsigned srcb, TCGMemOp memop, const char *n= ame) + unsigned srcb, MemOp memop, const char *name) { if (dest) { return TILEGX_EXCP_OPCODE_UNKNOWN; @@ -305,7 +305,7 @@ static TileExcp gen_st_opcode(DisasContext *dc, unsigne= d dest, unsigned srca, } static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigne= d srcb, - int imm, TCGMemOp memop, const char *nam= e) + int imm, MemOp memop, const char *name) { TCGv tsrca =3D load_gr(dc, srca); TCGv tsrcb =3D load_gr(dc, srcb); @@ -496,7 +496,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigne= d opext, { TCGv tdest, tsrca; const char *mnemonic; - TCGMemOp memop; + MemOp memop; TileExcp ret =3D TILEGX_EXCP_NONE; bool prefetch_nofault =3D false; @@ -1478,7 +1478,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsi= gned opext, TCGv tsrca =3D load_gr(dc, srca); bool prefetch_nofault =3D false; const char *mnemonic; - TCGMemOp memop; + MemOp memop; int i2, i3; TCGv t0; @@ -2106,7 +2106,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bu= ndle_bits bundle) unsigned srca =3D get_SrcA_Y2(bundle); unsigned srcbdest =3D get_SrcBDest_Y2(bundle); const char *mnemonic; - TCGMemOp memop; + MemOp memop; bool prefetch_nofault =3D false; switch (OEY2(opc, mode)) { diff --git a/target/tricore/translate.c b/target/tricore/translate.c index dc2a65f..87a5f50 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -227,7 +227,7 @@ static inline void generate_trap(DisasContext *ctx, int= class, int tin); /* Functions for load/save to/from memory */ static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, - int16_t con, TCGMemOp mop) + int16_t con, MemOp mop) { TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, r2, con); @@ -236,7 +236,7 @@ static inline void gen_offset_ld(DisasContext *ctx, TCG= v r1, TCGv r2, } static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, - int16_t con, TCGMemOp mop) + int16_t con, MemOp mop) { TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, r2, con); @@ -284,7 +284,7 @@ static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv = base, int16_t con, } static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t of= f, - TCGMemOp mop) + MemOp mop) { TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, r2, off); @@ -294,7 +294,7 @@ static void gen_st_preincr(DisasContext *ctx, TCGv r1, = TCGv r2, int16_t off, } static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t of= f, - TCGMemOp mop) + MemOp mop) { TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, r2, off); diff --git a/tcg/README b/tcg/README index 21fcdf7..b4382fa 100644 --- a/tcg/README +++ b/tcg/README @@ -512,7 +512,7 @@ Both t0 and t1 may be split into little-endian ordered = pairs of registers if dealing with 64-bit quantities on a 32-bit host. The memidx selects the qemu tlb index to use (e.g. user or kernel access). -The flags are the TCGMemOp bits, selecting the sign, width, and endianness +The flags are the MemOp bits, selecting the sign, width, and endianness of the memory access. For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 0713448..3f92101 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -1423,7 +1423,7 @@ static inline void tcg_out_rev16(TCGContext *s, TCGRe= g rd, TCGReg rn) tcg_out_insn(s, 3507, REV16, TCG_TYPE_I32, rd, rn); } -static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits, +static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits, TCGReg rd, TCGReg rn) { /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */ @@ -1431,7 +1431,7 @@ static inline void tcg_out_sxt(TCGContext *s, TCGType= ext, TCGMemOp s_bits, tcg_out_sbfm(s, ext, rd, rn, 0, bits); } -static inline void tcg_out_uxt(TCGContext *s, TCGMemOp s_bits, +static inline void tcg_out_uxt(TCGContext *s, MemOp s_bits, TCGReg rd, TCGReg rn) { /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */ @@ -1580,8 +1580,8 @@ static inline void tcg_out_adr(TCGContext *s, TCGReg = rd, void *target) static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(oi); + MemOp size =3D opc & MO_SIZE; if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { return false; @@ -1605,8 +1605,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp size =3D opc & MO_SIZE; + MemOp opc =3D get_memop(oi); + MemOp size =3D opc & MO_SIZE; if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) { return false; @@ -1649,7 +1649,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != =3D 8); slow path for the failure case, which will be patched later when finali= zing the slow path. Generated code returns the host addend in X1, clobbers X0,X2,X3,TMP. */ -static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc, +static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, tcg_insn_unit **label_ptr, int mem_index, bool is_read) { @@ -1709,11 +1709,11 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg = addr_reg, TCGMemOp opc, #endif /* CONFIG_SOFTMMU */ -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp memop, TCGType = ext, +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - const TCGMemOp bswap =3D memop & MO_BSWAP; + const MemOp bswap =3D memop & MO_BSWAP; switch (memop & MO_SSIZE) { case MO_UB: @@ -1765,11 +1765,11 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, T= CGMemOp memop, TCGType ext, } } -static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp memop, +static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, TCGReg data_r, TCGReg addr_r, TCGType otype, TCGReg off_r) { - const TCGMemOp bswap =3D memop & MO_BSWAP; + const MemOp bswap =3D memop & MO_BSWAP; switch (memop & MO_SIZE) { case MO_8: @@ -1804,7 +1804,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCG= MemOp memop, static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, TCGMemOpIdx oi, TCGType ext) { - TCGMemOp memop =3D get_memop(oi); + MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); @@ -1829,7 +1829,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, TCGMemOpIdx oi) { - TCGMemOp memop =3D get_memop(oi); + MemOp memop =3D get_memop(oi); const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c index ece88dc..94d80d7 100644 --- a/tcg/arm/tcg-target.inc.c +++ b/tcg/arm/tcg-target.inc.c @@ -1233,7 +1233,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != =3D 4); containing the addend of the tlb entry. Clobbers R0, R1, R2, TMP. */ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, - TCGMemOp opc, int mem_index, bool is_load) + MemOp opc, int mem_index, bool is_load) { int cmp_off =3D (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); @@ -1348,7 +1348,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) { TCGReg argreg, datalo, datahi; TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); void *func; if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { @@ -1412,7 +1412,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) { TCGReg argreg, datalo, datahi; TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) { return false; @@ -1453,11 +1453,11 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *lb) } #endif /* SOFTMMU */ -static inline void tcg_out_qemu_ld_index(TCGContext *s, TCGMemOp opc, +static inline void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addend) { - TCGMemOp bswap =3D opc & MO_BSWAP; + MemOp bswap =3D opc & MO_BSWAP; switch (opc & MO_SSIZE) { case MO_UB: @@ -1514,11 +1514,11 @@ static inline void tcg_out_qemu_ld_index(TCGContext= *s, TCGMemOp opc, } } -static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, +static inline void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo) { - TCGMemOp bswap =3D opc & MO_BSWAP; + MemOp bswap =3D opc & MO_BSWAP; switch (opc & MO_SSIZE) { case MO_UB: @@ -1577,7 +1577,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) { TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc; + MemOp opc; #ifdef CONFIG_SOFTMMU int mem_index; TCGReg addend; @@ -1614,11 +1614,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) #endif } -static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, TCGMemOp= opc, +static inline void tcg_out_qemu_st_index(TCGContext *s, int cond, MemOp op= c, TCGReg datalo, TCGReg datahi, TCGReg addrlo, TCGReg addend) { - TCGMemOp bswap =3D opc & MO_BSWAP; + MemOp bswap =3D opc & MO_BSWAP; switch (opc & MO_SIZE) { case MO_8: @@ -1659,11 +1659,11 @@ static inline void tcg_out_qemu_st_index(TCGContext= *s, int cond, TCGMemOp opc, } } -static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, +static inline void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo, TCGReg datahi, TCGReg addrlo) { - TCGMemOp bswap =3D opc & MO_BSWAP; + MemOp bswap =3D opc & MO_BSWAP; switch (opc & MO_SIZE) { case MO_8: @@ -1708,7 +1708,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) { TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc; + MemOp opc; #ifdef CONFIG_SOFTMMU int mem_index; TCGReg addend; diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 6ddeebf..9d8ed97 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -1697,7 +1697,7 @@ static void * const qemu_st_helpers[16] =3D { First argument register is clobbered. */ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg a= ddrhi, - int mem_index, TCGMemOp opc, + int mem_index, MemOp opc, tcg_insn_unit **label_ptr, int which) { const TCGReg r0 =3D TCG_REG_L0; @@ -1810,7 +1810,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, bool is_64, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); TCGReg data_reg; tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; int rexw =3D (l->type =3D=3D TCG_TYPE_I64 ? P_REXW : 0); @@ -1895,8 +1895,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; tcg_insn_unit **label_ptr =3D &l->label_ptr[0]; TCGReg retaddr; @@ -1995,10 +1995,10 @@ static inline int setup_guest_base_seg(void) static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, TCGReg base, int index, intptr_t ofs, - int seg, bool is64, TCGMemOp memop) + int seg, bool is64, MemOp memop) { - const TCGMemOp real_bswap =3D memop & MO_BSWAP; - TCGMemOp bswap =3D real_bswap; + const MemOp real_bswap =3D memop & MO_BSWAP; + MemOp bswap =3D real_bswap; int rexw =3D is64 * P_REXW; int movop =3D OPC_MOVL_GvEv; @@ -2103,7 +2103,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is64) TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc; + MemOp opc; #if defined(CONFIG_SOFTMMU) int mem_index; tcg_insn_unit *label_ptr[2]; @@ -2137,15 +2137,15 @@ static void tcg_out_qemu_ld(TCGContext *s, const TC= GArg *args, bool is64) static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg da= tahi, TCGReg base, int index, intptr_t ofs, - int seg, TCGMemOp memop) + int seg, MemOp memop) { /* ??? Ideally we wouldn't need a scratch register. For user-only, we could perform the bswap twice to restore the original value instead of moving to the scratch. But as it is, the L constraint means that TCG_REG_L0 is definitely free here. */ const TCGReg scratch =3D TCG_REG_L0; - const TCGMemOp real_bswap =3D memop & MO_BSWAP; - TCGMemOp bswap =3D real_bswap; + const MemOp real_bswap =3D memop & MO_BSWAP; + MemOp bswap =3D real_bswap; int movop =3D OPC_MOVL_EvGv; if (have_movbe && real_bswap) { @@ -2221,7 +2221,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is64) TCGReg datalo, datahi, addrlo; TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc; + MemOp opc; #if defined(CONFIG_SOFTMMU) int mem_index; tcg_insn_unit *label_ptr[2]; diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 41bff32..5442167 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -1215,7 +1215,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg ba= se, TCGReg addrl, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit *label_ptr[2], bool is_load) { - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); int mem_index =3D get_mmuidx(oi); @@ -1313,7 +1313,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is= _ld, TCGMemOpIdx oi, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); TCGReg v0; int i; @@ -1363,8 +1363,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; int i; /* resolve label address */ @@ -1413,7 +1413,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, TCGMemOp opc, bool is_64) + TCGReg base, MemOp opc, bool is_64) { switch (opc & (MO_SSIZE | MO_BSWAP)) { case MO_UB: @@ -1521,7 +1521,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; TCGMemOpIdx oi; - TCGMemOp opc; + MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; #endif @@ -1558,7 +1558,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) } static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, TCGMemOp opc) + TCGReg base, MemOp opc) { /* Don't clutter the code below with checks to avoid bswapping ZERO. = */ if ((lo | hi) =3D=3D 0) { @@ -1624,7 +1624,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; TCGMemOpIdx oi; - TCGMemOp opc; + MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; #endif diff --git a/tcg/optimize.c b/tcg/optimize.c index d2424de..a89ffda 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1014,7 +1014,7 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(qemu_ld): { TCGMemOpIdx oi =3D op->args[nb_oargs + nb_iargs]; - TCGMemOp mop =3D get_memop(oi); + MemOp mop =3D get_memop(oi); if (!(mop & MO_SIGN)) { mask =3D (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1; } diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 852b894..815edac 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1506,7 +1506,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and = R2. */ -static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, +static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, TCGReg addrlo, TCGReg addrhi, int mem_index, bool is_read) { @@ -1633,7 +1633,7 @@ static void add_qemu_ldst_label(TCGContext *s, bool i= s_ld, TCGMemOpIdx oi, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); TCGReg hi, lo, arg =3D TCG_REG_R3; if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { @@ -1680,8 +1680,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) { TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; TCGReg hi, lo, arg =3D TCG_REG_R3; if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) { @@ -1744,7 +1744,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) TCGReg datalo, datahi, addrlo, rbase; TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc, s_bits; + MemOp opc, s_bits; #ifdef CONFIG_SOFTMMU int mem_index; tcg_insn_unit *label_ptr; @@ -1819,7 +1819,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) TCGReg datalo, datahi, addrlo, rbase; TCGReg addrhi __attribute__((unused)); TCGMemOpIdx oi; - TCGMemOp opc, s_bits; + MemOp opc, s_bits; #ifdef CONFIG_SOFTMMU int mem_index; tcg_insn_unit *label_ptr; diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index 3e76bf5..7018509 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -970,7 +970,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addr= l, TCGReg addrh, TCGMemOpIdx oi, tcg_insn_unit **label_ptr, bool is_load) { - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); unsigned s_bits =3D opc & MO_SIZE; unsigned a_bits =3D get_alignment_bits(opc); tcg_target_long compare_mask; @@ -1044,7 +1044,7 @@ static void add_qemu_ldst_label(TCGContext *s, int is= _ld, TCGMemOpIdx oi, static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); TCGReg a0 =3D tcg_target_call_iarg_regs[0]; TCGReg a1 =3D tcg_target_call_iarg_regs[1]; TCGReg a2 =3D tcg_target_call_iarg_regs[2]; @@ -1077,8 +1077,8 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) { TCGMemOpIdx oi =3D l->oi; - TCGMemOp opc =3D get_memop(oi); - TCGMemOp s_bits =3D opc & MO_SIZE; + MemOp opc =3D get_memop(oi); + MemOp s_bits =3D opc & MO_SIZE; TCGReg a0 =3D tcg_target_call_iarg_regs[0]; TCGReg a1 =3D tcg_target_call_iarg_regs[1]; TCGReg a2 =3D tcg_target_call_iarg_regs[2]; @@ -1121,9 +1121,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) #endif /* CONFIG_SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, TCGMemOp opc, bool is_64) + TCGReg base, MemOp opc, bool is_64) { - const TCGMemOp bswap =3D opc & MO_BSWAP; + const MemOp bswap =3D opc & MO_BSWAP; /* We don't yet handle byteswapping, assert */ g_assert(!bswap); @@ -1172,7 +1172,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; TCGMemOpIdx oi; - TCGMemOp opc; + MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; #endif @@ -1208,9 +1208,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) } static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, - TCGReg base, TCGMemOp opc) + TCGReg base, MemOp opc) { - const TCGMemOp bswap =3D opc & MO_BSWAP; + const MemOp bswap =3D opc & MO_BSWAP; /* We don't yet handle byteswapping, assert */ g_assert(!bswap); @@ -1243,7 +1243,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) TCGReg addr_regl, addr_regh __attribute__((unused)); TCGReg data_regl, data_regh; TCGMemOpIdx oi; - TCGMemOp opc; + MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[1]; #endif diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index fe42939..8aaa4ce 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -1430,7 +1430,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit= *dest) } } -static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg dat= a, +static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data, TCGReg base, TCGReg index, int disp) { switch (opc & (MO_SSIZE | MO_BSWAP)) { @@ -1489,7 +1489,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCG= MemOp opc, TCGReg data, } } -static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg dat= a, +static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data, TCGReg base, TCGReg index, int disp) { switch (opc & (MO_SIZE | MO_BSWAP)) { @@ -1544,7 +1544,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); /* Load and compare a TLB entry, leaving the flags set. Loads the TLB addend into R2. Returns a register with the santitized guest address. = */ -static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp op= c, +static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, int mem_index, bool is_ld) { unsigned s_bits =3D opc & MO_SIZE; @@ -1614,7 +1614,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) TCGReg addr_reg =3D lb->addrlo_reg; TCGReg data_reg =3D lb->datalo_reg; TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2)) { @@ -1639,7 +1639,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *lb) TCGReg addr_reg =3D lb->addrlo_reg; TCGReg data_reg =3D lb->datalo_reg; TCGMemOpIdx oi =3D lb->oi; - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL, (intptr_t)s->code_ptr, 2)) { @@ -1694,7 +1694,7 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGR= eg *addr_reg, static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, TCGMemOpIdx oi) { - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; @@ -1721,7 +1721,7 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg dat= a_reg, TCGReg addr_reg, static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_re= g, TCGMemOpIdx oi) { - TCGMemOp opc =3D get_memop(oi); + MemOp opc =3D get_memop(oi); #ifdef CONFIG_SOFTMMU unsigned mem_index =3D get_mmuidx(oi); tcg_insn_unit *label_ptr; diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c index 10b1cea..d7986cd 100644 --- a/tcg/sparc/tcg-target.inc.c +++ b/tcg/sparc/tcg-target.inc.c @@ -1081,7 +1081,7 @@ QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); is in the returned register, maybe %o0. The TLB addend is in %o1. */ static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addr, int mem_index, - TCGMemOp opc, int which) + MemOp opc, int which) { int fast_off =3D TLB_MASK_TABLE_OFS(mem_index); int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); @@ -1164,7 +1164,7 @@ static const int qemu_st_opc[16] =3D { static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr, TCGMemOpIdx oi, bool is_64) { - TCGMemOp memop =3D get_memop(oi); + MemOp memop =3D get_memop(oi); #ifdef CONFIG_SOFTMMU unsigned memi =3D get_mmuidx(oi); TCGReg addrz, param; @@ -1246,7 +1246,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a, TCGReg addr, static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr, TCGMemOpIdx oi) { - TCGMemOp memop =3D get_memop(oi); + MemOp memop =3D get_memop(oi); #ifdef CONFIG_SOFTMMU unsigned memi =3D get_mmuidx(oi); TCGReg addrz, param; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 587d092..e87c327 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2714,7 +2714,7 @@ void tcg_gen_lookup_and_goto_ptr(void) } } -static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool= st) +static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { /* Trigger the asserts within as early as possible. */ (void)get_alignment_bits(op); @@ -2743,7 +2743,7 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemO= p op, bool is64, bool st) } static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr, - TCGMemOp memop, TCGArg idx) + MemOp memop, TCGArg idx) { TCGMemOpIdx oi =3D make_memop_idx(memop, idx); #if TARGET_LONG_BITS =3D=3D 32 @@ -2758,7 +2758,7 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val,= TCGv addr, } static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr, - TCGMemOp memop, TCGArg idx) + MemOp memop, TCGArg idx) { TCGMemOpIdx oi =3D make_memop_idx(memop, idx); #if TARGET_LONG_BITS =3D=3D 32 @@ -2788,9 +2788,9 @@ static void tcg_gen_req_mo(TCGBar type) } } -void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) +void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) { - TCGMemOp orig_memop; + MemOp orig_memop; tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop =3D tcg_canonicalize_memop(memop, 0, 0); @@ -2825,7 +2825,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } } -void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) +void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) { TCGv_i32 swap =3D NULL; @@ -2858,9 +2858,9 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } } -void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) +void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) { - TCGMemOp orig_memop; + MemOp orig_memop; if (TCG_TARGET_REG_BITS =3D=3D 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); @@ -2911,7 +2911,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } } -void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp mem= op) +void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) { TCGv_i64 swap =3D NULL; @@ -2953,7 +2953,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCG= Arg idx, TCGMemOp memop) } } -static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc) +static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) { switch (opc & MO_SSIZE) { case MO_SB: @@ -2974,7 +2974,7 @@ static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 va= l, TCGMemOp opc) } } -static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc) +static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, MemOp opc) { switch (opc & MO_SSIZE) { case MO_SB: @@ -3034,7 +3034,7 @@ static void * const table_cmpxchg[16] =3D { }; void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, - TCGv_i32 newv, TCGArg idx, TCGMemOp memop) + TCGv_i32 newv, TCGArg idx, MemOp memop) { memop =3D tcg_canonicalize_memop(memop, 0, 0); @@ -3078,7 +3078,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, } void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, - TCGv_i64 newv, TCGArg idx, TCGMemOp memop) + TCGv_i64 newv, TCGArg idx, MemOp memop) { memop =3D tcg_canonicalize_memop(memop, 1, 0); @@ -3142,7 +3142,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, } static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, - TCGArg idx, TCGMemOp memop, bool new_val, + TCGArg idx, MemOp memop, bool new_val, void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) { TCGv_i32 t1 =3D tcg_temp_new_i32(); @@ -3160,7 +3160,7 @@ static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv ad= dr, TCGv_i32 val, } static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, - TCGArg idx, TCGMemOp memop, void * const tabl= e[]) + TCGArg idx, MemOp memop, void * const table[]) { gen_atomic_op_i32 gen; @@ -3185,7 +3185,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr,= TCGv_i32 val, } static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, - TCGArg idx, TCGMemOp memop, bool new_val, + TCGArg idx, MemOp memop, bool new_val, void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) { TCGv_i64 t1 =3D tcg_temp_new_i64(); @@ -3203,7 +3203,7 @@ static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv ad= dr, TCGv_i64 val, } static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val, - TCGArg idx, TCGMemOp memop, void * const tabl= e[]) + TCGArg idx, MemOp memop, void * const table[]) { memop =3D tcg_canonicalize_memop(memop, 1, 0); @@ -3257,7 +3257,7 @@ static void * const table_##NAME[16] =3D { = \ WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be) \ }; \ void tcg_gen_atomic_##NAME##_i32 \ - (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ + (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop) \ { \ if (tcg_ctx->tb_cflags & CF_PARALLEL) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ @@ -3267,7 +3267,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ } \ } \ void tcg_gen_atomic_##NAME##_i64 \ - (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ + (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, MemOp memop) \ { \ if (tcg_ctx->tb_cflags & CF_PARALLEL) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 2d4dd5c..e9cf172 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -851,10 +851,10 @@ void tcg_gen_lookup_and_goto_ptr(void); #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 #endif -void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); -void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp); -void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); -void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp); +void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { @@ -912,46 +912,46 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TC= Gv addr, int mem_index) } void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, - TCGArg, TCGMemOp); + TCGArg, MemOp); void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, - TCGArg, TCGMemOp); - -void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp); -void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp); - -void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMem= Op); -void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMem= Op); -void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMem= Op); -void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMem= Op); -void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemO= p); -void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemO= p); -void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMem= Op); -void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMem= Op); -void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMe= mOp); - -void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMem= Op); -void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMem= Op); -void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMem= Op); -void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMem= Op); -void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemO= p); -void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemO= p); -void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMem= Op); -void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMem= Op); -void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMe= mOp); -void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMe= mOp); + TCGArg, MemOp); + +void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); + +void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); +void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); +void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); +void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); +void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); +void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); +void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); +void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); + +void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); +void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); +void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); +void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); +void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); +void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); +void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); +void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp= ); +void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp= ); void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); diff --git a/tcg/tcg.c b/tcg/tcg.c index 8d23fb0..0dff196 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2056,7 +2056,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_pre= fs) case INDEX_op_qemu_st_i64: { TCGMemOpIdx oi =3D op->args[k++]; - TCGMemOp op =3D get_memop(oi); + MemOp op =3D get_memop(oi); unsigned ix =3D get_mmuidx(oi); if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) { diff --git a/tcg/tcg.h b/tcg/tcg.h index 529acb2..a37181c 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -26,6 +26,7 @@ #define TCG_H #include "cpu.h" +#include "exec/memop.h" #include "exec/tb-context.h" #include "qemu/bitops.h" #include "qemu/queue.h" @@ -309,103 +310,13 @@ typedef enum TCGType { #endif } TCGType; -/* Constants for qemu_ld and qemu_st for the Memory Operation field. */ -typedef enum TCGMemOp { - MO_8 =3D 0, - MO_16 =3D 1, - MO_32 =3D 2, - MO_64 =3D 3, - MO_SIZE =3D 3, /* Mask for the above. */ - - MO_SIGN =3D 4, /* Sign-extended, otherwise zero-extended. */ - - MO_BSWAP =3D 8, /* Host reverse endian. */ -#ifdef HOST_WORDS_BIGENDIAN - MO_LE =3D MO_BSWAP, - MO_BE =3D 0, -#else - MO_LE =3D 0, - MO_BE =3D MO_BSWAP, -#endif -#ifdef TARGET_WORDS_BIGENDIAN - MO_TE =3D MO_BE, -#else - MO_TE =3D MO_LE, -#endif - - /* - * MO_UNALN accesses are never checked for alignment. - * MO_ALIGN accesses will result in a call to the CPU's - * do_unaligned_access hook if the guest address is not aligned. - * The default depends on whether the target CPU defines - * TARGET_ALIGNED_ONLY. - * - * Some architectures (e.g. ARMv8) need the address which is aligned - * to a size more than the size of the memory access. - * Some architectures (e.g. SPARCv9) need an address which is aligned, - * but less strictly than the natural alignment. - * - * MO_ALIGN supposes the alignment size is the size of a memory access. - * - * There are three options: - * - unaligned access permitted (MO_UNALN). - * - an alignment to the size of an access (MO_ALIGN); - * - an alignment to a specified size, which may be more or less than - * the access size (MO_ALIGN_x where 'x' is a size in bytes); - */ - MO_ASHIFT =3D 4, - MO_AMASK =3D 7 << MO_ASHIFT, -#ifdef TARGET_ALIGNED_ONLY - MO_ALIGN =3D 0, - MO_UNALN =3D MO_AMASK, -#else - MO_ALIGN =3D MO_AMASK, - MO_UNALN =3D 0, -#endif - MO_ALIGN_2 =3D 1 << MO_ASHIFT, - MO_ALIGN_4 =3D 2 << MO_ASHIFT, - MO_ALIGN_8 =3D 3 << MO_ASHIFT, - MO_ALIGN_16 =3D 4 << MO_ASHIFT, - MO_ALIGN_32 =3D 5 << MO_ASHIFT, - MO_ALIGN_64 =3D 6 << MO_ASHIFT, - - /* Combinations of the above, for ease of use. */ - MO_UB =3D MO_8, - MO_UW =3D MO_16, - MO_UL =3D MO_32, - MO_SB =3D MO_SIGN | MO_8, - MO_SW =3D MO_SIGN | MO_16, - MO_SL =3D MO_SIGN | MO_32, - MO_Q =3D MO_64, - - MO_LEUW =3D MO_LE | MO_UW, - MO_LEUL =3D MO_LE | MO_UL, - MO_LESW =3D MO_LE | MO_SW, - MO_LESL =3D MO_LE | MO_SL, - MO_LEQ =3D MO_LE | MO_Q, - - MO_BEUW =3D MO_BE | MO_UW, - MO_BEUL =3D MO_BE | MO_UL, - MO_BESW =3D MO_BE | MO_SW, - MO_BESL =3D MO_BE | MO_SL, - MO_BEQ =3D MO_BE | MO_Q, - - MO_TEUW =3D MO_TE | MO_UW, - MO_TEUL =3D MO_TE | MO_UL, - MO_TESW =3D MO_TE | MO_SW, - MO_TESL =3D MO_TE | MO_SL, - MO_TEQ =3D MO_TE | MO_Q, - - MO_SSIZE =3D MO_SIZE | MO_SIGN, -} TCGMemOp; - /** * get_alignment_bits - * @memop: TCGMemOp value + * @memop: MemOp value * * Extract the alignment size from the memop. */ -static inline unsigned get_alignment_bits(TCGMemOp memop) +static inline unsigned get_alignment_bits(MemOp memop) { unsigned a =3D memop & MO_AMASK; @@ -1186,7 +1097,7 @@ static inline size_t tcg_current_code_size(TCGContext= *s) return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); } -/* Combine the TCGMemOp and mmu_idx parameters into a single value. */ +/* Combine the MemOp and mmu_idx parameters into a single value. */ typedef uint32_t TCGMemOpIdx; /** @@ -1196,7 +1107,7 @@ typedef uint32_t TCGMemOpIdx; * * Encode these values into a single parameter. */ -static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) +static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx) { tcg_debug_assert(idx <=3D 15); return (op << 4) | idx; @@ -1208,7 +1119,7 @@ static inline TCGMemOpIdx make_memop_idx(TCGMemOp op,= unsigned idx) * * Extract the memory operation from the combined value. */ -static inline TCGMemOp get_memop(TCGMemOpIdx oi) +static inline MemOp get_memop(TCGMemOpIdx oi) { return oi >> 4; } diff --git a/trace/mem-internal.h b/trace/mem-internal.h index f6efaf6..3444fbc 100644 --- a/trace/mem-internal.h +++ b/trace/mem-internal.h @@ -16,7 +16,7 @@ #define TRACE_MEM_ST (1ULL << 5) /* store (y/n) */ static inline uint8_t trace_mem_build_info( - int size_shift, bool sign_extend, TCGMemOp endianness, bool store) + int size_shift, bool sign_extend, MemOp endianness, bool store) { uint8_t res; @@ -33,7 +33,7 @@ static inline uint8_t trace_mem_build_info( return res; } -static inline uint8_t trace_mem_get_info(TCGMemOp op, bool store) +static inline uint8_t trace_mem_get_info(MemOp op, bool store) { return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN), op & MO_BSWAP, store); diff --git a/trace/mem.h b/trace/mem.h index 2b58196..8cf213d 100644 --- a/trace/mem.h +++ b/trace/mem.h @@ -18,7 +18,7 @@ * * Return a value for the 'info' argument in guest memory access traces. */ -static uint8_t trace_mem_get_info(TCGMemOp op, bool store); +static uint8_t trace_mem_get_info(MemOp op, bool store); /** * trace_mem_build_info: @@ -26,7 +26,7 @@ static uint8_t trace_mem_get_info(TCGMemOp op, bool store= ); * Return a value for the 'info' argument in guest memory access traces. */ static uint8_t trace_mem_build_info(int size_shift, bool sign_extend, - TCGMemOp endianness, bool store); + MemOp endianness, bool store); #include "trace/mem-internal.h" -- 1.8.3.1 From nobody Sat Apr 20 01:08:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=bt.com ARC-Seal: i=1; a=rsa-sha256; t=1565166448; cv=none; d=zoho.com; s=zohoarc; b=BJORO47srIUeBO++frHeh9fspDy54SX9Q0KWtJBKzkqaCkhggByHBtmsFDh3XF0LsVlbEggV8to6mq4R7wXMuohYxQVAQk9eFko0EGclAl4UuhWTuIGWrj7R+ZMq5lIOuGhWDlR8PlxZ8ozVTkWJ9Jw7oHm+I1ntGNA09MxIifo= ARC-Message-Signature: i=1; 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Wed, 7 Aug 2019 09:26:47 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 03/26] memory: Introduce size_memop Thread-Index: AQHVTPnaWz9ZrvhuI0myNkwQ3w2mGQ== Date: Wed, 7 Aug 2019 08:26:47 +0000 Message-ID: <1565166407497.21726@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 62.239.224.235 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 03/26] memory: Introduce size_memop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The memory_region_dispatch_{read|write} operand "unsigned size" is being converted into a "MemOp op". Introduce no-op size_memop to aid preparatory conversion of interfaces. Once interfaces are converted, size_memop will be implemented to return a MemOp from size in bytes. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- include/exec/memop.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/exec/memop.h b/include/exec/memop.h index 7262ca3..5c5769e 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -107,4 +107,14 @@ typedef enum MemOp { MO_SSIZE =3D MO_SIZE | MO_SIGN, } MemOp; +/* Size in bytes to MemOp. */ +static inline MemOp size_memop(unsigned size) +{ + /* + * FIXME: No-op to aid conversion of memory_region_dispatch_{read|writ= e} + * "unsigned size" operand into a "MemOp op". + */ + return size; +} + #endif -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:27:14 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 04/26] target/mips: Access MemoryRegion with MemOp Thread-Index: AQHVTPnqprcONrFqPEOth6dH3Z+T4Q== Date: Wed, 7 Aug 2019 08:27:14 +0000 Message-ID: <1565166433653.42084@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.71 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 04/26] target/mips: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The memory_region_dispatch_{read|write} operand "unsigned size" is being converted into a "MemOp op". Convert interfaces by using no-op size_memop. After all interfaces are converted, size_memop will be implemented and the memory_region_dispatch_{read|write} operand "unsigned size" will be converted into a "MemOp op". As size_memop is a no-op, this patch does not change any behaviour. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 ? --- target/mips/op_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 9e2e02f..1c72a00 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/memop.h" #include "sysemu/kvm.h" /*************************************************************************= ****/ @@ -4740,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, target_ulong a= ddr, uint32_t op) if (op =3D=3D 9) { /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - 8, MEMTXATTRS_UNSPECIFIED); + size_memop(8), MEMTXATTRS_UNSPECIFIED= ); } else if (op =3D=3D 5) { /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - 8, MEMTXATTRS_UNSPECIFIED); + size_memop(8), MEMTXATTRS_UNSPECIFIED); } #endif } -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:27:35 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 05/26] hw/s390x: Access MemoryRegion with MemOp Thread-Index: AQHVTPn2pBvCxiLKIke2xdwZYbeoVw== Date: Wed, 7 Aug 2019 08:27:35 +0000 Message-ID: <1565166454836.5266@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.75 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 05/26] hw/s390x: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The memory_region_dispatch_{read|write} operand "unsigned size" is being converted into a "MemOp op". Convert interfaces by using no-op size_memop. After all interfaces are converted, size_memop will be implemented and the memory_region_dispatch_{read|write} operand "unsigned size" will be converted into a "MemOp op". As size_memop is a no-op, this patch does not change any behaviour. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson Reviewed-by: Cornelia Huck --- hw/s390x/s390-pci-inst.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 0023514..0c958fc 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -15,6 +15,7 @@ #include "cpu.h" #include "s390-pci-inst.h" #include "s390-pci-bus.h" +#include "exec/memop.h" #include "exec/memory-internal.h" #include "qemu/error-report.h" #include "sysemu/hw_accel.h" @@ -372,7 +373,7 @@ static MemTxResult zpci_read_bar(S390PCIBusDevice *pbde= v, uint8_t pcias, mr =3D pbdev->pdev->io_regions[pcias].memory; mr =3D s390_get_subregion(mr, offset, len); offset -=3D mr->addr; - return memory_region_dispatch_read(mr, offset, data, len, + return memory_region_dispatch_read(mr, offset, data, size_memop(len), MEMTXATTRS_UNSPECIFIED); } @@ -471,7 +472,7 @@ static MemTxResult zpci_write_bar(S390PCIBusDevice *pbd= ev, uint8_t pcias, mr =3D pbdev->pdev->io_regions[pcias].memory; mr =3D s390_get_subregion(mr, offset, len); offset -=3D mr->addr; - return memory_region_dispatch_write(mr, offset, data, len, + return memory_region_dispatch_write(mr, offset, data, size_memop(len), MEMTXATTRS_UNSPECIFIED); } @@ -780,7 +781,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8= _t r3, uint64_t gaddr, for (i =3D 0; i < len / 8; i++) { result =3D memory_region_dispatch_write(mr, offset + i * 8, - ldq_p(buffer + i * 8), 8, + ldq_p(buffer + i * 8), + size_memop(8), MEMTXATTRS_UNSPECIFIED); if (result !=3D MEMTX_OK) { s390_program_interrupt(env, PGM_OPERAND, 6, ra); -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:27:57 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 06/26] hw/intc/armv7m_nic: Access MemoryRegion with MemOp Thread-Index: AQHVTPoEhAACGcI7vEmAJW6vjexb7g== Date: Wed, 7 Aug 2019 08:27:57 +0000 Message-ID: <1565166476779.68828@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.77 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 06/26] hw/intc/armv7m_nic: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The memory_region_dispatch_{read|write} operand "unsigned size" is being converted into a "MemOp op". Convert interfaces by using no-op size_memop. After all interfaces are converted, size_memop will be implemented and the memory_region_dispatch_{read|write} operand "unsigned size" will be converted into a "MemOp op". As size_memop is a no-op, this patch does not change any behaviour. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 ? --- hw/intc/armv7m_nvic.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9f8f0d3..237ccef 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -18,6 +18,7 @@ #include "hw/intc/armv7m_nvic.h" #include "target/arm/cpu.h" #include "exec/exec-all.h" +#include "exec/memop.h" #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" @@ -2345,7 +2346,8 @@ static MemTxResult nvic_sysreg_ns_write(void *opaque,= hwaddr addr, if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; - return memory_region_dispatch_write(mr, addr, value, size, attrs); + return memory_region_dispatch_write(mr, addr, value, size_memop(si= ze), + attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2364,7 +2366,8 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, = hwaddr addr, if (attrs.secure) { /* S accesses to the alias act like NS accesses to the real region= */ attrs.secure =3D 0; - return memory_region_dispatch_read(mr, addr, data, size, attrs); + return memory_region_dispatch_read(mr, addr, data, size_memop(size= ), + attrs); } else { /* NS attrs are RAZ/WI for privileged, and BusFault for user */ if (attrs.user) { @@ -2390,7 +2393,8 @@ static MemTxResult nvic_systick_write(void *opaque, h= waddr addr, /* Direct the access to the correct systick */ mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_write(mr, addr, value, size, attrs); + return memory_region_dispatch_write(mr, addr, value, size_memop(size), + attrs); } static MemTxResult nvic_systick_read(void *opaque, hwaddr addr, @@ -2402,7 +2406,7 @@ static MemTxResult nvic_systick_read(void *opaque, hw= addr addr, /* Direct the access to the correct systick */ mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->systick[attrs.secure]= ), 0); - return memory_region_dispatch_read(mr, addr, data, size, attrs); + return memory_region_dispatch_read(mr, addr, data, size_memop(size), a= ttrs); } static const MemoryRegionOps nvic_systick_ops =3D { -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:28:16 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 07/26] hw/virtio: Access MemoryRegion with MemOp Thread-Index: AQHVTPoPeg6DwrIkBEWe8eU+OaDygw== Date: Wed, 7 Aug 2019 08:28:16 +0000 Message-ID: <1565166496048.47265@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.72 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 07/26] hw/virtio: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The memory_region_dispatch_{read|write} operand "unsigned size" is being converted into a "MemOp op". Convert interfaces by using no-op size_memop. After all interfaces are converted, size_memop will be implemented and the memory_region_dispatch_{read|write} operand "unsigned size" will be converted into a "MemOp op". As size_memop is a no-op, this patch does not change any behaviour. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson Reviewed-by: Cornelia Huck --- hw/virtio/virtio-pci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index f6d2223..25875c8 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -17,6 +17,7 @@ #include "qemu/osdep.h" +#include "exec/memop.h" #include "standard-headers/linux/virtio_pci.h" #include "hw/virtio/virtio.h" #include "hw/pci/pci.h" @@ -550,7 +551,8 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, = hwaddr addr, /* As length is under guest control, handle illegal values. */ return; } - memory_region_dispatch_write(mr, addr, val, len, MEMTXATTRS_UNSPECIFIE= D); + memory_region_dispatch_write(mr, addr, val, size_memop(len), + MEMTXATTRS_UNSPECIFIED); } static void @@ -573,7 +575,8 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr= addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); - memory_region_dispatch_read(mr, addr, &val, len, MEMTXATTRS_UNSPECIFIE= D); + memory_region_dispatch_read(mr, addr, &val, size_memop(len), + MEMTXATTRS_UNSPECIFIED); switch (len) { case 1: pci_set_byte(buf, val); -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:28:40 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 08/26] hw/vfio: Access MemoryRegion with MemOp Thread-Index: AQHVTPodpOirbSsH2ke9flAJiOEFxA== Date: Wed, 7 Aug 2019 08:28:40 +0000 Message-ID: <1565166520130.61317@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.74 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 08/26] hw/vfio: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The memory_region_dispatch_{read|write} operand "unsigned size" is being converted into a "MemOp op". Convert interfaces by using no-op size_memop. After all interfaces are converted, size_memop will be implemented and the memory_region_dispatch_{read|write} operand "unsigned size" will be converted into a "MemOp op". As size_memop is a no-op, this patch does not change any behaviour. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson Reviewed-by: Cornelia Huck --- hw/vfio/pci-quirks.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index b35a640..fb3cc33 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -11,6 +11,7 @@ */ #include "qemu/osdep.h" +#include "exec/memop.h" #include "qemu/units.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" @@ -1071,7 +1072,7 @@ static void vfio_rtl8168_quirk_address_write(void *op= aque, hwaddr addr, /* Write to the proper guest MSI-X table instead */ memory_region_dispatch_write(&vdev->pdev.msix_table_mmio, - offset, val, size, + offset, val, size_memop(size), MEMTXATTRS_UNSPECIFIED); } return; /* Do not write guest MSI-X data to hardware */ @@ -1102,7 +1103,8 @@ static uint64_t vfio_rtl8168_quirk_data_read(void *op= aque, if (rtl->enabled && (vdev->pdev.cap_present & QEMU_PCI_CAP_MSIX)) { hwaddr offset =3D rtl->addr & 0xfff; memory_region_dispatch_read(&vdev->pdev.msix_table_mmio, offset, - &data, size, MEMTXATTRS_UNSPECIFIED); + &data, size_memop(size), + MEMTXATTRS_UNSPECIFIED); trace_vfio_quirk_rtl8168_msix_read(vdev->vbasedev.name, offset, da= ta); } -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:28:59 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 09/26] exec: Access MemoryRegion with MemOp Thread-Index: AQHVTPopl/eCIE+w30qkb8WHjtwBMw== Date: Wed, 7 Aug 2019 08:28:59 +0000 Message-ID: <1565166539442.24361@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.77 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 09/26] exec: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The memory_region_dispatch_{read|write} operand "unsigned size" is being converted into a "MemOp op". Convert interfaces by using no-op size_memop. After all interfaces are converted, size_memop will be implemented and the memory_region_dispatch_{read|write} operand "unsigned size" will be converted into a "MemOp op". As size_memop is a no-op, this patch does not change any behaviour. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 ? --- exec.c | 6 ++++-- memory_ldst.inc.c | 18 +++++++++--------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/exec.c b/exec.c index 3e78de3..9f69197 100644 --- a/exec.c +++ b/exec.c @@ -3334,7 +3334,8 @@ static MemTxResult flatview_write_continue(FlatView *= fv, hwaddr addr, /* XXX: could force current_cpu to NULL to avoid potential bugs */ val =3D ldn_p(buf, l); - result |=3D memory_region_dispatch_write(mr, addr1, val, l, at= trs); + result |=3D memory_region_dispatch_write(mr, addr1, val, + size_memop(l), attrs); } else { /* RAM case */ ptr =3D qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); @@ -3395,7 +3396,8 @@ MemTxResult flatview_read_continue(FlatView *fv, hwad= dr addr, /* I/O case */ release_lock |=3D prepare_mmio_access(mr); l =3D memory_access_size(mr, l, addr1); - result |=3D memory_region_dispatch_read(mr, addr1, &val, l, at= trs); + result |=3D memory_region_dispatch_read(mr, addr1, &val, + size_memop(l), attrs); stn_p(buf, l, val); } else { /* RAM case */ diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index acf865b..1e8a2fc 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -38,7 +38,7 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, 4, attrs); + r =3D memory_region_dispatch_read(mr, addr1, &val, size_memop(4), = attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap32(val); @@ -114,7 +114,7 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, 8, attrs); + r =3D memory_region_dispatch_read(mr, addr1, &val, size_memop(8), = attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap64(val); @@ -188,7 +188,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, 1, attrs); + r =3D memory_region_dispatch_read(mr, addr1, &val, size_memop(1), = attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -224,7 +224,7 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, 2, attrs); + r =3D memory_region_dispatch_read(mr, addr1, &val, size_memop(2), = attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap16(val); @@ -300,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, 4, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(4), = attrs); } else { ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); stl_p(ptr, val); @@ -346,7 +346,7 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, val =3D bswap32(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, 4, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(4), = attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -408,7 +408,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL, mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (!memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, 1, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(1), = attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -451,7 +451,7 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, val =3D bswap16(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, 2, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(2), = attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -524,7 +524,7 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, val =3D bswap64(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, 8, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(8), = attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:29:23 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 10/26] cputlb: Access MemoryRegion with MemOp Thread-Index: AQHVTPo3/fbgDfmaOEuIplRQ5wIAjA== Date: Wed, 7 Aug 2019 08:29:23 +0000 Message-ID: <1565166562774.65589@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.72 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 10/26] cputlb: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The memory_region_dispatch_{read|write} operand "unsigned size" is being converted into a "MemOp op". Convert interfaces by using no-op size_memop. After all interfaces are converted, size_memop will be implemented and the memory_region_dispatch_{read|write} operand "unsigned size" will be converted into a "MemOp op". As size_memop is a no-op, this patch does not change any behaviour. Signed-off-by: Tony Nguyen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 523be4c..6c83878 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -906,8 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, - &val, size, iotlbentry->attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size= ), + iotlbentry->attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - @@ -947,8 +947,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, - val, size, iotlbentry->attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, size_memop(size= ), + iotlbentry->attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - -- 1.8.3.1 ? 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X-Received-From: 62.239.224.236 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 11/26] memory: Access MemoryRegion with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Convert memory_region_dispatch_{read|write} operand "unsigned size" into a "MemOp op". Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- include/exec/memop.h | 18 +++++++++++++----- include/exec/memory.h | 9 +++++---- memory.c | 7 +++++-- 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index 5c5769e..4a4212d 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -12,6 +12,8 @@ #ifndef MEMOP_H #define MEMOP_H +#include "qemu/host-utils.h" + typedef enum MemOp { MO_8 =3D 0, MO_16 =3D 1, @@ -107,14 +109,20 @@ typedef enum MemOp { MO_SSIZE =3D MO_SIZE | MO_SIGN, } MemOp; +/* MemOp to size in bytes. */ +static inline unsigned memop_size(MemOp op) +{ + return 1 << ((op) & MO_SIZE); +} + /* Size in bytes to MemOp. */ static inline MemOp size_memop(unsigned size) { - /* - * FIXME: No-op to aid conversion of memory_region_dispatch_{read|writ= e} - * "unsigned size" operand into a "MemOp op". - */ - return size; +#ifdef CONFIG_DEBUG_TCG + /* Power of 2 up to 8. */ + assert((size & (size - 1)) =3D=3D 0 && size >=3D 1 && size <=3D 8); +#endif + return ctz32(size); } #endif diff --git a/include/exec/memory.h b/include/exec/memory.h index bb0961d..975b86a 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -19,6 +19,7 @@ #include "exec/cpu-common.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" +#include "exec/memop.h" #include "exec/ramlist.h" #include "qemu/queue.h" #include "qemu/int128.h" @@ -1731,13 +1732,13 @@ void mtree_info(bool flatview, bool dispatch_tree, = bool owner); * @mr: #MemoryRegion to access * @addr: address within that region * @pval: pointer to uint64_t which the data is written to - * @size: size of the access in bytes + * @op: size, sign, and endianness of the memory operation * @attrs: memory transaction attributes to use for the access */ MemTxResult memory_region_dispatch_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, - unsigned size, + MemOp op, MemTxAttrs attrs); /** * memory_region_dispatch_write: perform a write directly to the specified @@ -1746,13 +1747,13 @@ MemTxResult memory_region_dispatch_read(MemoryRegio= n *mr, * @mr: #MemoryRegion to access * @addr: address within that region * @data: data to write - * @size: size of the access in bytes + * @op: size, sign, and endianness of the memory operation * @attrs: memory transaction attributes to use for the access */ MemTxResult memory_region_dispatch_write(MemoryRegion *mr, hwaddr addr, uint64_t data, - unsigned size, + MemOp op, MemTxAttrs attrs); /** diff --git a/memory.c b/memory.c index 5d8c9a9..89ea4fb 100644 --- a/memory.c +++ b/memory.c @@ -1439,9 +1439,10 @@ static MemTxResult memory_region_dispatch_read1(Memo= ryRegion *mr, MemTxResult memory_region_dispatch_read(MemoryRegion *mr, hwaddr addr, uint64_t *pval, - unsigned size, + MemOp op, MemTxAttrs attrs) { + unsigned size =3D memop_size(op); MemTxResult r; if (!memory_region_access_valid(mr, addr, size, false, attrs)) { @@ -1483,9 +1484,11 @@ static bool memory_region_dispatch_write_eventfds(Me= moryRegion *mr, MemTxResult memory_region_dispatch_write(MemoryRegion *mr, hwaddr addr, uint64_t data, - unsigned size, + MemOp op, MemTxAttrs attrs) { + unsigned size =3D memop_size(op); + if (!memory_region_access_valid(mr, addr, size, true, attrs)) { unassigned_mem_write(mr, addr, data, size); return MEMTX_DECODE_ERROR; -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:30:04 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 12/26] hw/s390x: Hard code size with MO_{8|16|32|64} Thread-Index: AQHVTPpQM7LT8hhvO0OR23cGISCqIg== Date: Wed, 7 Aug 2019 08:30:04 +0000 Message-ID: <1565166604452.72353@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.80 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 12/26] hw/s390x: Hard code size with MO_{8|16|32|64} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Temporarily no-op size_memop was introduced to aid the conversion of memory_region_dispatch_{read|write} operand "unsigned size" into "MemOp op". Now size_memop is implemented, again hard coded size but with MO_{8|16|32|64}. This is more expressive and avoid size_memop calls. Signed-off-by: Tony Nguyen Reviewed-by: Cornelia Huck Reviewed-by: Richard Henderson --- hw/s390x/s390-pci-inst.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 0c958fc..0e92a37 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -782,8 +782,7 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8= _t r3, uint64_t gaddr, for (i =3D 0; i < len / 8; i++) { result =3D memory_region_dispatch_write(mr, offset + i * 8, ldq_p(buffer + i * 8), - size_memop(8), - MEMTXATTRS_UNSPECIFIED); + MO_64, MEMTXATTRS_UNSPECIFIE= D); if (result !=3D MEMTX_OK) { s390_program_interrupt(env, PGM_OPERAND, 6, ra); return 0; -- 1.8.3.1 ? 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Wed, 7 Aug 2019 09:30:28 +0100 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 13/26] target/mips: Hard code size with MO_{8|16|32|64} Thread-Index: AQHVTPpe3pO2B8oHbkS8tiFNOyPXPg== Date: Wed, 7 Aug 2019 08:30:28 +0000 Message-ID: <1565166627824.57868@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 213.121.35.80 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 13/26] target/mips: Hard code size with MO_{8|16|32|64} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Temporarily no-op size_memop was introduced to aid the conversion of memory_region_dispatch_{read|write} operand "unsigned size" into "MemOp op". Now size_memop is implemented, again hard coded size but with MO_{8|16|32|64}. This is more expressive and avoid size_memop calls. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- target/mips/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 1c72a00..e79f99d 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, target_ulong a= ddr, uint32_t op) if (op =3D=3D 9) { /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - size_memop(8), MEMTXATTRS_UNSPECIFIED= ); + MO_64, MEMTXATTRS_UNSPECIFIED); } else if (op =3D=3D 5) { /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - size_memop(8), MEMTXATTRS_UNSPECIFIED); + MO_64, MEMTXATTRS_UNSPECIFIED); } #endif } -- 1.8.3.1 ? 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boundary="===============5576793863668627418==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============5576793863668627418== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516664488325395btcom_" --_000_156516664488325395btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Temporarily no-op size_memop was introduced to aid the conversion of memory_region_dispatch_{read|write} operand "unsigned size" into "MemOp op". Now size_memop is implemented, again hard coded size but with MO_{8|16|32|64}. This is more expressive and avoid size_memop calls. Signed-off-by: Tony Nguyen --- memory_ldst.inc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index 1e8a2fc..de658c4 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -38,7 +38,7 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, size_memop(4), = attrs); + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap32(val); @@ -114,7 +114,7 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, size_memop(8), = attrs); + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap64(val); @@ -188,7 +188,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, size_memop(1), = attrs); + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -224,7 +224,7 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, size_memop(2), = attrs); + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { val =3D bswap16(val); @@ -300,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL= , if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(4), = attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); } else { ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); stl_p(ptr, val); @@ -346,7 +346,7 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, val =3D bswap32(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(4), = attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -408,7 +408,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL, mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (!memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(1), = attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_8, attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -451,7 +451,7 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, val =3D bswap16(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(2), = attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_16, attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -524,7 +524,7 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, val =3D bswap64(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, size_memop(8), = attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_64, attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); -- 1.8.3.1 ? --_000_156516664488325395btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Temporarily no-op size_memop was intr= oduced to aid the conversion of
memory_region_dispatch_{read|write} operand "unsigned size" = into
"MemOp op".

Now size_memop is implemented, again hard coded size but with
MO_{8|16|32|64}. This is more expressive and avoid size_memop calls.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 memory_ldst.inc.c | 18 ++++++++&= #43;---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index 1e8a2fc..de658c4 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -38,7 +38,7 @@ static inline uint32_t glue(address_space_ldl_in= ternal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, size_memop(4), attrs);
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_32, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D DEVICE_LITTLE_ENDI= AN) {
             val =3D bswap32(val);<= /div>
@@ -114,7 +114,7 @@ static inline uint64_t glue(address_space_ldq_= internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, size_memop(8), attrs);
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_64, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D DEVICE_LITTLE_ENDI= AN) {
             val =3D bswap64(val);<= /div>
@@ -188,7 +188,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1= _DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, size_memop(1), attrs);
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_8, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -224,7 +224,7 @@ static inline uint32_t glue(address_space_lduw= _internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, size_memop(2), attrs);
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_16, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D DEVICE_LITTLE_ENDI= AN) {
             val =3D bswap16(val);<= /div>
@@ -300,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(= ARG1_DECL,
     if (l < 4 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
 
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, size_memop(4), attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32, attrs);
     } else {
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
         stl_p(ptr, val);
@@ -346,7 +346,7 @@ static inline void glue(address_space_stl_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap32(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, size_memop(4), attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -408,7 +408,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL= ,
     mr =3D TRANSLATE(addr, &addr1, &l, true, a= ttrs);
     if (!memory_access_is_direct(mr, true)) {
         release_lock |=3D prepare_mmio_acces= s(mr);
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, size_memop(1), attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_8, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -451,7 +451,7 @@ static inline void glue(address_space_stw_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap16(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, size_memop(2), attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_16, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -524,7 +524,7 @@ static void glue(address_space_stq_internal, S= UFFIX)(ARG1_DECL,
             val =3D bswap64(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, size_memop(8), attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_64, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
-- 
1.8.3.1

​

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boundary="===============6081151666295021508==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============6081151666295021508== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516666883025608btcom_" --_000_156516666883025608btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation for replacing device_endian with MemOp. Device realizing code with MemorRegionOps endianness as DEVICE_NATIVE_ENDIAN is not common code. Corrected devices were identified by making the declaration of DEVICE_NATIVE_ENDIAN conditional upon NEED_CPU_H and then listing what failed to compile. Signed-off-by: Tony Nguyen --- hw/audio/Makefile.objs | 11 ++++++----- hw/block/Makefile.objs | 8 ++++---- hw/char/Makefile.objs | 22 +++++++++++----------- hw/core/Makefile.objs | 2 +- hw/display/Makefile.objs | 10 +++++----- hw/dma/Makefile.objs | 18 +++++++++--------- hw/gpio/Makefile.objs | 6 +++--- hw/i2c/Makefile.objs | 8 ++++---- hw/input/Makefile.objs | 4 ++-- hw/intc/Makefile.objs | 19 ++++++++++--------- hw/ipack/Makefile.objs | 2 +- hw/isa/Makefile.objs | 2 +- hw/misc/Makefile.objs | 18 +++++++++--------- hw/net/Makefile.objs | 14 +++++++------- hw/pci-host/Makefile.objs | 6 +++--- hw/scsi/Makefile.objs | 2 +- hw/sd/Makefile.objs | 2 +- hw/ssi/Makefile.objs | 10 +++++----- hw/timer/Makefile.objs | 39 ++++++++++++++++++++------------------- hw/virtio/Makefile.objs | 2 +- 20 files changed, 104 insertions(+), 101 deletions(-) diff --git a/hw/audio/Makefile.objs b/hw/audio/Makefile.objs index 63db383..40b26c6 100644 --- a/hw/audio/Makefile.objs +++ b/hw/audio/Makefile.objs @@ -5,14 +5,15 @@ common-obj-$(CONFIG_AC97) +=3D ac97.o common-obj-$(CONFIG_ADLIB) +=3D fmopl.o adlib.o common-obj-$(CONFIG_GUS) +=3D gus.o gusemu_hal.o gusemu_mixer.o common-obj-$(CONFIG_CS4231A) +=3D cs4231a.o -common-obj-$(CONFIG_HDA) +=3D intel-hda.o hda-codec.o +common-obj-$(CONFIG_HDA) +=3D hda-codec.o +obj-$(CONFIG_HDA) +=3D intel-hda.o common-obj-$(CONFIG_PCSPK) +=3D pcspk.o common-obj-$(CONFIG_WM8750) +=3D wm8750.o -common-obj-$(CONFIG_PL041) +=3D pl041.o lm4549.o +obj-$(CONFIG_PL041) +=3D pl041.o lm4549.o -common-obj-$(CONFIG_CS4231) +=3D cs4231.o -common-obj-$(CONFIG_MARVELL_88W8618) +=3D marvell_88w8618.o -common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-ac97.o +obj-$(CONFIG_CS4231) +=3D cs4231.o +obj-$(CONFIG_MARVELL_88W8618) +=3D marvell_88w8618.o +obj-$(CONFIG_MILKYMIST) +=3D milkymist-ac97.o common-obj-y +=3D soundhw.o diff --git a/hw/block/Makefile.objs b/hw/block/Makefile.objs index f5f643f..9098cda 100644 --- a/hw/block/Makefile.objs +++ b/hw/block/Makefile.objs @@ -1,12 +1,12 @@ common-obj-y +=3D block.o cdrom.o hd-geometry.o -common-obj-$(CONFIG_FDC) +=3D fdc.o +obj-$(CONFIG_FDC) +=3D fdc.o common-obj-$(CONFIG_SSI_M25P80) +=3D m25p80.o common-obj-$(CONFIG_NAND) +=3D nand.o -common-obj-$(CONFIG_PFLASH_CFI01) +=3D pflash_cfi01.o -common-obj-$(CONFIG_PFLASH_CFI02) +=3D pflash_cfi02.o +obj-$(CONFIG_PFLASH_CFI01) +=3D pflash_cfi01.o +obj-$(CONFIG_PFLASH_CFI02) +=3D pflash_cfi02.o common-obj-$(CONFIG_XEN) +=3D xen-block.o common-obj-$(CONFIG_ECC) +=3D ecc.o -common-obj-$(CONFIG_ONENAND) +=3D onenand.o +obj-$(CONFIG_ONENAND) +=3D onenand.o common-obj-$(CONFIG_NVME_PCI) +=3D nvme.o obj-$(CONFIG_SH4) +=3D tc58128.o diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 02d8a66..af3e76a 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -1,17 +1,17 @@ common-obj-$(CONFIG_IPACK) +=3D ipoctal232.o -common-obj-$(CONFIG_ESCC) +=3D escc.o +obj-$(CONFIG_ESCC) +=3D escc.o common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_uart.o -common-obj-$(CONFIG_PARALLEL) +=3D parallel.o +obj-$(CONFIG_PARALLEL) +=3D parallel.o common-obj-$(CONFIG_ISA_BUS) +=3D parallel-isa.o -common-obj-$(CONFIG_PL011) +=3D pl011.o -common-obj-$(CONFIG_SERIAL) +=3D serial.o +obj-$(CONFIG_PL011) +=3D pl011.o +obj-$(CONFIG_SERIAL) +=3D serial.o common-obj-$(CONFIG_SERIAL_ISA) +=3D serial-isa.o common-obj-$(CONFIG_SERIAL_PCI) +=3D serial-pci.o common-obj-$(CONFIG_SERIAL_PCI_MULTI) +=3D serial-pci-multi.o common-obj-$(CONFIG_VIRTIO_SERIAL) +=3D virtio-console.o -common-obj-$(CONFIG_XILINX) +=3D xilinx_uartlite.o +obj-$(CONFIG_XILINX) +=3D xilinx_uartlite.o common-obj-$(CONFIG_XEN) +=3D xen_console.o -common-obj-$(CONFIG_CADENCE) +=3D cadence_uart.o +obj-$(CONFIG_CADENCE) +=3D cadence_uart.o obj-$(CONFIG_EXYNOS4) +=3D exynos4210_uart.o obj-$(CONFIG_COLDFIRE) +=3D mcf_uart.o @@ -23,13 +23,13 @@ obj-$(CONFIG_STM32F2XX_USART) +=3D stm32f2xx_usart.o obj-$(CONFIG_RASPI) +=3D bcm2835_aux.o common-obj-$(CONFIG_CMSDK_APB_UART) +=3D cmsdk-apb-uart.o -common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_ser.o +obj-$(CONFIG_ETRAXFS) +=3D etraxfs_ser.o common-obj-$(CONFIG_ISA_DEBUG) +=3D debugcon.o -common-obj-$(CONFIG_GRLIB) +=3D grlib_apbuart.o -common-obj-$(CONFIG_IMX) +=3D imx_serial.o +obj-$(CONFIG_GRLIB) +=3D grlib_apbuart.o +obj-$(CONFIG_IMX) +=3D imx_serial.o common-obj-$(CONFIG_LM32) +=3D lm32_juart.o -common-obj-$(CONFIG_LM32) +=3D lm32_uart.o -common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-uart.o +obj-$(CONFIG_LM32) +=3D lm32_uart.o +obj-$(CONFIG_MILKYMIST) +=3D milkymist-uart.o common-obj-$(CONFIG_SCLPCONSOLE) +=3D sclpconsole.o sclpconsole-lm.o obj-$(CONFIG_VIRTIO) +=3D virtio-serial-bus.o diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index f8481d9..1b336c6 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -9,7 +9,7 @@ common-obj-y +=3D hotplug.o common-obj-$(CONFIG_SOFTMMU) +=3D nmi.o common-obj-$(CONFIG_SOFTMMU) +=3D vm-change-state-handler.o -common-obj-$(CONFIG_EMPTY_SLOT) +=3D empty_slot.o +obj-$(CONFIG_EMPTY_SLOT) +=3D empty_slot.o common-obj-$(CONFIG_XILINX_AXI) +=3D stream.o common-obj-$(CONFIG_PTIMER) +=3D ptimer.o common-obj-$(CONFIG_SOFTMMU) +=3D sysbus.o diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs index a64998f..53c3efb 100644 --- a/hw/display/Makefile.objs +++ b/hw/display/Makefile.objs @@ -8,8 +8,8 @@ common-obj-$(CONFIG_ADS7846) +=3D ads7846.o common-obj-$(CONFIG_VGA_CIRRUS) +=3D cirrus_vga.o common-obj-$(call land,$(CONFIG_VGA_CIRRUS),$(CONFIG_VGA_ISA))+=3Dcirrus_v= ga_isa.o common-obj-$(CONFIG_G364FB) +=3D g364fb.o -common-obj-$(CONFIG_JAZZ_LED) +=3D jazz_led.o -common-obj-$(CONFIG_PL110) +=3D pl110.o +obj-$(CONFIG_JAZZ_LED) +=3D jazz_led.o +obj-$(CONFIG_PL110) +=3D pl110.o common-obj-$(CONFIG_SII9022) +=3D sii9022.o common-obj-$(CONFIG_SSD0303) +=3D ssd0303.o common-obj-$(CONFIG_SSD0323) +=3D ssd0323.o @@ -17,15 +17,15 @@ common-obj-$(CONFIG_XEN) +=3D xenfb.o common-obj-$(CONFIG_VGA_PCI) +=3D vga-pci.o common-obj-$(CONFIG_VGA_ISA) +=3D vga-isa.o -common-obj-$(CONFIG_VGA_ISA_MM) +=3D vga-isa-mm.o +obj-$(CONFIG_VGA_ISA_MM) +=3D vga-isa-mm.o common-obj-$(CONFIG_VMWARE_VGA) +=3D vmware_vga.o common-obj-$(CONFIG_BOCHS_DISPLAY) +=3D bochs-display.o common-obj-$(CONFIG_BLIZZARD) +=3D blizzard.o -common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_fimd.o +obj-$(CONFIG_EXYNOS4) +=3D exynos4210_fimd.o common-obj-$(CONFIG_FRAMEBUFFER) +=3D framebuffer.o obj-$(CONFIG_MILKYMIST) +=3D milkymist-vgafb.o -common-obj-$(CONFIG_ZAURUS) +=3D tc6393xb.o +obj-$(CONFIG_ZAURUS) +=3D tc6393xb.o obj-$(CONFIG_MILKYMIST_TMU2) +=3D milkymist-tmu2.o milkymist-tmu2.o-cflags :=3D $(X11_CFLAGS) $(OPENGL_CFLAGS) diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs index 8b39f9c..7e17776 100644 --- a/hw/dma/Makefile.objs +++ b/hw/dma/Makefile.objs @@ -1,17 +1,17 @@ -common-obj-$(CONFIG_PUV3) +=3D puv3_dma.o -common-obj-$(CONFIG_RC4030) +=3D rc4030.o -common-obj-$(CONFIG_PL080) +=3D pl080.o -common-obj-$(CONFIG_PL330) +=3D pl330.o +obj-$(CONFIG_PUV3) +=3D puv3_dma.o +obj-$(CONFIG_RC4030) +=3D rc4030.o +obj-$(CONFIG_PL080) +=3D pl080.o +obj-$(CONFIG_PL330) +=3D pl330.o common-obj-$(CONFIG_I82374) +=3D i82374.o -common-obj-$(CONFIG_I8257) +=3D i8257.o -common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axidma.o +obj-$(CONFIG_I8257) +=3D i8257.o +obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axidma.o common-obj-$(CONFIG_ZYNQ_DEVCFG) +=3D xlnx-zynq-devcfg.o -common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_dma.o -common-obj-$(CONFIG_STP2000) +=3D sparc32_dma.o +obj-$(CONFIG_ETRAXFS) +=3D etraxfs_dma.o +obj-$(CONFIG_STP2000) +=3D sparc32_dma.o obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx_dpdma.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx_dpdma.o common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zdma.o obj-$(CONFIG_OMAP) +=3D omap_dma.o soc_dma.o obj-$(CONFIG_PXA2XX) +=3D pxa2xx_dma.o -common-obj-$(CONFIG_RASPI) +=3D bcm2835_dma.o +obj-$(CONFIG_RASPI) +=3D bcm2835_dma.o diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs index e5da0cb..9d297fd 100644 --- a/hw/gpio/Makefile.objs +++ b/hw/gpio/Makefile.objs @@ -1,7 +1,7 @@ common-obj-$(CONFIG_MAX7310) +=3D max7310.o -common-obj-$(CONFIG_PL061) +=3D pl061.o -common-obj-$(CONFIG_PUV3) +=3D puv3_gpio.o -common-obj-$(CONFIG_ZAURUS) +=3D zaurus.o +obj-$(CONFIG_PL061) +=3D pl061.o +obj-$(CONFIG_PUV3) +=3D puv3_gpio.o +obj-$(CONFIG_ZAURUS) +=3D zaurus.o common-obj-$(CONFIG_E500) +=3D mpc8xxx.o common-obj-$(CONFIG_GPIO_KEY) +=3D gpio_key.o diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs index d7073a4..9c8839c 100644 --- a/hw/i2c/Makefile.objs +++ b/hw/i2c/Makefile.objs @@ -1,13 +1,13 @@ common-obj-$(CONFIG_I2C) +=3D core.o smbus_slave.o smbus_master.o common-obj-$(CONFIG_SMBUS_EEPROM) +=3D smbus_eeprom.o -common-obj-$(CONFIG_VERSATILE_I2C) +=3D versatile_i2c.o +obj-$(CONFIG_VERSATILE_I2C) +=3D versatile_i2c.o common-obj-$(CONFIG_ACPI_X86_ICH) +=3D smbus_ich9.o common-obj-$(CONFIG_ACPI_SMBUS) +=3D pm_smbus.o common-obj-$(CONFIG_BITBANG_I2C) +=3D bitbang_i2c.o -common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_i2c.o -common-obj-$(CONFIG_IMX_I2C) +=3D imx_i2c.o +obj-$(CONFIG_EXYNOS4) +=3D exynos4210_i2c.o +obj-$(CONFIG_IMX_I2C) +=3D imx_i2c.o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_i2c.o common-obj-$(CONFIG_NRF51_SOC) +=3D microbit_i2c.o -common-obj-$(CONFIG_MPC_I2C) +=3D mpc_i2c.o +obj-$(CONFIG_MPC_I2C) +=3D mpc_i2c.o obj-$(CONFIG_OMAP) +=3D omap_i2c.o obj-$(CONFIG_PPC4XX) +=3D ppc4xx_i2c.o diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs index a1bc502..e096cc5 100644 --- a/hw/input/Makefile.objs +++ b/hw/input/Makefile.objs @@ -1,8 +1,8 @@ common-obj-$(CONFIG_ADB) +=3D adb.o adb-mouse.o adb-kbd.o common-obj-y +=3D hid.o common-obj-$(CONFIG_LM832X) +=3D lm832x.o -common-obj-$(CONFIG_PCKBD) +=3D pckbd.o -common-obj-$(CONFIG_PL050) +=3D pl050.o +obj-$(CONFIG_PCKBD) +=3D pckbd.o +obj-$(CONFIG_PL050) +=3D pl050.o common-obj-$(CONFIG_PS2) +=3D ps2.o common-obj-$(CONFIG_STELLARIS_INPUT) +=3D stellaris_input.o common-obj-$(CONFIG_TSC2005) +=3D tsc2005.o diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs index 03019b9..6d7ba84 100644 --- a/hw/intc/Makefile.objs +++ b/hw/intc/Makefile.objs @@ -1,24 +1,25 @@ common-obj-$(CONFIG_HEATHROW_PIC) +=3D heathrow_pic.o common-obj-$(CONFIG_I8259) +=3D i8259_common.o i8259.o -common-obj-$(CONFIG_PL190) +=3D pl190.o -common-obj-$(CONFIG_PUV3) +=3D puv3_intc.o -common-obj-$(CONFIG_XILINX) +=3D xilinx_intc.o +obj-$(CONFIG_PL190) +=3D pl190.o +obj-$(CONFIG_PUV3) +=3D puv3_intc.o +obj-$(CONFIG_XILINX) +=3D xilinx_intc.o common-obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-pmu-iomod-intc.o common-obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-zynqmp-ipi.o -common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_pic.o -common-obj-$(CONFIG_IMX) +=3D imx_avic.o imx_gpcv2.o +obj-$(CONFIG_ETRAXFS) +=3D etraxfs_pic.o +obj-$(CONFIG_IMX) +=3D imx_avic.o +obj-$(CONFIG_IMX) +=3D imx_gpcv2.o common-obj-$(CONFIG_LM32) +=3D lm32_pic.o common-obj-$(CONFIG_REALVIEW) +=3D realview_gic.o -common-obj-$(CONFIG_SLAVIO) +=3D slavio_intctl.o +obj-$(CONFIG_SLAVIO) +=3D slavio_intctl.o common-obj-$(CONFIG_IOAPIC) +=3D ioapic_common.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gic_common.o -common-obj-$(CONFIG_ARM_GIC) +=3D arm_gic.o +obj-$(CONFIG_ARM_GIC) +=3D arm_gic.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv2m.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_common.o -common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3.o +obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_dist.o common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_redist.o -common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_its_common.o +obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_its_common.o common-obj-$(CONFIG_OPENPIC) +=3D openpic.o common-obj-y +=3D intc.o diff --git a/hw/ipack/Makefile.objs b/hw/ipack/Makefile.objs index 8b9bdcb..a7c5485 100644 --- a/hw/ipack/Makefile.objs +++ b/hw/ipack/Makefile.objs @@ -1,2 +1,2 @@ common-obj-$(CONFIG_IPACK) +=3D ipack.o -common-obj-$(CONFIG_IPACK) +=3D tpci200.o +obj-$(CONFIG_IPACK) +=3D tpci200.o diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs index 9e106df..898b504 100644 --- a/hw/isa/Makefile.objs +++ b/hw/isa/Makefile.objs @@ -4,7 +4,7 @@ common-obj-$(CONFIG_APM) +=3D apm.o common-obj-$(CONFIG_I82378) +=3D i82378.o common-obj-$(CONFIG_PC87312) +=3D pc87312.o common-obj-$(CONFIG_PIIX4) +=3D piix4.o -common-obj-$(CONFIG_VT82C686) +=3D vt82c686.o +obj-$(CONFIG_VT82C686) +=3D vt82c686.o common-obj-$(CONFIG_SMC37C669) +=3D smc37c669-superio.o obj-$(CONFIG_LPC_ICH9) +=3D lpc_ich9.o diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index e9aab51..6ee5a8a 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-$(CONFIG_APPLESMC) +=3D applesmc.o +obj-$(CONFIG_APPLESMC) +=3D applesmc.o common-obj-$(CONFIG_MAX111X) +=3D max111x.o common-obj-$(CONFIG_TMP105) +=3D tmp105.o common-obj-$(CONFIG_TMP421) +=3D tmp421.o @@ -6,23 +6,23 @@ common-obj-$(CONFIG_ISA_DEBUG) +=3D debugexit.o common-obj-$(CONFIG_SGA) +=3D sga.o common-obj-$(CONFIG_ISA_TESTDEV) +=3D pc-testdev.o common-obj-$(CONFIG_PCI_TESTDEV) +=3D pci-testdev.o -common-obj-$(CONFIG_EDU) +=3D edu.o +obj-$(CONFIG_EDU) +=3D edu.o common-obj-$(CONFIG_PCA9552) +=3D pca9552.o -common-obj-y +=3D unimp.o +obj-y +=3D unimp.o common-obj-$(CONFIG_FW_CFG_DMA) +=3D vmcoreinfo.o # ARM devices -common-obj-$(CONFIG_PL310) +=3D arm_l2x0.o -common-obj-$(CONFIG_INTEGRATOR_DEBUG) +=3D arm_integrator_debug.o -common-obj-$(CONFIG_A9SCU) +=3D a9scu.o -common-obj-$(CONFIG_ARM11SCU) +=3D arm11scu.o +obj-$(CONFIG_PL310) +=3D arm_l2x0.o +obj-$(CONFIG_INTEGRATOR_DEBUG) +=3D arm_integrator_debug.o +obj-$(CONFIG_A9SCU) +=3D a9scu.o +obj-$(CONFIG_ARM11SCU) +=3D arm11scu.o # Mac devices -common-obj-$(CONFIG_MOS6522) +=3D mos6522.o +obj-$(CONFIG_MOS6522) +=3D mos6522.o # PKUnity SoC devices -common-obj-$(CONFIG_PUV3) +=3D puv3_pm.o +obj-$(CONFIG_PUV3) +=3D puv3_pm.o common-obj-$(CONFIG_MACIO) +=3D macio/ diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs index 9904273..1ff7b59 100644 --- a/hw/net/Makefile.objs +++ b/hw/net/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-$(CONFIG_DP8393X) +=3D dp8393x.o +obj-$(CONFIG_DP8393X) +=3D dp8393x.o common-obj-$(CONFIG_XEN) +=3D xen_nic.o common-obj-$(CONFIG_NE2000_COMMON) +=3D ne2000.o @@ -14,19 +14,19 @@ common-obj-$(CONFIG_RTL8139_PCI) +=3D rtl8139.o common-obj-$(CONFIG_VMXNET3_PCI) +=3D net_tx_pkt.o net_rx_pkt.o common-obj-$(CONFIG_VMXNET3_PCI) +=3D vmxnet3.o -common-obj-$(CONFIG_SMC91C111) +=3D smc91c111.o -common-obj-$(CONFIG_LAN9118) +=3D lan9118.o +obj-$(CONFIG_SMC91C111) +=3D smc91c111.o +obj-$(CONFIG_LAN9118) +=3D lan9118.o common-obj-$(CONFIG_NE2000_ISA) +=3D ne2000-isa.o common-obj-$(CONFIG_OPENCORES_ETH) +=3D opencores_eth.o common-obj-$(CONFIG_XGMAC) +=3D xgmac.o common-obj-$(CONFIG_MIPSNET) +=3D mipsnet.o common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axienet.o -common-obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o -common-obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o +obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o +obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o common-obj-$(CONFIG_CADENCE) +=3D cadence_gem.o -common-obj-$(CONFIG_STELLARIS_ENET) +=3D stellaris_enet.o -common-obj-$(CONFIG_LANCE) +=3D lance.o +obj-$(CONFIG_STELLARIS_ENET) +=3D stellaris_enet.o +obj-$(CONFIG_LANCE) +=3D lance.o common-obj-$(CONFIG_SUNHME) +=3D sunhme.o common-obj-$(CONFIG_FTGMAC100) +=3D ftgmac100.o common-obj-$(CONFIG_SUNGEM) +=3D sungem.o diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs index a9cd3e0..0970e8e 100644 --- a/hw/pci-host/Makefile.objs +++ b/hw/pci-host/Makefile.objs @@ -9,12 +9,12 @@ common-obj-$(CONFIG_UNIN_PCI) +=3D uninorth.o common-obj-$(CONFIG_PPCE500_PCI) +=3D ppce500.o # ARM devices -common-obj-$(CONFIG_VERSATILE_PCI) +=3D versatile.o +obj-$(CONFIG_VERSATILE_PCI) +=3D versatile.o common-obj-$(CONFIG_PCI_SABRE) +=3D sabre.o -common-obj-$(CONFIG_FULONG) +=3D bonito.o +obj-$(CONFIG_FULONG) +=3D bonito.o common-obj-$(CONFIG_PCI_PIIX) +=3D piix.o -common-obj-$(CONFIG_PCI_EXPRESS_Q35) +=3D q35.o +obj-$(CONFIG_PCI_EXPRESS_Q35) +=3D q35.o common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) +=3D gpex.o common-obj-$(CONFIG_PCI_EXPRESS_XILINX) +=3D xilinx-pcie.o diff --git a/hw/scsi/Makefile.objs b/hw/scsi/Makefile.objs index 54b36ed..418af9a 100644 --- a/hw/scsi/Makefile.objs +++ b/hw/scsi/Makefile.objs @@ -4,7 +4,7 @@ common-obj-$(CONFIG_LSI_SCSI_PCI) +=3D lsi53c895a.o common-obj-$(CONFIG_MPTSAS_SCSI_PCI) +=3D mptsas.o mptconfig.o mptendian.o common-obj-$(CONFIG_MEGASAS_SCSI_PCI) +=3D megasas.o common-obj-$(CONFIG_VMW_PVSCSI_SCSI_PCI) +=3D vmw_pvscsi.o -common-obj-$(CONFIG_ESP) +=3D esp.o +obj-$(CONFIG_ESP) +=3D esp.o common-obj-$(CONFIG_ESP_PCI) +=3D esp-pci.o obj-$(CONFIG_SPAPR_VSCSI) +=3D spapr_vscsi.o diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs index 0665727..a8cd6bf 100644 --- a/hw/sd/Makefile.objs +++ b/hw/sd/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-$(CONFIG_PL181) +=3D pl181.o +obj-$(CONFIG_PL181) +=3D pl181.o common-obj-$(CONFIG_SSI_SD) +=3D ssi-sd.o common-obj-$(CONFIG_SD) +=3D sd.o core.o sdmmc-internal.o common-obj-$(CONFIG_SDHCI) +=3D sdhci.o diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs index f5bcc65..b084802 100644 --- a/hw/ssi/Makefile.objs +++ b/hw/ssi/Makefile.objs @@ -1,10 +1,10 @@ -common-obj-$(CONFIG_PL022) +=3D pl022.o +obj-$(CONFIG_PL022) +=3D pl022.o common-obj-$(CONFIG_SSI) +=3D ssi.o -common-obj-$(CONFIG_XILINX_SPI) +=3D xilinx_spi.o -common-obj-$(CONFIG_XILINX_SPIPS) +=3D xilinx_spips.o +obj-$(CONFIG_XILINX_SPI) +=3D xilinx_spi.o +obj-$(CONFIG_XILINX_SPIPS) +=3D xilinx_spips.o common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_smc.o -common-obj-$(CONFIG_STM32F2XX_SPI) +=3D stm32f2xx_spi.o -common-obj-$(CONFIG_MSF2) +=3D mss-spi.o +obj-$(CONFIG_STM32F2XX_SPI) +=3D stm32f2xx_spi.o +obj-$(CONFIG_MSF2) +=3D mss-spi.o obj-$(CONFIG_OMAP) +=3D omap_spi.o obj-$(CONFIG_IMX) +=3D imx_spi.o diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index 123d92c..0a8f651 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -1,27 +1,27 @@ -common-obj-$(CONFIG_ARM_TIMER) +=3D arm_timer.o -common-obj-$(CONFIG_ARM_MPTIMER) +=3D arm_mptimer.o -common-obj-$(CONFIG_ARM_V7M) +=3D armv7m_systick.o -common-obj-$(CONFIG_A9_GTIMER) +=3D a9gtimer.o -common-obj-$(CONFIG_CADENCE) +=3D cadence_ttc.o +obj-$(CONFIG_ARM_TIMER) +=3D arm_timer.o +obj-$(CONFIG_ARM_MPTIMER) +=3D arm_mptimer.o +obj-$(CONFIG_ARM_V7M) +=3D armv7m_systick.o +obj-$(CONFIG_A9_GTIMER) +=3D a9gtimer.o +obj-$(CONFIG_CADENCE) +=3D cadence_ttc.o common-obj-$(CONFIG_DS1338) +=3D ds1338.o -common-obj-$(CONFIG_HPET) +=3D hpet.o +obj-$(CONFIG_HPET) +=3D hpet.o common-obj-$(CONFIG_I8254) +=3D i8254_common.o i8254.o common-obj-$(CONFIG_M41T80) +=3D m41t80.o common-obj-$(CONFIG_M48T59) +=3D m48t59.o ifeq ($(CONFIG_ISA_BUS),y) common-obj-$(CONFIG_M48T59) +=3D m48t59-isa.o endif -common-obj-$(CONFIG_PL031) +=3D pl031.o -common-obj-$(CONFIG_PUV3) +=3D puv3_ost.o +obj-$(CONFIG_PL031) +=3D pl031.o +obj-$(CONFIG_PUV3) +=3D puv3_ost.o common-obj-$(CONFIG_TWL92230) +=3D twl92230.o -common-obj-$(CONFIG_XILINX) +=3D xilinx_timer.o -common-obj-$(CONFIG_SLAVIO) +=3D slavio_timer.o +obj-$(CONFIG_XILINX) +=3D xilinx_timer.o +obj-$(CONFIG_SLAVIO) +=3D slavio_timer.o common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_timer.o -common-obj-$(CONFIG_GRLIB) +=3D grlib_gptimer.o -common-obj-$(CONFIG_IMX) +=3D imx_epit.o -common-obj-$(CONFIG_IMX) +=3D imx_gpt.o -common-obj-$(CONFIG_LM32) +=3D lm32_timer.o -common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-sysctl.o +obj-$(CONFIG_GRLIB) +=3D grlib_gptimer.o +obj-$(CONFIG_IMX) +=3D imx_epit.o +obj-$(CONFIG_IMX) +=3D imx_gpt.o +obj-$(CONFIG_LM32) +=3D lm32_timer.o +obj-$(CONFIG_MILKYMIST) +=3D milkymist-sysctl.o common-obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-zynqmp-rtc.o common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_timer.o @@ -40,10 +40,11 @@ obj-$(CONFIG_MC146818RTC) +=3D mc146818rtc.o obj-$(CONFIG_ALLWINNER_A10_PIT) +=3D allwinner-a10-pit.o -common-obj-$(CONFIG_STM32F2XX_TIMER) +=3D stm32f2xx_timer.o -common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o aspeed_rtc.o +obj-$(CONFIG_STM32F2XX_TIMER) +=3D stm32f2xx_timer.o +common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o +obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_rtc.o -common-obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o +obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o common-obj-$(CONFIG_CMSDK_APB_TIMER) +=3D cmsdk-apb-timer.o common-obj-$(CONFIG_CMSDK_APB_DUALTIMER) +=3D cmsdk-apb-dualtimer.o -common-obj-$(CONFIG_MSF2) +=3D mss-timer.o +obj-$(CONFIG_MSF2) +=3D mss-timer.o diff --git a/hw/virtio/Makefile.objs b/hw/virtio/Makefile.objs index 964ce78..573b1a9 100644 --- a/hw/virtio/Makefile.objs +++ b/hw/virtio/Makefile.objs @@ -8,7 +8,7 @@ obj-$(CONFIG_VHOST_USER) +=3D vhost-user.o common-obj-$(CONFIG_VIRTIO_RNG) +=3D virtio-rng.o common-obj-$(CONFIG_VIRTIO_PCI) +=3D virtio-pci.o -common-obj-$(CONFIG_VIRTIO_MMIO) +=3D virtio-mmio.o +obj-$(CONFIG_VIRTIO_MMIO) +=3D virtio-mmio.o obj-$(CONFIG_VIRTIO_BALLOON) +=3D virtio-balloon.o obj-$(CONFIG_VIRTIO_CRYPTO) +=3D virtio-crypto.o obj-$(call land,$(CONFIG_VIRTIO_CRYPTO),$(CONFIG_VIRTIO_PCI)) +=3D virtio-= crypto-pci.o -- 1.8.3.1 ? --_000_156516666883025608btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation for replacing device_endi= an with MemOp.

Device realizing code with MemorRegionOps endianness as
DEVICE_NATIVE_ENDIAN is not common code.

Corrected devices were identified by making the declaration of
DEVICE_NATIVE_ENDIAN conditional upon NEED_CPU_H and then listing
what failed to compile.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 hw/audio/Makefile.objs    | 11 ++++= 3;+-----
 hw/block/Makefile.objs    |  8 +++= 3;----
 hw/char/Makefile.objs     | 22 ++++= 3;++++++-----------
 hw/core/Makefile.objs     |  2 +-
 hw/display/Makefile.objs  | 10 +++++---= --
 hw/dma/Makefile.objs      | 18 +++= 3;+++++---------
 hw/gpio/Makefile.objs     |  6 +++---=
 hw/i2c/Makefile.objs      |  8 ++= 3;+----
 hw/input/Makefile.objs    |  4 ++--
 hw/intc/Makefile.objs     | 19 ++++= 3;+++++---------
 hw/ipack/Makefile.objs    |  2 +-
 hw/isa/Makefile.objs      |  2 +-
 hw/misc/Makefile.objs     | 18 ++++= 3;++++---------
 hw/net/Makefile.objs      | 14 +++= 3;+++-------
 hw/pci-host/Makefile.objs |  6 +++---
 hw/scsi/Makefile.objs     |  2 +-
 hw/sd/Makefile.objs       |  2 +-
 hw/ssi/Makefile.objs      | 10 +++= 3;+-----
 hw/timer/Makefile.objs    | 39 ++++= 3;++++++++++++++= 3;-------------------
 hw/virtio/Makefile.objs   |  2 +-
 20 files changed, 104 insertions(+), 101 deletions(-)

diff --git a/hw/audio/Makefile.objs b/hw/audio/Makefile.objs
index 63db383..40b26c6 100644
--- a/hw/audio/Makefile.objs
+++ b/hw/audio/Makefile.objs
@@ -5,14 +5,15 @@ common-obj-$(CONFIG_AC97) +=3D ac97.o
 common-obj-$(CONFIG_ADLIB) +=3D fmopl.o adlib.o
 common-obj-$(CONFIG_GUS) +=3D gus.o gusemu_hal.o gusemu_mixe= r.o
 common-obj-$(CONFIG_CS4231A) +=3D cs4231a.o
-common-obj-$(CONFIG_HDA) +=3D intel-hda.o hda-codec.o
+common-obj-$(CONFIG_HDA) +=3D hda-codec.o
+obj-$(CONFIG_HDA) +=3D intel-hda.o
 
 common-obj-$(CONFIG_PCSPK) +=3D pcspk.o
 common-obj-$(CONFIG_WM8750) +=3D wm8750.o
-common-obj-$(CONFIG_PL041) +=3D pl041.o lm4549.o
+obj-$(CONFIG_PL041) +=3D pl041.o lm4549.o
 
-common-obj-$(CONFIG_CS4231) +=3D cs4231.o
-common-obj-$(CONFIG_MARVELL_88W8618) +=3D marvell_88w8618.o
-common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-ac97.o
+obj-$(CONFIG_CS4231) +=3D cs4231.o
+obj-$(CONFIG_MARVELL_88W8618) +=3D marvell_88w8618.o
+obj-$(CONFIG_MILKYMIST) +=3D milkymist-ac97.o
 
 common-obj-y +=3D soundhw.o
diff --git a/hw/block/Makefile.objs b/hw/block/Makefile.objs
index f5f643f..9098cda 100644
--- a/hw/block/Makefile.objs
+++ b/hw/block/Makefile.objs
@@ -1,12 +1,12 @@
 common-obj-y +=3D block.o cdrom.o hd-geometry.o
-common-obj-$(CONFIG_FDC) +=3D fdc.o
+obj-$(CONFIG_FDC) +=3D fdc.o
 common-obj-$(CONFIG_SSI_M25P80) +=3D m25p80.o
 common-obj-$(CONFIG_NAND) +=3D nand.o
-common-obj-$(CONFIG_PFLASH_CFI01) +=3D pflash_cfi01.o
-common-obj-$(CONFIG_PFLASH_CFI02) +=3D pflash_cfi02.o
+obj-$(CONFIG_PFLASH_CFI01) +=3D pflash_cfi01.o
+obj-$(CONFIG_PFLASH_CFI02) +=3D pflash_cfi02.o
 common-obj-$(CONFIG_XEN) +=3D xen-block.o
 common-obj-$(CONFIG_ECC) +=3D ecc.o
-common-obj-$(CONFIG_ONENAND) +=3D onenand.o
+obj-$(CONFIG_ONENAND) +=3D onenand.o
 common-obj-$(CONFIG_NVME_PCI) +=3D nvme.o
 
 obj-$(CONFIG_SH4) +=3D tc58128.o
diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index 02d8a66..af3e76a 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -1,17 +1,17 @@
 common-obj-$(CONFIG_IPACK) +=3D ipoctal232.o
-common-obj-$(CONFIG_ESCC) +=3D escc.o
+obj-$(CONFIG_ESCC) +=3D escc.o
 common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_uart.o
-common-obj-$(CONFIG_PARALLEL) +=3D parallel.o
+obj-$(CONFIG_PARALLEL) +=3D parallel.o
 common-obj-$(CONFIG_ISA_BUS) +=3D parallel-isa.o
-common-obj-$(CONFIG_PL011) +=3D pl011.o
-common-obj-$(CONFIG_SERIAL) +=3D serial.o
+obj-$(CONFIG_PL011) +=3D pl011.o
+obj-$(CONFIG_SERIAL) +=3D serial.o
 common-obj-$(CONFIG_SERIAL_ISA) +=3D serial-isa.o
 common-obj-$(CONFIG_SERIAL_PCI) +=3D serial-pci.o
 common-obj-$(CONFIG_SERIAL_PCI_MULTI) +=3D serial-pci-multi.= o
 common-obj-$(CONFIG_VIRTIO_SERIAL) +=3D virtio-console.o
-common-obj-$(CONFIG_XILINX) +=3D xilinx_uartlite.o
+obj-$(CONFIG_XILINX) +=3D xilinx_uartlite.o
 common-obj-$(CONFIG_XEN) +=3D xen_console.o
-common-obj-$(CONFIG_CADENCE) +=3D cadence_uart.o
+obj-$(CONFIG_CADENCE) +=3D cadence_uart.o
 
 obj-$(CONFIG_EXYNOS4) +=3D exynos4210_uart.o
 obj-$(CONFIG_COLDFIRE) +=3D mcf_uart.o
@@ -23,13 +23,13 @@ obj-$(CONFIG_STM32F2XX_USART) +=3D stm32f2= xx_usart.o
 obj-$(CONFIG_RASPI) +=3D bcm2835_aux.o
 
 common-obj-$(CONFIG_CMSDK_APB_UART) +=3D cmsdk-apb-uart.o
-common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_ser.o
+obj-$(CONFIG_ETRAXFS) +=3D etraxfs_ser.o
 common-obj-$(CONFIG_ISA_DEBUG) +=3D debugcon.o
-common-obj-$(CONFIG_GRLIB) +=3D grlib_apbuart.o
-common-obj-$(CONFIG_IMX) +=3D imx_serial.o
+obj-$(CONFIG_GRLIB) +=3D grlib_apbuart.o
+obj-$(CONFIG_IMX) +=3D imx_serial.o
 common-obj-$(CONFIG_LM32) +=3D lm32_juart.o
-common-obj-$(CONFIG_LM32) +=3D lm32_uart.o
-common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-uart.o
+obj-$(CONFIG_LM32) +=3D lm32_uart.o
+obj-$(CONFIG_MILKYMIST) +=3D milkymist-uart.o
 common-obj-$(CONFIG_SCLPCONSOLE) +=3D sclpconsole.o sclpcons= ole-lm.o
 
 obj-$(CONFIG_VIRTIO) +=3D virtio-serial-bus.o
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index f8481d9..1b336c6 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -9,7 +9,7 @@ common-obj-y +=3D hotplug.o
 common-obj-$(CONFIG_SOFTMMU) +=3D nmi.o
 common-obj-$(CONFIG_SOFTMMU) +=3D vm-change-state-handler.o<= /div>
 
-common-obj-$(CONFIG_EMPTY_SLOT) +=3D empty_slot.o
+obj-$(CONFIG_EMPTY_SLOT) +=3D empty_slot.o
 common-obj-$(CONFIG_XILINX_AXI) +=3D stream.o
 common-obj-$(CONFIG_PTIMER) +=3D ptimer.o
 common-obj-$(CONFIG_SOFTMMU) +=3D sysbus.o
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index a64998f..53c3efb 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -8,8 +8,8 @@ common-obj-$(CONFIG_ADS7846) +=3D ads7846.o
 common-obj-$(CONFIG_VGA_CIRRUS) +=3D cirrus_vga.o
 common-obj-$(call land,$(CONFIG_VGA_CIRRUS),$(CONFIG_VGA_ISA))&#= 43;=3Dcirrus_vga_isa.o
 common-obj-$(CONFIG_G364FB) +=3D g364fb.o
-common-obj-$(CONFIG_JAZZ_LED) +=3D jazz_led.o
-common-obj-$(CONFIG_PL110) +=3D pl110.o
+obj-$(CONFIG_JAZZ_LED) +=3D jazz_led.o
+obj-$(CONFIG_PL110) +=3D pl110.o
 common-obj-$(CONFIG_SII9022) +=3D sii9022.o
 common-obj-$(CONFIG_SSD0303) +=3D ssd0303.o
 common-obj-$(CONFIG_SSD0323) +=3D ssd0323.o
@@ -17,15 +17,15 @@ common-obj-$(CONFIG_XEN) +=3D xenfb.o
 
 common-obj-$(CONFIG_VGA_PCI) +=3D vga-pci.o
 common-obj-$(CONFIG_VGA_ISA) +=3D vga-isa.o
-common-obj-$(CONFIG_VGA_ISA_MM) +=3D vga-isa-mm.o
+obj-$(CONFIG_VGA_ISA_MM) +=3D vga-isa-mm.o
 common-obj-$(CONFIG_VMWARE_VGA) +=3D vmware_vga.o
 common-obj-$(CONFIG_BOCHS_DISPLAY) +=3D bochs-display.o
 
 common-obj-$(CONFIG_BLIZZARD) +=3D blizzard.o
-common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_fimd.o
+obj-$(CONFIG_EXYNOS4) +=3D exynos4210_fimd.o
 common-obj-$(CONFIG_FRAMEBUFFER) +=3D framebuffer.o
 obj-$(CONFIG_MILKYMIST) +=3D milkymist-vgafb.o
-common-obj-$(CONFIG_ZAURUS) +=3D tc6393xb.o
+obj-$(CONFIG_ZAURUS) +=3D tc6393xb.o
 
 obj-$(CONFIG_MILKYMIST_TMU2) +=3D milkymist-tmu2.o
 milkymist-tmu2.o-cflags :=3D $(X11_CFLAGS) $(OPENGL_CFLAGS)
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index 8b39f9c..7e17776 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -1,17 +1,17 @@
-common-obj-$(CONFIG_PUV3) +=3D puv3_dma.o
-common-obj-$(CONFIG_RC4030) +=3D rc4030.o
-common-obj-$(CONFIG_PL080) +=3D pl080.o
-common-obj-$(CONFIG_PL330) +=3D pl330.o
+obj-$(CONFIG_PUV3) +=3D puv3_dma.o
+obj-$(CONFIG_RC4030) +=3D rc4030.o
+obj-$(CONFIG_PL080) +=3D pl080.o
+obj-$(CONFIG_PL330) +=3D pl330.o
 common-obj-$(CONFIG_I82374) +=3D i82374.o
-common-obj-$(CONFIG_I8257) +=3D i8257.o
-common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axidma.o
+obj-$(CONFIG_I8257) +=3D i8257.o
+obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axidma.o
 common-obj-$(CONFIG_ZYNQ_DEVCFG) +=3D xlnx-zynq-devcfg.o
-common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_dma.o
-common-obj-$(CONFIG_STP2000) +=3D sparc32_dma.o
+obj-$(CONFIG_ETRAXFS) +=3D etraxfs_dma.o
+obj-$(CONFIG_STP2000) +=3D sparc32_dma.o
 obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx_dpdma.o
 obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx_dpdma.o
 common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) +=3D xlnx-zdma.o
 
 obj-$(CONFIG_OMAP) +=3D omap_dma.o soc_dma.o
 obj-$(CONFIG_PXA2XX) +=3D pxa2xx_dma.o
-common-obj-$(CONFIG_RASPI) +=3D bcm2835_dma.o
+obj-$(CONFIG_RASPI) +=3D bcm2835_dma.o
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
index e5da0cb..9d297fd 100644
--- a/hw/gpio/Makefile.objs
+++ b/hw/gpio/Makefile.objs
@@ -1,7 +1,7 @@
 common-obj-$(CONFIG_MAX7310) +=3D max7310.o
-common-obj-$(CONFIG_PL061) +=3D pl061.o
-common-obj-$(CONFIG_PUV3) +=3D puv3_gpio.o
-common-obj-$(CONFIG_ZAURUS) +=3D zaurus.o
+obj-$(CONFIG_PL061) +=3D pl061.o
+obj-$(CONFIG_PUV3) +=3D puv3_gpio.o
+obj-$(CONFIG_ZAURUS) +=3D zaurus.o
 common-obj-$(CONFIG_E500) +=3D mpc8xxx.o
 common-obj-$(CONFIG_GPIO_KEY) +=3D gpio_key.o
 
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index d7073a4..9c8839c 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -1,13 +1,13 @@
 common-obj-$(CONFIG_I2C) +=3D core.o smbus_slave.o smbus_mas= ter.o
 common-obj-$(CONFIG_SMBUS_EEPROM) +=3D smbus_eeprom.o
-common-obj-$(CONFIG_VERSATILE_I2C) +=3D versatile_i2c.o
+obj-$(CONFIG_VERSATILE_I2C) +=3D versatile_i2c.o
 common-obj-$(CONFIG_ACPI_X86_ICH) +=3D smbus_ich9.o
 common-obj-$(CONFIG_ACPI_SMBUS) +=3D pm_smbus.o
 common-obj-$(CONFIG_BITBANG_I2C) +=3D bitbang_i2c.o
-common-obj-$(CONFIG_EXYNOS4) +=3D exynos4210_i2c.o
-common-obj-$(CONFIG_IMX_I2C) +=3D imx_i2c.o
+obj-$(CONFIG_EXYNOS4) +=3D exynos4210_i2c.o
+obj-$(CONFIG_IMX_I2C) +=3D imx_i2c.o
 common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_i2c.o
 common-obj-$(CONFIG_NRF51_SOC) +=3D microbit_i2c.o
-common-obj-$(CONFIG_MPC_I2C) +=3D mpc_i2c.o
+obj-$(CONFIG_MPC_I2C) +=3D mpc_i2c.o
 obj-$(CONFIG_OMAP) +=3D omap_i2c.o
 obj-$(CONFIG_PPC4XX) +=3D ppc4xx_i2c.o
diff --git a/hw/input/Makefile.objs b/hw/input/Makefile.objs
index a1bc502..e096cc5 100644
--- a/hw/input/Makefile.objs
+++ b/hw/input/Makefile.objs
@@ -1,8 +1,8 @@
 common-obj-$(CONFIG_ADB) +=3D adb.o adb-mouse.o adb-kbd.o
 common-obj-y +=3D hid.o
 common-obj-$(CONFIG_LM832X) +=3D lm832x.o
-common-obj-$(CONFIG_PCKBD) +=3D pckbd.o
-common-obj-$(CONFIG_PL050) +=3D pl050.o
+obj-$(CONFIG_PCKBD) +=3D pckbd.o
+obj-$(CONFIG_PL050) +=3D pl050.o
 common-obj-$(CONFIG_PS2) +=3D ps2.o
 common-obj-$(CONFIG_STELLARIS_INPUT) +=3D stellaris_input.o<= /div>
 common-obj-$(CONFIG_TSC2005) +=3D tsc2005.o
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 03019b9..6d7ba84 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -1,24 +1,25 @@
 common-obj-$(CONFIG_HEATHROW_PIC) +=3D heathrow_pic.o
 common-obj-$(CONFIG_I8259) +=3D i8259_common.o i8259.o
-common-obj-$(CONFIG_PL190) +=3D pl190.o
-common-obj-$(CONFIG_PUV3) +=3D puv3_intc.o
-common-obj-$(CONFIG_XILINX) +=3D xilinx_intc.o
+obj-$(CONFIG_PL190) +=3D pl190.o
+obj-$(CONFIG_PUV3) +=3D puv3_intc.o
+obj-$(CONFIG_XILINX) +=3D xilinx_intc.o
 common-obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-pmu-iomod-intc.o<= /div>
 common-obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-zynqmp-ipi.o
-common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_pic.o
-common-obj-$(CONFIG_IMX) +=3D imx_avic.o imx_gpcv2.o
+obj-$(CONFIG_ETRAXFS) +=3D etraxfs_pic.o
+obj-$(CONFIG_IMX) +=3D imx_avic.o
+obj-$(CONFIG_IMX) +=3D imx_gpcv2.o
 common-obj-$(CONFIG_LM32) +=3D lm32_pic.o
 common-obj-$(CONFIG_REALVIEW) +=3D realview_gic.o
-common-obj-$(CONFIG_SLAVIO) +=3D slavio_intctl.o
+obj-$(CONFIG_SLAVIO) +=3D slavio_intctl.o
 common-obj-$(CONFIG_IOAPIC) +=3D ioapic_common.o
 common-obj-$(CONFIG_ARM_GIC) +=3D arm_gic_common.o
-common-obj-$(CONFIG_ARM_GIC) +=3D arm_gic.o
+obj-$(CONFIG_ARM_GIC) +=3D arm_gic.o
 common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv2m.o
 common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_common.o
-common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3.o
+obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3.o
 common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_dist.o
 common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_redist.o
-common-obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_its_common.o
+obj-$(CONFIG_ARM_GIC) +=3D arm_gicv3_its_common.o
 common-obj-$(CONFIG_OPENPIC) +=3D openpic.o
 common-obj-y +=3D intc.o
 
diff --git a/hw/ipack/Makefile.objs b/hw/ipack/Makefile.objs
index 8b9bdcb..a7c5485 100644
--- a/hw/ipack/Makefile.objs
+++ b/hw/ipack/Makefile.objs
@@ -1,2 +1,2 @@
 common-obj-$(CONFIG_IPACK) +=3D ipack.o
-common-obj-$(CONFIG_IPACK) +=3D tpci200.o
+obj-$(CONFIG_IPACK) +=3D tpci200.o
diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
index 9e106df..898b504 100644
--- a/hw/isa/Makefile.objs
+++ b/hw/isa/Makefile.objs
@@ -4,7 +4,7 @@ common-obj-$(CONFIG_APM) +=3D apm.o
 common-obj-$(CONFIG_I82378) +=3D i82378.o
 common-obj-$(CONFIG_PC87312) +=3D pc87312.o
 common-obj-$(CONFIG_PIIX4) +=3D piix4.o
-common-obj-$(CONFIG_VT82C686) +=3D vt82c686.o
+obj-$(CONFIG_VT82C686) +=3D vt82c686.o
 common-obj-$(CONFIG_SMC37C669) +=3D smc37c669-superio.o
 
 obj-$(CONFIG_LPC_ICH9) +=3D lpc_ich9.o
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index e9aab51..6ee5a8a 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-$(CONFIG_APPLESMC) +=3D applesmc.o
+obj-$(CONFIG_APPLESMC) +=3D applesmc.o
 common-obj-$(CONFIG_MAX111X) +=3D max111x.o
 common-obj-$(CONFIG_TMP105) +=3D tmp105.o
 common-obj-$(CONFIG_TMP421) +=3D tmp421.o
@@ -6,23 +6,23 @@ common-obj-$(CONFIG_ISA_DEBUG) +=3D debugexi= t.o
 common-obj-$(CONFIG_SGA) +=3D sga.o
 common-obj-$(CONFIG_ISA_TESTDEV) +=3D pc-testdev.o
 common-obj-$(CONFIG_PCI_TESTDEV) +=3D pci-testdev.o
-common-obj-$(CONFIG_EDU) +=3D edu.o
+obj-$(CONFIG_EDU) +=3D edu.o
 common-obj-$(CONFIG_PCA9552) +=3D pca9552.o
 
-common-obj-y +=3D unimp.o
+obj-y +=3D unimp.o
 common-obj-$(CONFIG_FW_CFG_DMA) +=3D vmcoreinfo.o
 
 # ARM devices
-common-obj-$(CONFIG_PL310) +=3D arm_l2x0.o
-common-obj-$(CONFIG_INTEGRATOR_DEBUG) +=3D arm_integrator_debug.o=
-common-obj-$(CONFIG_A9SCU) +=3D a9scu.o
-common-obj-$(CONFIG_ARM11SCU) +=3D arm11scu.o
+obj-$(CONFIG_PL310) +=3D arm_l2x0.o
+obj-$(CONFIG_INTEGRATOR_DEBUG) +=3D arm_integrator_debug.o
+obj-$(CONFIG_A9SCU) +=3D a9scu.o
+obj-$(CONFIG_ARM11SCU) +=3D arm11scu.o
 
 # Mac devices
-common-obj-$(CONFIG_MOS6522) +=3D mos6522.o
+obj-$(CONFIG_MOS6522) +=3D mos6522.o
 
 # PKUnity SoC devices
-common-obj-$(CONFIG_PUV3) +=3D puv3_pm.o
+obj-$(CONFIG_PUV3) +=3D puv3_pm.o
 
 common-obj-$(CONFIG_MACIO) +=3D macio/
 
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
index 9904273..1ff7b59 100644
--- a/hw/net/Makefile.objs
+++ b/hw/net/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-$(CONFIG_DP8393X) +=3D dp8393x.o
+obj-$(CONFIG_DP8393X) +=3D dp8393x.o
 common-obj-$(CONFIG_XEN) +=3D xen_nic.o
 common-obj-$(CONFIG_NE2000_COMMON) +=3D ne2000.o
 
@@ -14,19 +14,19 @@ common-obj-$(CONFIG_RTL8139_PCI) +=3D rtl8= 139.o
 common-obj-$(CONFIG_VMXNET3_PCI) +=3D net_tx_pkt.o net_rx_pk= t.o
 common-obj-$(CONFIG_VMXNET3_PCI) +=3D vmxnet3.o
 
-common-obj-$(CONFIG_SMC91C111) +=3D smc91c111.o
-common-obj-$(CONFIG_LAN9118) +=3D lan9118.o
+obj-$(CONFIG_SMC91C111) +=3D smc91c111.o
+obj-$(CONFIG_LAN9118) +=3D lan9118.o
 common-obj-$(CONFIG_NE2000_ISA) +=3D ne2000-isa.o
 common-obj-$(CONFIG_OPENCORES_ETH) +=3D opencores_eth.o
 common-obj-$(CONFIG_XGMAC) +=3D xgmac.o
 common-obj-$(CONFIG_MIPSNET) +=3D mipsnet.o
 common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axienet.o
-common-obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o
-common-obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o
+obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o
+obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o
 
 common-obj-$(CONFIG_CADENCE) +=3D cadence_gem.o
-common-obj-$(CONFIG_STELLARIS_ENET) +=3D stellaris_enet.o
-common-obj-$(CONFIG_LANCE) +=3D lance.o
+obj-$(CONFIG_STELLARIS_ENET) +=3D stellaris_enet.o
+obj-$(CONFIG_LANCE) +=3D lance.o
 common-obj-$(CONFIG_SUNHME) +=3D sunhme.o
 common-obj-$(CONFIG_FTGMAC100) +=3D ftgmac100.o
 common-obj-$(CONFIG_SUNGEM) +=3D sungem.o
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index a9cd3e0..0970e8e 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -9,12 +9,12 @@ common-obj-$(CONFIG_UNIN_PCI) +=3D uninorth.= o
 common-obj-$(CONFIG_PPCE500_PCI) +=3D ppce500.o
 
 # ARM devices
-common-obj-$(CONFIG_VERSATILE_PCI) +=3D versatile.o
+obj-$(CONFIG_VERSATILE_PCI) +=3D versatile.o
 
 common-obj-$(CONFIG_PCI_SABRE) +=3D sabre.o
-common-obj-$(CONFIG_FULONG) +=3D bonito.o
+obj-$(CONFIG_FULONG) +=3D bonito.o
 common-obj-$(CONFIG_PCI_PIIX) +=3D piix.o
-common-obj-$(CONFIG_PCI_EXPRESS_Q35) +=3D q35.o
+obj-$(CONFIG_PCI_EXPRESS_Q35) +=3D q35.o
 common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) +=3D gpex.o<= /div>
 common-obj-$(CONFIG_PCI_EXPRESS_XILINX) +=3D xilinx-pcie.o
 
diff --git a/hw/scsi/Makefile.objs b/hw/scsi/Makefile.objs
index 54b36ed..418af9a 100644
--- a/hw/scsi/Makefile.objs
+++ b/hw/scsi/Makefile.objs
@@ -4,7 +4,7 @@ common-obj-$(CONFIG_LSI_SCSI_PCI) +=3D lsi53c8= 95a.o
 common-obj-$(CONFIG_MPTSAS_SCSI_PCI) +=3D mptsas.o mptconfig= .o mptendian.o
 common-obj-$(CONFIG_MEGASAS_SCSI_PCI) +=3D megasas.o
 common-obj-$(CONFIG_VMW_PVSCSI_SCSI_PCI) +=3D vmw_pvscsi.o
-common-obj-$(CONFIG_ESP) +=3D esp.o
+obj-$(CONFIG_ESP) +=3D esp.o
 common-obj-$(CONFIG_ESP_PCI) +=3D esp-pci.o
 obj-$(CONFIG_SPAPR_VSCSI) +=3D spapr_vscsi.o
 
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
index 0665727..a8cd6bf 100644
--- a/hw/sd/Makefile.objs
+++ b/hw/sd/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-$(CONFIG_PL181) +=3D pl181.o
+obj-$(CONFIG_PL181) +=3D pl181.o
 common-obj-$(CONFIG_SSI_SD) +=3D ssi-sd.o
 common-obj-$(CONFIG_SD) +=3D sd.o core.o sdmmc-internal.o
 common-obj-$(CONFIG_SDHCI) +=3D sdhci.o
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index f5bcc65..b084802 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -1,10 +1,10 @@
-common-obj-$(CONFIG_PL022) +=3D pl022.o
+obj-$(CONFIG_PL022) +=3D pl022.o
 common-obj-$(CONFIG_SSI) +=3D ssi.o
-common-obj-$(CONFIG_XILINX_SPI) +=3D xilinx_spi.o
-common-obj-$(CONFIG_XILINX_SPIPS) +=3D xilinx_spips.o
+obj-$(CONFIG_XILINX_SPI) +=3D xilinx_spi.o
+obj-$(CONFIG_XILINX_SPIPS) +=3D xilinx_spips.o
 common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_smc.o
-common-obj-$(CONFIG_STM32F2XX_SPI) +=3D stm32f2xx_spi.o
-common-obj-$(CONFIG_MSF2) +=3D mss-spi.o
+obj-$(CONFIG_STM32F2XX_SPI) +=3D stm32f2xx_spi.o
+obj-$(CONFIG_MSF2) +=3D mss-spi.o
 
 obj-$(CONFIG_OMAP) +=3D omap_spi.o
 obj-$(CONFIG_IMX) +=3D imx_spi.o
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 123d92c..0a8f651 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -1,27 +1,27 @@
-common-obj-$(CONFIG_ARM_TIMER) +=3D arm_timer.o
-common-obj-$(CONFIG_ARM_MPTIMER) +=3D arm_mptimer.o
-common-obj-$(CONFIG_ARM_V7M) +=3D armv7m_systick.o
-common-obj-$(CONFIG_A9_GTIMER) +=3D a9gtimer.o
-common-obj-$(CONFIG_CADENCE) +=3D cadence_ttc.o
+obj-$(CONFIG_ARM_TIMER) +=3D arm_timer.o
+obj-$(CONFIG_ARM_MPTIMER) +=3D arm_mptimer.o
+obj-$(CONFIG_ARM_V7M) +=3D armv7m_systick.o
+obj-$(CONFIG_A9_GTIMER) +=3D a9gtimer.o
+obj-$(CONFIG_CADENCE) +=3D cadence_ttc.o
 common-obj-$(CONFIG_DS1338) +=3D ds1338.o
-common-obj-$(CONFIG_HPET) +=3D hpet.o
+obj-$(CONFIG_HPET) +=3D hpet.o
 common-obj-$(CONFIG_I8254) +=3D i8254_common.o i8254.o
 common-obj-$(CONFIG_M41T80) +=3D m41t80.o
 common-obj-$(CONFIG_M48T59) +=3D m48t59.o
 ifeq ($(CONFIG_ISA_BUS),y)
 common-obj-$(CONFIG_M48T59) +=3D m48t59-isa.o
 endif
-common-obj-$(CONFIG_PL031) +=3D pl031.o
-common-obj-$(CONFIG_PUV3) +=3D puv3_ost.o
+obj-$(CONFIG_PL031) +=3D pl031.o
+obj-$(CONFIG_PUV3) +=3D puv3_ost.o
 common-obj-$(CONFIG_TWL92230) +=3D twl92230.o
-common-obj-$(CONFIG_XILINX) +=3D xilinx_timer.o
-common-obj-$(CONFIG_SLAVIO) +=3D slavio_timer.o
+obj-$(CONFIG_XILINX) +=3D xilinx_timer.o
+obj-$(CONFIG_SLAVIO) +=3D slavio_timer.o
 common-obj-$(CONFIG_ETRAXFS) +=3D etraxfs_timer.o
-common-obj-$(CONFIG_GRLIB) +=3D grlib_gptimer.o
-common-obj-$(CONFIG_IMX) +=3D imx_epit.o
-common-obj-$(CONFIG_IMX) +=3D imx_gpt.o
-common-obj-$(CONFIG_LM32) +=3D lm32_timer.o
-common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-sysctl.o
+obj-$(CONFIG_GRLIB) +=3D grlib_gptimer.o
+obj-$(CONFIG_IMX) +=3D imx_epit.o
+obj-$(CONFIG_IMX) +=3D imx_gpt.o
+obj-$(CONFIG_LM32) +=3D lm32_timer.o
+obj-$(CONFIG_MILKYMIST) +=3D milkymist-sysctl.o
 common-obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-zynqmp-rtc.o
 common-obj-$(CONFIG_NRF51_SOC) +=3D nrf51_timer.o
 
@@ -40,10 +40,11 @@ obj-$(CONFIG_MC146818RTC) +=3D mc146818rtc= .o
 
 obj-$(CONFIG_ALLWINNER_A10_PIT) +=3D allwinner-a10-pit.o
 
-common-obj-$(CONFIG_STM32F2XX_TIMER) +=3D stm32f2xx_timer.o
-common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o aspeed_rtc.o<= /div>
+obj-$(CONFIG_STM32F2XX_TIMER) +=3D stm32f2xx_timer.o
+common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_timer.o
+obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_rtc.o
 
-common-obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o
+obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o
 common-obj-$(CONFIG_CMSDK_APB_TIMER) +=3D cmsdk-apb-timer.o<= /div>
 common-obj-$(CONFIG_CMSDK_APB_DUALTIMER) +=3D cmsdk-apb-dual= timer.o
-common-obj-$(CONFIG_MSF2) +=3D mss-timer.o
+obj-$(CONFIG_MSF2) +=3D mss-timer.o
diff --git a/hw/virtio/Makefile.objs b/hw/virtio/Makefile.objs
index 964ce78..573b1a9 100644
--- a/hw/virtio/Makefile.objs
+++ b/hw/virtio/Makefile.objs
@@ -8,7 +8,7 @@ obj-$(CONFIG_VHOST_USER) +=3D vhost-user.o
 
 common-obj-$(CONFIG_VIRTIO_RNG) +=3D virtio-rng.o
 common-obj-$(CONFIG_VIRTIO_PCI) +=3D virtio-pci.o
-common-obj-$(CONFIG_VIRTIO_MMIO) +=3D virtio-mmio.o
+obj-$(CONFIG_VIRTIO_MMIO) +=3D virtio-mmio.o
 obj-$(CONFIG_VIRTIO_BALLOON) +=3D virtio-balloon.o
 obj-$(CONFIG_VIRTIO_CRYPTO) +=3D virtio-crypto.o
 obj-$(call land,$(CONFIG_VIRTIO_CRYPTO),$(CONFIG_VIRTIO_PCI)) &#= 43;=3D virtio-crypto-pci.o
-- 
1.8.3.1

​

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Wed, 7 Aug 2019 09:31:28 +0100 X-Inumbo-ID: c156d4c2-b8ed-11e9-8980-bc764e045a96 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 16/26] exec: Map device_endian onto MemOp Thread-Index: AQHVTPqBizwOZ0pOOka1lx5iTeYAMw== Date: Wed, 7 Aug 2019 08:31:28 +0000 Message-ID: <1565166687895.25037@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 07 Aug 2019 08:32:04 +0000 Subject: [Xen-devel] [Qemu-devel] [PATCH v6 16/26] exec: Map device_endian onto MemOp X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Content-Type: multipart/mixed; boundary="===============0373994539903350518==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============0373994539903350518== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516668789525037btcom_" --_000_156516668789525037btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation to replace device_endian with MemOp. Mapping device_endian onto MemOp limits behaviour changes to this relatively smaller patch. The next patch will replace all device_endian usages with the equivalent MemOp. That patch will be large but have no behaviour changes. A subsequent patch will then delete unused device_endian. Signed-off-by: Tony Nguyen --- hw/char/serial.c | 18 ++++++------------ include/exec/cpu-common.h | 10 +++++++--- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/hw/char/serial.c b/hw/char/serial.c index 7c42a2a..7345f69 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -1012,22 +1012,15 @@ static void serial_mm_write(void *opaque, hwaddr ad= dr, serial_ioport_write(s, addr >> s->it_shift, value, 1); } -static const MemoryRegionOps serial_mm_ops[3] =3D { - [DEVICE_NATIVE_ENDIAN] =3D { - .read =3D serial_mm_read, - .write =3D serial_mm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid.max_access_size =3D 8, - .impl.max_access_size =3D 8, - }, - [DEVICE_LITTLE_ENDIAN] =3D { +static const MemoryRegionOps serial_mm_ops[2] =3D { + [0] =3D { .read =3D serial_mm_read, .write =3D serial_mm_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid.max_access_size =3D 8, .impl.max_access_size =3D 8, }, - [DEVICE_BIG_ENDIAN] =3D { + [1] =3D { .read =3D serial_mm_read, .write =3D serial_mm_write, .endianness =3D DEVICE_BIG_ENDIAN, @@ -1053,8 +1046,9 @@ SerialState *serial_mm_init(MemoryRegion *address_spa= ce, serial_realize_core(s, &error_fatal); vmstate_register(NULL, base, &vmstate_serial, s); - memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s, - "serial", 8 << it_shift); + memory_region_init_io(&s->io, NULL, + &serial_mm_ops[end =3D=3D DEVICE_LITTLE_ENDIAN ?= 0 : 1], + s, "serial", 8 << it_shift); memory_region_add_subregion(address_space, base, &s->io); return s; } diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index f7dbe75..c388453 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -16,10 +16,14 @@ void tcg_flush_softmmu_tlb(CPUState *cs); #if !defined(CONFIG_USER_ONLY) +#include "exec/memop.h" + enum device_endian { - DEVICE_NATIVE_ENDIAN, - DEVICE_BIG_ENDIAN, - DEVICE_LITTLE_ENDIAN, +#ifdef NEED_CPU_H + DEVICE_NATIVE_ENDIAN =3D MO_TE, +#endif + DEVICE_BIG_ENDIAN =3D MO_BE, + DEVICE_LITTLE_ENDIAN =3D MO_LE, }; #if defined(HOST_WORDS_BIGENDIAN) -- 1.8.3.1 ? --_000_156516668789525037btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation to replace device_endian = with MemOp.

Mapping device_endian onto MemOp limits behaviour changes to this
relatively smaller patch.

The next patch will replace all device_endian usages with the
equivalent MemOp. That patch will be large but have no behaviour
changes.

A subsequent patch will then delete unused device_endian.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 hw/char/serial.c          | 18 += 3;++++------------
 include/exec/cpu-common.h | 10 ++++++= 3;---
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/hw/char/serial.c b/hw/char/serial.c
index 7c42a2a..7345f69 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -1012,22 +1012,15 @@ static void serial_mm_write(void *opaque, = hwaddr addr,
     serial_ioport_write(s, addr >> s->it_shif= t, value, 1);
 }
 
-static const MemoryRegionOps serial_mm_ops[3] =3D {
-    [DEVICE_NATIVE_ENDIAN] =3D {
-        .read =3D serial_mm_read,
-        .write =3D serial_mm_write,
-        .endianness =3D DEVICE_NATIVE_ENDIAN,
-        .valid.max_access_size =3D 8,
-        .impl.max_access_size =3D 8,
-    },
-    [DEVICE_LITTLE_ENDIAN] =3D {
+static const MemoryRegionOps serial_mm_ops[2] =3D {
+    [0] =3D {
         .read =3D serial_mm_read,
         .write =3D serial_mm_write,
         .endianness =3D DEVICE_LITTLE_ENDIAN= ,
         .valid.max_access_size =3D 8,
         .impl.max_access_size =3D 8,
     },
-    [DEVICE_BIG_ENDIAN] =3D {
+    [1] =3D {
         .read =3D serial_mm_read,
         .write =3D serial_mm_write,
         .endianness =3D DEVICE_BIG_ENDIAN,
@@ -1053,8 +1046,9 @@ SerialState *serial_mm_init(MemoryRegion *ad= dress_space,
     serial_realize_core(s, &error_fatal);
     vmstate_register(NULL, base, &vmstate_serial, = s);
 
-    memory_region_init_io(&s->io, NULL, &serial_= mm_ops[end], s,
-                    = ;      "serial", 8 << it_shift);
+    memory_region_init_io(&s->io, NULL,
+                   &= nbsp;      &serial_mm_ops[end =3D=3D DEVICE_LITTLE_ENDIA= N ? 0 : 1],
+                   &= nbsp;      s, "serial", 8 << it_shift);
     memory_region_add_subregion(address_space, base, &= amp;s->io);
     return s;
 }
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index f7dbe75..c388453 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -16,10 +16,14 @@ void tcg_flush_softmmu_tlb(CPUState *cs);
 
 #if !defined(CONFIG_USER_ONLY)
 
+#include "exec/memop.h"
+
 enum device_endian {
-    DEVICE_NATIVE_ENDIAN,
-    DEVICE_BIG_ENDIAN,
-    DEVICE_LITTLE_ENDIAN,
+#ifdef NEED_CPU_H
+    DEVICE_NATIVE_ENDIAN =3D MO_TE,
+#endif
+    DEVICE_BIG_ENDIAN =3D MO_BE,
+    DEVICE_LITTLE_ENDIAN =3D MO_LE,
 };
 
 #if defined(HOST_WORDS_BIGENDIAN)
-- 
1.8.3.1

​

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X-Received-From: 62.239.224.237 X-Mailman-Approved-At: Wed, 07 Aug 2019 09:05:14 -0400 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.23 Subject: [Qemu-devel] [PATCH v6 17/26] exec: Replace device_endian with MemOp X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Simplify endianness comparisons with consistent use of the more expressive MemOp. Suggested-by: Richard Henderson Signed-off-by: Tony Nguyen irq[1= ], - 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); + 115200, serial_hd(0), MO_TE); } static void aw_a10_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index b9efad6..9bce022 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -86,7 +86,7 @@ static MemTxResult bitband_write(void *opaque, hwaddr off= set, uint64_t value, static const MemoryRegionOps bitband_ops =3D { .read_with_attrs =3D bitband_read, .write_with_attrs =3D bitband_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl.min_access_size =3D 1, .impl.max_access_size =3D 4, .valid.min_access_size =3D 1, diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 843b708..c0ccb35 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -105,7 +105,7 @@ static void max_ram_write(void *opaque, hwaddr offset, = uint64_t value, static const MemoryRegionOps max_ram_ops =3D { .read =3D max_ram_read, .write =3D max_ram_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; #define FIRMWARE_ADDR 0x0 diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index c6fb370..9437b9d 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -331,7 +331,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error = **errp) if (serial_hd(0)) { qemu_irq uart5 =3D aspeed_soc_get_irq(s, ASPEED_UART5); serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5]= , 2, - uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); + uart5, 38400, serial_hd(0), MO_LE); } /* I2C */ diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index becd864..c1ce423 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -119,7 +119,7 @@ static void exynos4210_chipid_and_omr_write(void *opaqu= e, hwaddr offset, static const MemoryRegionOps exynos4210_chipid_and_omr_ops =3D { .read =3D exynos4210_chipid_and_omr_read, .write =3D exynos4210_chipid_and_omr_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .max_access_size =3D 1, } diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index def0f1c..0d1b699 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -148,7 +148,7 @@ static uint64_t hb_regs_read(void *opaque, hwaddr offse= t, static const MemoryRegionOps hb_mem_ops =3D { .read =3D hb_regs_read, .write =3D hb_regs_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; #define TYPE_HIGHBANK_REGISTERS "highbank-regs" diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 200c010..260d928 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -259,7 +259,7 @@ static void integratorcm_write(void *opaque, hwaddr off= set, static const MemoryRegionOps integratorcm_ops =3D { .read =3D integratorcm_read, .write =3D integratorcm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void integratorcm_init(Object *obj) @@ -435,7 +435,7 @@ static void icp_pic_write(void *opaque, hwaddr offset, static const MemoryRegionOps icp_pic_ops =3D { .read =3D icp_pic_read, .write =3D icp_pic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void icp_pic_init(Object *obj) @@ -527,7 +527,7 @@ static void icp_control_write(void *opaque, hwaddr offs= et, static const MemoryRegionOps icp_control_ops =3D { .read =3D icp_control_read, .write =3D icp_control_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void icp_control_mmc_wprot(void *opaque, int line, int level) diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 59d2102..836c1a7 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -122,7 +122,7 @@ static void kzm_init(MachineState *machine) if (serial_hd(2)) { /* touchscreen */ serial_mm_init(get_system_memory(), KZM_FPGA_ADDR+0x10, 0, qdev_get_gpio_in(DEVICE(&s->soc.avic), 52), - 14745600, serial_hd(2), DEVICE_NATIVE_ENDIAN); + 14745600, serial_hd(2), MO_TE); } kzm_binfo.ram_size =3D machine->ram_size; diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 1ccb644..30ea87f 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -139,7 +139,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) if (serial_hd(i)) { serial_mm_init(get_system_memory(), uart_addr[i], 2, qdev_get_gpio_in(armv7m, uart_irq[i]), - 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); + 115200, serial_hd(i), MO_TE); } } diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 95d56f3..e20f0a9 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -366,7 +366,7 @@ static void mv88w8618_eth_write(void *opaque, hwaddr of= fset, static const MemoryRegionOps mv88w8618_eth_ops =3D { .read =3D mv88w8618_eth_read, .write =3D mv88w8618_eth_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void eth_cleanup(NetClientState *nc) @@ -612,7 +612,7 @@ static void musicpal_lcd_write(void *opaque, hwaddr off= set, static const MemoryRegionOps musicpal_lcd_ops =3D { .read =3D musicpal_lcd_read, .write =3D musicpal_lcd_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const GraphicHwOps musicpal_gfx_ops =3D { @@ -753,7 +753,7 @@ static void mv88w8618_pic_reset(DeviceState *d) static const MemoryRegionOps mv88w8618_pic_ops =3D { .read =3D mv88w8618_pic_read, .write =3D mv88w8618_pic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void mv88w8618_pic_init(Object *obj) @@ -917,7 +917,7 @@ static void mv88w8618_pit_reset(DeviceState *d) static const MemoryRegionOps mv88w8618_pit_ops =3D { .read =3D mv88w8618_pit_read, .write =3D mv88w8618_pit_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void mv88w8618_pit_init(Object *obj) @@ -1021,7 +1021,7 @@ static void mv88w8618_flashcfg_write(void *opaque, hw= addr offset, static const MemoryRegionOps mv88w8618_flashcfg_ops =3D { .read =3D mv88w8618_flashcfg_read, .write =3D mv88w8618_flashcfg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void mv88w8618_flashcfg_init(Object *obj) @@ -1094,7 +1094,7 @@ static void musicpal_misc_write(void *opaque, hwaddr = offset, static const MemoryRegionOps musicpal_misc_ops =3D { .read =3D musicpal_misc_read, .write =3D musicpal_misc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void musicpal_misc_init(Object *obj) @@ -1142,7 +1142,7 @@ static void mv88w8618_wlan_write(void *opaque, hwaddr= offset, static const MemoryRegionOps mv88w8618_wlan_ops =3D { .read =3D mv88w8618_wlan_read, .write =3Dmv88w8618_wlan_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp) @@ -1339,7 +1339,7 @@ static void musicpal_gpio_write(void *opaque, hwaddr = offset, static const MemoryRegionOps musicpal_gpio_ops =3D { .read =3D musicpal_gpio_read, .write =3D musicpal_gpio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void musicpal_gpio_reset(DeviceState *d) @@ -1609,11 +1609,11 @@ static void musicpal_init(MachineState *machine) if (serial_hd(0)) { serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_I= RQ], - 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); + 1825000, serial_hd(0), MO_TE); } if (serial_hd(1)) { serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_I= RQ], - 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); + 1825000, serial_hd(1), MO_TE); } /* Register flash */ diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 28fbe27..174a000 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -252,7 +252,7 @@ static void omap_mpu_timer_write(void *opaque, hwaddr a= ddr, static const MemoryRegionOps omap_mpu_timer_ops =3D { .read =3D omap_mpu_timer_read, .write =3D omap_mpu_timer_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) @@ -375,7 +375,7 @@ static void omap_wd_timer_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps omap_wd_timer_ops =3D { .read =3D omap_wd_timer_read, .write =3D omap_wd_timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) @@ -487,7 +487,7 @@ static void omap_os_timer_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps omap_os_timer_ops =3D { .read =3D omap_os_timer_read, .write =3D omap_os_timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_os_timer_reset(struct omap_32khz_timer_s *s) @@ -714,7 +714,7 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr add= r, static const MemoryRegionOps omap_ulpd_pm_ops =3D { .read =3D omap_ulpd_pm_read, .write =3D omap_ulpd_pm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) @@ -948,7 +948,7 @@ static void omap_pin_cfg_write(void *opaque, hwaddr add= r, static const MemoryRegionOps omap_pin_cfg_ops =3D { .read =3D omap_pin_cfg_read, .write =3D omap_pin_cfg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) @@ -1039,7 +1039,7 @@ static void omap_id_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_id_ops =3D { .read =3D omap_id_read, .write =3D omap_id_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_id_init(MemoryRegion *memory, struct omap_mpu_state_s *mp= u) @@ -1128,7 +1128,7 @@ static void omap_mpui_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_mpui_ops =3D { .read =3D omap_mpui_read, .write =3D omap_mpui_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_mpui_reset(struct omap_mpu_state_s *s) @@ -1231,7 +1231,7 @@ static void omap_tipb_bridge_write(void *opaque, hwad= dr addr, static const MemoryRegionOps omap_tipb_bridge_ops =3D { .read =3D omap_tipb_bridge_read, .write =3D omap_tipb_bridge_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) @@ -1336,7 +1336,7 @@ static void omap_tcmi_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_tcmi_ops =3D { .read =3D omap_tcmi_read, .write =3D omap_tcmi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) @@ -1431,7 +1431,7 @@ static void omap_dpll_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_dpll_ops =3D { .read =3D omap_dpll_read, .write =3D omap_dpll_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_dpll_reset(struct dpll_ctl_s *s) @@ -1743,7 +1743,7 @@ static void omap_clkm_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_clkm_ops =3D { .read =3D omap_clkm_read, .write =3D omap_clkm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr, @@ -1832,7 +1832,7 @@ static void omap_clkdsp_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps omap_clkdsp_ops =3D { .read =3D omap_clkdsp_read, .write =3D omap_clkdsp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_clkm_reset(struct omap_mpu_state_s *s) @@ -2077,7 +2077,7 @@ static void omap_mpuio_write(void *opaque, hwaddr add= r, static const MemoryRegionOps omap_mpuio_ops =3D { .read =3D omap_mpuio_read, .write =3D omap_mpuio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_mpuio_reset(struct omap_mpuio_s *s) @@ -2283,7 +2283,7 @@ static void omap_uwire_write(void *opaque, hwaddr add= r, static const MemoryRegionOps omap_uwire_ops =3D { .read =3D omap_uwire_read, .write =3D omap_uwire_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_uwire_reset(struct omap_uwire_s *s) @@ -2394,7 +2394,7 @@ static void omap_pwl_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_pwl_ops =3D { .read =3D omap_pwl_read, .write =3D omap_pwl_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_pwl_reset(struct omap_pwl_s *s) @@ -2512,7 +2512,7 @@ static void omap_pwt_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_pwt_ops =3D { .read =3Domap_pwt_read, .write =3D omap_pwt_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_pwt_reset(struct omap_pwt_s *s) @@ -2849,7 +2849,7 @@ static void omap_rtc_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_rtc_ops =3D { .read =3D omap_rtc_read, .write =3D omap_rtc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_rtc_tick(void *opaque) @@ -3447,7 +3447,7 @@ static void omap_mcbsp_write(void *opaque, hwaddr add= r, static const MemoryRegionOps omap_mcbsp_ops =3D { .read =3D omap_mcbsp_read, .write =3D omap_mcbsp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_mcbsp_reset(struct omap_mcbsp_s *s) @@ -3639,7 +3639,7 @@ static void omap_lpg_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_lpg_ops =3D { .read =3D omap_lpg_read, .write =3D omap_lpg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_lpg_clk_update(void *opaque, int line, int on) @@ -3692,7 +3692,7 @@ static void omap_mpui_io_write(void *opaque, hwaddr a= ddr, static const MemoryRegionOps omap_mpui_io_ops =3D { .read =3D omap_mpui_io_read, .write =3D omap_mpui_io_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_setup_mpui_io(MemoryRegion *system_memory, diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 87ced7f..b1e1d3e 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -593,7 +593,7 @@ static void omap_eac_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_eac_ops =3D { .read =3D omap_eac_read, .write =3D omap_eac_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, @@ -744,7 +744,7 @@ static void omap_sti_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_sti_ops =3D { .read =3D omap_sti_read, .write =3D omap_sti_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr, @@ -785,7 +785,7 @@ static void omap_sti_fifo_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps omap_sti_fifo_ops =3D { .read =3D omap_sti_fifo_read, .write =3D omap_sti_fifo_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, @@ -1724,7 +1724,7 @@ static void omap_prcm_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_prcm_ops =3D { .read =3D omap_prcm_read, .write =3D omap_prcm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_prcm_reset(struct omap_prcm_s *s) @@ -2124,7 +2124,7 @@ static const MemoryRegionOps omap_sysctl_ops =3D { .write =3D omap_sysctl_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_sysctl_reset(struct omap_sysctl_s *s) diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index cae78d0..5566407 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -83,7 +83,7 @@ static void static_write(void *opaque, hwaddr offset, static const MemoryRegionOps static_ops =3D { .read =3D static_read, .write =3D static_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; #define sdram_size 0x02000000 diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 9eb9612..78337c3 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -53,7 +53,7 @@ static const MemoryRegionOps static_ops =3D { .write =3D static_write, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* Palm Tunsgten|E support */ diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index e2e43ae..c04b393 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -149,7 +149,7 @@ static void pxa2xx_pm_write(void *opaque, hwaddr addr, static const MemoryRegionOps pxa2xx_pm_ops =3D { .read =3D pxa2xx_pm_read, .write =3D pxa2xx_pm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_pxa2xx_pm =3D { @@ -215,7 +215,7 @@ static void pxa2xx_cm_write(void *opaque, hwaddr addr, static const MemoryRegionOps pxa2xx_cm_ops =3D { .read =3D pxa2xx_cm_read, .write =3D pxa2xx_cm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_pxa2xx_cm =3D { @@ -439,7 +439,7 @@ static void pxa2xx_mm_write(void *opaque, hwaddr addr, static const MemoryRegionOps pxa2xx_mm_ops =3D { .read =3D pxa2xx_mm_read, .write =3D pxa2xx_mm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_pxa2xx_mm =3D { @@ -738,7 +738,7 @@ static void pxa2xx_ssp_write(void *opaque, hwaddr addr, static const MemoryRegionOps pxa2xx_ssp_ops =3D { .read =3D pxa2xx_ssp_read, .write =3D pxa2xx_ssp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pxa2xx_ssp_reset(DeviceState *d) @@ -1105,7 +1105,7 @@ static void pxa2xx_rtc_write(void *opaque, hwaddr add= r, static const MemoryRegionOps pxa2xx_rtc_ops =3D { .read =3D pxa2xx_rtc_read, .write =3D pxa2xx_rtc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pxa2xx_rtc_init(Object *obj) @@ -1426,7 +1426,7 @@ static void pxa2xx_i2c_write(void *opaque, hwaddr add= r, static const MemoryRegionOps pxa2xx_i2c_ops =3D { .read =3D pxa2xx_i2c_read, .write =3D pxa2xx_i2c_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_pxa2xx_i2c_slave =3D { @@ -1684,7 +1684,7 @@ static void pxa2xx_i2s_write(void *opaque, hwaddr add= r, static const MemoryRegionOps pxa2xx_i2s_ops =3D { .read =3D pxa2xx_i2s_read, .write =3D pxa2xx_i2s_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_pxa2xx_i2s =3D { @@ -1921,7 +1921,7 @@ static void pxa2xx_fir_write(void *opaque, hwaddr add= r, static const MemoryRegionOps pxa2xx_fir_ops =3D { .read =3D pxa2xx_fir_read, .write =3D pxa2xx_fir_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int pxa2xx_fir_is_empty(void *opaque) @@ -2109,8 +2109,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, if (serial_hd(i)) { serial_mm_init(address_space, pxa270_serial[i].io_base, 2, qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), - 14857000 / 16, serial_hd(i), - DEVICE_NATIVE_ENDIAN); + 14857000 / 16, serial_hd(i), MO_TE); } else { break; } @@ -2233,8 +2232,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space,= unsigned int sdram_size) if (serial_hd(i)) { serial_mm_init(address_space, pxa255_serial[i].io_base, 2, qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), - 14745600 / 16, serial_hd(i), - DEVICE_NATIVE_ENDIAN); + 14745600 / 16, serial_hd(i), MO_TE); } else { break; } diff --git a/hw/arm/pxa2xx_gpio.c b/hw/arm/pxa2xx_gpio.c index d1fc9cb..36ffb93 100644 --- a/hw/arm/pxa2xx_gpio.c +++ b/hw/arm/pxa2xx_gpio.c @@ -256,7 +256,7 @@ static void pxa2xx_gpio_write(void *opaque, hwaddr offs= et, static const MemoryRegionOps pxa_gpio_ops =3D { .read =3D pxa2xx_gpio_read, .write =3D pxa2xx_gpio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; DeviceState *pxa2xx_gpio_init(hwaddr base, diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 2f4b461..0d95605 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -256,7 +256,7 @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] =3D { static const MemoryRegionOps pxa2xx_pic_ops =3D { .read =3D pxa2xx_pic_mem_read, .write =3D pxa2xx_pic_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int pxa2xx_pic_post_load(void *opaque, int version_id) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index e96d5be..b5f8b76 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1349,7 +1349,7 @@ static MemTxResult smmu_read_mmio(void *opaque, hwadd= r offset, uint64_t *data, static const MemoryRegionOps smmu_mem_ops =3D { .read_with_attrs =3D smmu_read_mmio, .write_with_attrs =3D smmu_write_mmio, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 8, diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 723cf5d..17c0d7a 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -145,7 +145,7 @@ enum { static const MemoryRegionOps sl_ops =3D { .read =3D sl_read, .write =3D sl_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void sl_flash_register(PXA2xxState *cpu, int size) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 499035f..73f0614 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -305,7 +305,7 @@ static void gptm_write(void *opaque, hwaddr offset, static const MemoryRegionOps gptm_ops =3D { .read =3D gptm_read, .write =3D gptm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_stellaris_gptm =3D { @@ -637,7 +637,7 @@ static void ssys_write(void *opaque, hwaddr offset, static const MemoryRegionOps ssys_ops =3D { .read =3D ssys_read, .write =3D ssys_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void ssys_reset(void *opaque) @@ -874,7 +874,7 @@ static void stellaris_i2c_reset(stellaris_i2c_state *s) static const MemoryRegionOps stellaris_i2c_ops =3D { .read =3D stellaris_i2c_read, .write =3D stellaris_i2c_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_stellaris_i2c =3D { @@ -1144,7 +1144,7 @@ static void stellaris_adc_write(void *opaque, hwaddr = offset, static const MemoryRegionOps stellaris_adc_ops =3D { .read =3D stellaris_adc_read, .write =3D stellaris_adc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_stellaris_adc =3D { diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index fed51a8..f475ccf 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -179,7 +179,7 @@ static void strongarm_pic_mem_write(void *opaque, hwadd= r offset, static const MemoryRegionOps strongarm_pic_ops =3D { .read =3D strongarm_pic_mem_read, .write =3D strongarm_pic_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void strongarm_pic_initfn(Object *obj) @@ -379,7 +379,7 @@ static void strongarm_rtc_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps strongarm_rtc_ops =3D { .read =3D strongarm_rtc_read, .write =3D strongarm_rtc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void strongarm_rtc_init(Object *obj) @@ -627,7 +627,7 @@ static void strongarm_gpio_write(void *opaque, hwaddr o= ffset, static const MemoryRegionOps strongarm_gpio_ops =3D { .read =3D strongarm_gpio_read, .write =3D strongarm_gpio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static DeviceState *strongarm_gpio_init(hwaddr base, @@ -820,7 +820,7 @@ static void strongarm_ppc_write(void *opaque, hwaddr of= fset, static const MemoryRegionOps strongarm_ppc_ops =3D { .read =3D strongarm_ppc_read, .write =3D strongarm_ppc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void strongarm_ppc_init(Object *obj) @@ -1225,7 +1225,7 @@ static void strongarm_uart_write(void *opaque, hwaddr= addr, static const MemoryRegionOps strongarm_uart_ops =3D { .read =3D strongarm_uart_read, .write =3D strongarm_uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void strongarm_uart_init(Object *obj) @@ -1514,7 +1514,7 @@ static void strongarm_ssp_write(void *opaque, hwaddr = addr, static const MemoryRegionOps strongarm_ssp_ops =3D { .read =3D strongarm_ssp_read, .write =3D strongarm_ssp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int strongarm_ssp_post_load(void *opaque, int version_id) diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index e585711..7ed7ff2 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -149,7 +149,7 @@ static void vpb_sic_write(void *opaque, hwaddr offset, static const MemoryRegionOps vpb_sic_ops =3D { .read =3D vpb_sic_read, .write =3D vpb_sic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void vpb_sic_init(Object *obj) diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c index fb98da2..e115550 100644 --- a/hw/audio/ac97.c +++ b/hw/audio/ac97.c @@ -1275,7 +1275,7 @@ static const MemoryRegionOps ac97_io_nam_ops =3D { .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t nabm_read(void *opaque, hwaddr addr, unsigned size) @@ -1324,7 +1324,7 @@ static const MemoryRegionOps ac97_io_nabm_ops =3D { .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ac97_on_reset (DeviceState *dev) diff --git a/hw/audio/cs4231.c b/hw/audio/cs4231.c index 8372299..e0b8271 100644 --- a/hw/audio/cs4231.c +++ b/hw/audio/cs4231.c @@ -132,7 +132,7 @@ static void cs_mem_write(void *opaque, hwaddr addr, static const MemoryRegionOps cs_mem_ops =3D { .read =3D cs_mem_read, .write =3D cs_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_cs4231 =3D { diff --git a/hw/audio/es1370.c b/hw/audio/es1370.c index 260c142..b94db3b 100644 --- a/hw/audio/es1370.c +++ b/hw/audio/es1370.c @@ -774,7 +774,7 @@ static const MemoryRegionOps es1370_io_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const VMStateDescription vmstate_es1370_channel =3D { diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index b78baac..1dbd741 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -1068,7 +1068,7 @@ static const MemoryRegionOps intel_hda_mmio_ops =3D { .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* --------------------------------------------------------------------- */ diff --git a/hw/audio/marvell_88w8618.c b/hw/audio/marvell_88w8618.c index ff1a0d0..fcff61e 100644 --- a/hw/audio/marvell_88w8618.c +++ b/hw/audio/marvell_88w8618.c @@ -240,7 +240,7 @@ static void mv88w8618_audio_reset(DeviceState *d) static const MemoryRegionOps mv88w8618_audio_ops =3D { .read =3D mv88w8618_audio_read, .write =3D mv88w8618_audio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void mv88w8618_audio_init(Object *obj) diff --git a/hw/audio/milkymist-ac97.c b/hw/audio/milkymist-ac97.c index bf6a5a6..46b4f1e 100644 --- a/hw/audio/milkymist-ac97.c +++ b/hw/audio/milkymist-ac97.c @@ -176,7 +176,7 @@ static const MemoryRegionOps ac97_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void ac97_in_cb(void *opaque, int avail_b) diff --git a/hw/audio/pl041.c b/hw/audio/pl041.c index 59c6ce1..6f16c34 100644 --- a/hw/audio/pl041.c +++ b/hw/audio/pl041.c @@ -519,7 +519,7 @@ static void pl041_device_reset(DeviceState *d) static const MemoryRegionOps pl041_ops =3D { .read =3D pl041_read, .write =3D pl041_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pl041_init(Object *obj) diff --git a/hw/block/fdc.c b/hw/block/fdc.c index 9b24cb9..f87fbac 100644 --- a/hw/block/fdc.c +++ b/hw/block/fdc.c @@ -981,13 +981,13 @@ static void fdctrl_write_mem (void *opaque, hwaddr re= g, static const MemoryRegionOps fdctrl_mem_ops =3D { .read =3D fdctrl_read_mem, .write =3D fdctrl_write_mem, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const MemoryRegionOps fdctrl_mem_strict_ops =3D { .read =3D fdctrl_read_mem, .write =3D fdctrl_write_mem, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 36d6a8b..7d71e59 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1272,7 +1272,7 @@ static void nvme_mmio_write(void *opaque, hwaddr addr= , uint64_t data, static const MemoryRegionOps nvme_mmio_ops =3D { .read =3D nvme_mmio_read, .write =3D nvme_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 2, .max_access_size =3D 8, @@ -1295,7 +1295,7 @@ static uint64_t nvme_cmb_read(void *opaque, hwaddr ad= dr, unsigned size) static const MemoryRegionOps nvme_cmb_ops =3D { .read =3D nvme_cmb_read, .write =3D nvme_cmb_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 8, diff --git a/hw/block/onenand.c b/hw/block/onenand.c index b3644f7..f475daa 100644 --- a/hw/block/onenand.c +++ b/hw/block/onenand.c @@ -769,7 +769,7 @@ static void onenand_write(void *opaque, hwaddr addr, static const MemoryRegionOps onenand_ops =3D { .read =3D onenand_read, .write =3D onenand_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void onenand_realize(DeviceState *dev, Error **errp) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index a1ec1fa..aa51958 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -694,7 +694,7 @@ static MemTxResult pflash_mem_write_with_attrs(void *op= aque, hwaddr addr, uint64 static const MemoryRegionOps pflash_cfi01_ops =3D { .read_with_attrs =3D pflash_mem_read_with_attrs, .write_with_attrs =3D pflash_mem_write_with_attrs, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pflash_cfi01_realize(DeviceState *dev, Error **errp) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 42886f6..80c4091 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -713,7 +713,7 @@ static const MemoryRegionOps pflash_cfi02_ops =3D { .write =3D pflash_write, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pflash_cfi02_realize(DeviceState *dev, Error **errp) diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c index 94679d2..f3c2947 100644 --- a/hw/char/bcm2835_aux.c +++ b/hw/char/bcm2835_aux.c @@ -244,7 +244,7 @@ static void bcm2835_aux_receive(void *opaque, const uin= t8_t *buf, int size) static const MemoryRegionOps bcm2835_aux_ops =3D { .read =3D bcm2835_aux_read, .write =3D bcm2835_aux_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fa25fe2..f280469 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -457,7 +457,7 @@ static uint64_t uart_read(void *opaque, hwaddr offset, static const MemoryRegionOps uart_ops =3D { .read =3D uart_read, .write =3D uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void cadence_uart_reset(DeviceState *dev) diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c index 606c9cc..e3ef1eb 100644 --- a/hw/char/cmsdk-apb-uart.c +++ b/hw/char/cmsdk-apb-uart.c @@ -298,7 +298,7 @@ static void uart_write(void *opaque, hwaddr offset, uin= t64_t value, static const MemoryRegionOps uart_ops =3D { .read =3D uart_read, .write =3D uart_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void cmsdk_apb_uart_reset(DeviceState *dev) diff --git a/hw/char/debugcon.c b/hw/char/debugcon.c index e1b6d11..1f1cfc5 100644 --- a/hw/char/debugcon.c +++ b/hw/char/debugcon.c @@ -82,7 +82,7 @@ static const MemoryRegionOps debugcon_ops =3D { .write =3D debugcon_ioport_write, .valid.min_access_size =3D 1, .valid.max_access_size =3D 1, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void debugcon_realize_core(DebugconState *s, Error **errp) diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c index e4ac843..863f467 100644 --- a/hw/char/digic-uart.c +++ b/hw/char/digic-uart.c @@ -110,7 +110,7 @@ static const MemoryRegionOps uart_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int uart_can_rx(void *opaque) diff --git a/hw/char/escc.c b/hw/char/escc.c index 8ddbb4b..20bd68a 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -574,7 +574,7 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr, static const MemoryRegionOps escc_mem_ops =3D { .read =3D escc_mem_read, .write =3D escc_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index 9745bca..e9c283e 100644 --- a/hw/char/etraxfs_ser.c +++ b/hw/char/etraxfs_ser.c @@ -155,7 +155,7 @@ ser_write(void *opaque, hwaddr addr, static const MemoryRegionOps ser_ops =3D { .read =3D ser_read, .write =3D ser_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index c5700ee..3497e5b 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -481,7 +481,7 @@ static uint64_t exynos4210_uart_read(void *opaque, hwad= dr offset, static const MemoryRegionOps exynos4210_uart_ops =3D { .read =3D exynos4210_uart_read, .write =3D exynos4210_uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .max_access_size =3D 4, .unaligned =3D false diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c index c2bb3ac..ede9af3 100644 --- a/hw/char/grlib_apbuart.c +++ b/hw/char/grlib_apbuart.c @@ -237,7 +237,7 @@ static void grlib_apbuart_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps grlib_apbuart_ops =3D { .write =3D grlib_apbuart_write, .read =3D grlib_apbuart_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void grlib_apbuart_realize(DeviceState *dev, Error **errp) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 0655a95..1099b4a 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -332,7 +332,7 @@ static void imx_event(void *opaque, int event) static const struct MemoryRegionOps imx_serial_ops =3D { .read =3D imx_serial_read, .write =3D imx_serial_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void imx_serial_realize(DeviceState *dev, Error **errp) diff --git a/hw/char/lm32_uart.c b/hw/char/lm32_uart.c index d047a44..2f01d9a 100644 --- a/hw/char/lm32_uart.c +++ b/hw/char/lm32_uart.c @@ -205,7 +205,7 @@ static void uart_write(void *opaque, hwaddr addr, static const MemoryRegionOps uart_ops =3D { .read =3D uart_read, .write =3D uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c index 7b06110..9ea74de 100644 --- a/hw/char/mcf_uart.c +++ b/hw/char/mcf_uart.c @@ -286,7 +286,7 @@ static void mcf_uart_receive(void *opaque, const uint8_= t *buf, int size) static const MemoryRegionOps mcf_uart_ops =3D { .read =3D mcf_uart_read, .write =3D mcf_uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void mcf_uart_instance_init(Object *obj) diff --git a/hw/char/milkymist-uart.c b/hw/char/milkymist-uart.c index 8a78fcc..86d2ad6 100644 --- a/hw/char/milkymist-uart.c +++ b/hw/char/milkymist-uart.c @@ -156,7 +156,7 @@ static const MemoryRegionOps uart_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void uart_rx(void *opaque, const uint8_t *buf, int size) diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c index c90b491..6a72813 100644 --- a/hw/char/nrf51_uart.c +++ b/hw/char/nrf51_uart.c @@ -189,7 +189,7 @@ static void uart_write(void *opaque, hwaddr addr, static const MemoryRegionOps uart_ops =3D { .read =3D uart_read, .write =3D uart_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void nrf51_uart_reset(DeviceState *dev) diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c index b3bb1cf..2de1abc 100644 --- a/hw/char/omap_uart.c +++ b/hw/char/omap_uart.c @@ -64,7 +64,7 @@ struct omap_uart_s *omap_uart_init(hwaddr base, s->serial =3D serial_mm_init(get_system_memory(), base, 2, irq, omap_clk_getrate(fclk)/16, chr ?: qemu_chr_new(label, "null", NULL), - DEVICE_NATIVE_ENDIAN); + MO_TE); return s; } @@ -156,7 +156,7 @@ static void omap_uart_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_uart_ops =3D { .read =3D omap_uart_read, .write =3D omap_uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, @@ -184,5 +184,5 @@ void omap_uart_attach(struct omap_uart_s *s, Chardev *c= hr) s->serial =3D serial_mm_init(get_system_memory(), s->base, 2, s->irq, omap_clk_getrate(s->fclk) / 16, chr ?: qemu_chr_new("null", "null", NULL), - DEVICE_NATIVE_ENDIAN); + MO_TE); } diff --git a/hw/char/parallel.c b/hw/char/parallel.c index 1cd4c54..32552db 100644 --- a/hw/char/parallel.c +++ b/hw/char/parallel.c @@ -588,7 +588,7 @@ static const MemoryRegionOps parallel_mm_ops =3D { .write =3D parallel_mm_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* If fd is zero, it means that the parallel device uses the console */ diff --git a/hw/char/pl011.c b/hw/char/pl011.c index c1ae2f3..51c110c 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -287,7 +287,7 @@ static void pl011_event(void *opaque, int event) static const MemoryRegionOps pl011_ops =3D { .read =3D pl011_read, .write =3D pl011_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_pl011 =3D { diff --git a/hw/char/serial.c b/hw/char/serial.c index 7345f69..0b5bbaf 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -973,7 +973,7 @@ const MemoryRegionOps serial_io_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; SerialState *serial_init(int base, qemu_irq irq, int baudbase, @@ -1016,14 +1016,14 @@ static const MemoryRegionOps serial_mm_ops[2] =3D { [0] =3D { .read =3D serial_mm_read, .write =3D serial_mm_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.max_access_size =3D 8, .impl.max_access_size =3D 8, }, [1] =3D { .read =3D serial_mm_read, .write =3D serial_mm_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid.max_access_size =3D 8, .impl.max_access_size =3D 8, }, @@ -1032,7 +1032,7 @@ static const MemoryRegionOps serial_mm_ops[2] =3D { SerialState *serial_mm_init(MemoryRegion *address_space, hwaddr base, int it_shift, qemu_irq irq, int baudbase, - Chardev *chr, enum device_endian end) + Chardev *chr, MemOp end) { SerialState *s; @@ -1047,7 +1047,7 @@ SerialState *serial_mm_init(MemoryRegion *address_spa= ce, vmstate_register(NULL, base, &vmstate_serial, s); memory_region_init_io(&s->io, NULL, - &serial_mm_ops[end =3D=3D DEVICE_LITTLE_ENDIAN ?= 0 : 1], + &serial_mm_ops[end =3D=3D MO_LE ? 0 : 1], s, "serial", 8 << it_shift); memory_region_add_subregion(address_space, base, &s->io); return s; diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 67740b7..f789c06 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -367,7 +367,7 @@ static void sh_serial_event(void *opaque, int event) static const MemoryRegionOps sh_serial_ops =3D { .read =3D sh_serial_read, .write =3D sh_serial_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void sh_serial_init(MemoryRegion *sysmem, diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 40c365b..65fd733 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -187,7 +187,7 @@ static void stm32f2xx_usart_write(void *opaque, hwaddr = addr, static const MemoryRegionOps stm32f2xx_usart_ops =3D { .read =3D stm32f2xx_usart_read, .write =3D stm32f2xx_usart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static Property stm32f2xx_usart_properties[] =3D { diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index 880962a..48f2b85 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -166,7 +166,7 @@ uart_write(void *opaque, hwaddr addr, static const MemoryRegionOps uart_ops =3D { .read =3D uart_read, .write =3D uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4 diff --git a/hw/core/empty_slot.c b/hw/core/empty_slot.c index c694532..245a333 100644 --- a/hw/core/empty_slot.c +++ b/hw/core/empty_slot.c @@ -50,7 +50,7 @@ static void empty_slot_write(void *opaque, hwaddr addr, static const MemoryRegionOps empty_slot_ops =3D { .read =3D empty_slot_read, .write =3D empty_slot_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void empty_slot_init(hwaddr addr, uint64_t slot_size) diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index 940c7dd..a98ffd3 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -83,7 +83,7 @@ nand_write(void *opaque, hwaddr addr, uint64_t value, static const MemoryRegionOps nand_ops =3D { .read =3D nand_read, .write =3D nand_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct tempsensor_t @@ -235,7 +235,7 @@ static void gpio_write(void *opaque, hwaddr addr, uint6= 4_t value, static const MemoryRegionOps gpio_ops =3D { .read =3D gpio_read, .write =3D gpio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/display/ati.c b/hw/display/ati.c index a747c4c..ef37e8d 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -810,7 +810,7 @@ static void ati_mm_write(void *opaque, hwaddr addr, static const MemoryRegionOps ati_mm_ops =3D { .read =3D ati_mm_read, .write =3D ati_mm_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ati_vga_realize(PCIDevice *dev, Error **errp) diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c index 2311ec7..78dc827 100644 --- a/hw/display/bcm2835_fb.c +++ b/hw/display/bcm2835_fb.c @@ -340,7 +340,7 @@ static void bcm2835_fb_write(void *opaque, hwaddr offse= t, uint64_t value, static const MemoryRegionOps bcm2835_fb_ops =3D { .read =3D bcm2835_fb_read, .write =3D bcm2835_fb_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index 582133d..366a259 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -106,7 +106,7 @@ static const MemoryRegionOps bochs_display_vbe_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 2, .impl.max_access_size =3D 2, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t bochs_display_qext_read(void *ptr, hwaddr addr, @@ -147,7 +147,7 @@ static const MemoryRegionOps bochs_display_qext_ops =3D= { .write =3D bochs_display_qext_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static int bochs_display_get_mode(BochsDisplayState *s, diff --git a/hw/display/cg3.c b/hw/display/cg3.c index a7340dc..dade07d 100644 --- a/hw/display/cg3.c +++ b/hw/display/cg3.c @@ -267,7 +267,7 @@ static void cg3_reg_write(void *opaque, hwaddr addr, ui= nt64_t val, static const MemoryRegionOps cg3_reg_ops =3D { .read =3D cg3_reg_read, .write =3D cg3_reg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index 2e4911a..03123ba 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -2123,7 +2123,7 @@ static void cirrus_vga_mem_write(void *opaque, static const MemoryRegionOps cirrus_vga_mem_ops =3D { .read =3D cirrus_vga_mem_read, .write =3D cirrus_vga_mem_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -2436,7 +2436,7 @@ static void cirrus_linear_bitblt_write(void *opaque, static const MemoryRegionOps cirrus_linear_bitblt_io_ops =3D { .read =3D cirrus_linear_bitblt_read, .write =3D cirrus_linear_bitblt_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -2736,7 +2736,7 @@ static void cirrus_mmio_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps cirrus_mmio_io_ops =3D { .read =3D cirrus_mmio_read, .write =3D cirrus_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -2847,7 +2847,7 @@ static void cirrus_reset(void *opaque) static const MemoryRegionOps cirrus_linear_io_ops =3D { .read =3D cirrus_linear_read, .write =3D cirrus_linear_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -2857,7 +2857,7 @@ static const MemoryRegionOps cirrus_linear_io_ops =3D= { static const MemoryRegionOps cirrus_vga_io_ops =3D { .read =3D cirrus_vga_ioport_read, .write =3D cirrus_vga_ioport_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/display/edid-region.c b/hw/display/edid-region.c index d0d31ba..094b200 100644 --- a/hw/display/edid-region.c +++ b/hw/display/edid-region.c @@ -21,7 +21,7 @@ static const MemoryRegionOps edid_region_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 1, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; void qemu_edid_region_io(MemoryRegion *region, Object *owner, diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c index 61f7408..cdd2977 100644 --- a/hw/display/exynos4210_fimd.c +++ b/hw/display/exynos4210_fimd.c @@ -1818,7 +1818,7 @@ static const MemoryRegionOps exynos4210_fimd_mmio_ops= =3D { .max_access_size =3D 4, .unaligned =3D false }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int exynos4210_fimd_load(void *opaque, int version_id) diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index 1774b44..3b02d3f 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -428,7 +428,7 @@ static void g364fb_ctrl_write(void *opaque, static const MemoryRegionOps g364fb_ctrl_ops =3D { .read =3D g364fb_ctrl_read, .write =3D g364fb_ctrl_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, }; diff --git a/hw/display/jazz_led.c b/hw/display/jazz_led.c index 783189e..6f3e626 100644 --- a/hw/display/jazz_led.c +++ b/hw/display/jazz_led.c @@ -72,7 +72,7 @@ static void jazz_led_write(void *opaque, hwaddr addr, static const MemoryRegionOps led_ops =3D { .read =3D jazz_led_read, .write =3D jazz_led_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl.min_access_size =3D 1, .impl.max_access_size =3D 1, }; diff --git a/hw/display/milkymist-tmu2.c b/hw/display/milkymist-tmu2.c index e1ed018..ed39a14 100644 --- a/hw/display/milkymist-tmu2.c +++ b/hw/display/milkymist-tmu2.c @@ -434,7 +434,7 @@ static const MemoryRegionOps tmu2_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void milkymist_tmu2_reset(DeviceState *d) diff --git a/hw/display/milkymist-vgafb.c b/hw/display/milkymist-vgafb.c index dce1dd7..1c7fc17 100644 --- a/hw/display/milkymist-vgafb.c +++ b/hw/display/milkymist-vgafb.c @@ -269,7 +269,7 @@ static const MemoryRegionOps vgafb_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void milkymist_vgafb_reset(DeviceState *d) diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c index 601f178..cb6b882 100644 --- a/hw/display/omap_dss.c +++ b/hw/display/omap_dss.c @@ -245,7 +245,7 @@ static void omap_diss_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_diss_ops =3D { .read =3D omap_diss_read, .write =3D omap_diss_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t omap_disc_read(void *opaque, hwaddr addr, @@ -589,7 +589,7 @@ static void omap_disc_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_disc_ops =3D { .read =3D omap_disc_read, .write =3D omap_disc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_rfbi_transfer_stop(struct omap_dss_s *s) @@ -865,7 +865,7 @@ static void omap_rfbi_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_rfbi_ops =3D { .read =3D omap_rfbi_read, .write =3D omap_rfbi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t omap_venc_read(void *opaque, hwaddr addr, @@ -988,7 +988,7 @@ static void omap_venc_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_venc_ops =3D { .read =3D omap_venc_read, .write =3D omap_venc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t omap_im3_read(void *opaque, hwaddr addr, @@ -1042,7 +1042,7 @@ static void omap_im3_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_im3_ops =3D { .read =3D omap_im3_read, .write =3D omap_im3_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index 07a5eff..d5d316f 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -330,7 +330,7 @@ static void omap_lcdc_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_lcdc_ops =3D { .read =3D omap_lcdc_read, .write =3D omap_lcdc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void omap_lcdc_reset(struct omap_lcd_panel_s *s) diff --git a/hw/display/pl110.c b/hw/display/pl110.c index 2bdfc3c..cec81ba 100644 --- a/hw/display/pl110.c +++ b/hw/display/pl110.c @@ -471,7 +471,7 @@ static void pl110_write(void *opaque, hwaddr offset, static const MemoryRegionOps pl110_ops =3D { .read =3D pl110_read, .write =3D pl110_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pl110_mux_ctrl_set(void *opaque, int line, int level) diff --git a/hw/display/pxa2xx_lcd.c b/hw/display/pxa2xx_lcd.c index b83f807..fc2a3c4 100644 --- a/hw/display/pxa2xx_lcd.c +++ b/hw/display/pxa2xx_lcd.c @@ -567,7 +567,7 @@ static void pxa2xx_lcdc_write(void *opaque, hwaddr offs= et, static const MemoryRegionOps pxa2xx_lcdc_ops =3D { .read =3D pxa2xx_lcdc_read, .write =3D pxa2xx_lcdc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* Load new palette for a given DMA channel, convert to internal format */ diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 5918f59..b147d98 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -967,7 +967,7 @@ static const MemoryRegionOps sm501_system_config_ops = =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t sm501_i2c_read(void *opaque, hwaddr addr, unsigned size) @@ -1070,7 +1070,7 @@ static const MemoryRegionOps sm501_i2c_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint32_t sm501_palette_read(void *opaque, hwaddr addr) @@ -1358,7 +1358,7 @@ static const MemoryRegionOps sm501_disp_ctrl_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t sm501_2d_engine_read(void *opaque, hwaddr addr, @@ -1533,7 +1533,7 @@ static const MemoryRegionOps sm501_2d_engine_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; /* draw line functions for all console modes */ @@ -1961,7 +1961,7 @@ static void sm501_realize_sysbus(DeviceState *dev, Er= ror **errp) if (s->chr_state) { serial_mm_init(&s->state.mmio_region, SM501_UART0, 2, NULL, /* TODO : chain irq to IRL */ - 115200, s->chr_state, DEVICE_LITTLE_ENDIAN); + 115200, s->chr_state, MO_LE); } } diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c index 0b7c59c..21109d6 100644 --- a/hw/display/tc6393xb.c +++ b/hw/display/tc6393xb.c @@ -547,7 +547,7 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint= 32_t base, qemu_irq irq) static const MemoryRegionOps tc6393xb_ops =3D { .read =3D tc6393xb_readb, .write =3D tc6393xb_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/display/tcx.c b/hw/display/tcx.c index cdabcbc..3a841dc 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -462,7 +462,7 @@ static void tcx_dac_writel(void *opaque, hwaddr addr, u= int64_t val, static const MemoryRegionOps tcx_dac_ops =3D { .read =3D tcx_dac_readl, .write =3D tcx_dac_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -543,7 +543,7 @@ static void tcx_rstip_writel(void *opaque, hwaddr addr, static const MemoryRegionOps tcx_stip_ops =3D { .read =3D tcx_stip_readl, .write =3D tcx_stip_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -553,7 +553,7 @@ static const MemoryRegionOps tcx_stip_ops =3D { static const MemoryRegionOps tcx_rstip_ops =3D { .read =3D tcx_stip_readl, .write =3D tcx_rstip_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -635,7 +635,7 @@ static void tcx_rblit_writel(void *opaque, hwaddr addr, static const MemoryRegionOps tcx_blit_ops =3D { .read =3D tcx_blit_readl, .write =3D tcx_blit_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -645,7 +645,7 @@ static const MemoryRegionOps tcx_blit_ops =3D { static const MemoryRegionOps tcx_rblit_ops =3D { .read =3D tcx_blit_readl, .write =3D tcx_rblit_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -707,7 +707,7 @@ static void tcx_thc_writel(void *opaque, hwaddr addr, static const MemoryRegionOps tcx_thc_ops =3D { .read =3D tcx_thc_readl, .write =3D tcx_thc_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -729,7 +729,7 @@ static void tcx_dummy_writel(void *opaque, hwaddr addr, static const MemoryRegionOps tcx_dummy_ops =3D { .read =3D tcx_dummy_readl, .write =3D tcx_dummy_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/display/vga-isa-mm.c b/hw/display/vga-isa-mm.c index 215e649..58e299b 100644 --- a/hw/display/vga-isa-mm.c +++ b/hw/display/vga-isa-mm.c @@ -60,7 +60,7 @@ static const MemoryRegionOps vga_mm_ctrl_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void vga_mm_init(ISAVGAMMState *s, hwaddr vram_base, diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c index dedac5d..c893968 100644 --- a/hw/display/vga-pci.c +++ b/hw/display/vga-pci.c @@ -110,7 +110,7 @@ static const MemoryRegionOps pci_vga_ioport_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 2, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr, @@ -140,7 +140,7 @@ static const MemoryRegionOps pci_vga_bochs_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 2, .impl.max_access_size =3D 2, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size) @@ -194,7 +194,7 @@ static const MemoryRegionOps pci_vga_qext_ops =3D { .write =3D pci_vga_qext_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; void pci_std_vga_mmio_region_init(VGACommonState *s, diff --git a/hw/display/vga.c b/hw/display/vga.c index 910a23c..046bbfa 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -2062,7 +2062,7 @@ static void vga_mem_write(void *opaque, hwaddr addr, const MemoryRegionOps vga_mem_ops =3D { .read =3D vga_mem_read, .write =3D vga_mem_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index 249a179..e534a33 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -1280,7 +1280,7 @@ static void vmsvga_io_write(void *opaque, hwaddr addr, static const MemoryRegionOps vmsvga_io_ops =3D { .read =3D vmsvga_io_read, .write =3D vmsvga_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index cc5b650..9fbfc0b 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -301,7 +301,7 @@ static void xlnx_dp_audio_write(void *opaque, hwaddr of= fset, uint64_t value, static const MemoryRegionOps audio_ops =3D { .read =3D xlnx_dp_audio_read, .write =3D xlnx_dp_audio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static inline uint32_t xlnx_dp_audio_get_volume(XlnxDPState *s, @@ -876,7 +876,7 @@ static void xlnx_dp_write(void *opaque, hwaddr offset, = uint64_t value, static const MemoryRegionOps dp_ops =3D { .read =3D xlnx_dp_read, .write =3D xlnx_dp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -991,7 +991,7 @@ static uint64_t xlnx_dp_vblend_read(void *opaque, hwadd= r offset, static const MemoryRegionOps vblend_ops =3D { .read =3D xlnx_dp_vblend_read, .write =3D xlnx_dp_vblend_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1104,7 +1104,7 @@ static uint64_t xlnx_dp_avbufm_read(void *opaque, hwa= ddr offset, static const MemoryRegionOps avbufm_ops =3D { .read =3D xlnx_dp_avbufm_read, .write =3D xlnx_dp_avbufm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/dma/bcm2835_dma.c b/hw/dma/bcm2835_dma.c index a39e8f4..2148db1 100644 --- a/hw/dma/bcm2835_dma.c +++ b/hw/dma/bcm2835_dma.c @@ -288,7 +288,7 @@ static void bcm2835_dma15_write(void *opaque, hwaddr of= fset, uint64_t value, static const MemoryRegionOps bcm2835_dma0_ops =3D { .read =3D bcm2835_dma0_read, .write =3D bcm2835_dma0_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; @@ -296,7 +296,7 @@ static const MemoryRegionOps bcm2835_dma0_ops =3D { static const MemoryRegionOps bcm2835_dma15_ops =3D { .read =3D bcm2835_dma15_read, .write =3D bcm2835_dma15_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index 85783eb..bd26769 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -697,7 +697,7 @@ dma_write(void *opaque, hwaddr addr, static const MemoryRegionOps dma_ops =3D { .read =3D dma_read, .write =3D dma_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4 diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index 30a3442..cf71c47 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -475,7 +475,7 @@ static int i8257_phony_handler(void *opaque, int nchan,= int dma_pos, static const MemoryRegionOps channel_io_ops =3D { .read =3D i8257_read_chan, .write =3D i8257_write_chan, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -499,7 +499,7 @@ static const MemoryRegionPortio pageh_portio_list[] =3D= { static const MemoryRegionOps cont_io_ops =3D { .read =3D i8257_read_cont, .write =3D i8257_write_cont, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index eab83c5..16cc7df 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -1552,7 +1552,7 @@ static void omap_dma_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_dma_ops =3D { .read =3D omap_dma_read, .write =3D omap_dma_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_dma_request(void *opaque, int drq, int req) @@ -2073,7 +2073,7 @@ static void omap_dma4_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_dma4_ops =3D { .read =3D omap_dma4_read, .write =3D omap_dma4_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index 7e57624..4e80459 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -346,7 +346,7 @@ static void pl080_write(void *opaque, hwaddr offset, static const MemoryRegionOps pl080_ops =3D { .read =3D pl080_read, .write =3D pl080_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pl080_reset(DeviceState *dev) diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index a56a3e7..deec0bc 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1493,7 +1493,7 @@ static uint64_t pl330_iomem_read(void *opaque, hwaddr= offset, static const MemoryRegionOps pl330_ops =3D { .read =3D pl330_iomem_read, .write =3D pl330_iomem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/dma/puv3_dma.c b/hw/dma/puv3_dma.c index 122f87a..94947bc 100644 --- a/hw/dma/puv3_dma.c +++ b/hw/dma/puv3_dma.c @@ -75,7 +75,7 @@ static const MemoryRegionOps puv3_dma_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void puv3_dma_realize(DeviceState *dev, Error **errp) diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c index d6fb957..fa1c38f 100644 --- a/hw/dma/pxa2xx_dma.c +++ b/hw/dma/pxa2xx_dma.c @@ -424,7 +424,7 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offse= t, static const MemoryRegionOps pxa2xx_dma_ops =3D { .read =3D pxa2xx_dma_read, .write =3D pxa2xx_dma_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pxa2xx_dma_request(void *opaque, int req_num, int on) diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index 155af9b..631880d 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -387,7 +387,7 @@ static const MemoryRegionOps rc4030_ops =3D { .write =3D rc4030_write, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void update_jazz_irq(rc4030State *s) @@ -490,7 +490,7 @@ static const MemoryRegionOps jazzio_ops =3D { .write =3D jazzio_write, .impl.min_access_size =3D 2, .impl.max_access_size =3D 2, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr= addr, diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index 88765d0..2cc1562 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -224,7 +224,7 @@ static void dma_mem_write(void *opaque, hwaddr addr, static const MemoryRegionOps dma_mem_ops =3D { .read =3D dma_mem_read, .write =3D dma_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 921be17..da79828 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -512,7 +512,7 @@ static void axidma_write(void *opaque, hwaddr addr, static const MemoryRegionOps axidma_ops =3D { .read =3D axidma_read, .write =3D axidma_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void xilinx_axidma_realize(DeviceState *dev, Error **errp) diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c index 51e1ead..ecf4ff6 100644 --- a/hw/dma/xlnx-zdma.c +++ b/hw/dma/xlnx-zdma.c @@ -742,7 +742,7 @@ static void zdma_write(void *opaque, hwaddr addr, uint6= 4_t value, static const MemoryRegionOps zdma_ops =3D { .read =3D zdma_read, .write =3D zdma_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 7a03ce1..a14c966 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -319,7 +319,7 @@ static const RegisterAccessInfo xlnx_zynq_devcfg_regs_i= nfo[] =3D { static const MemoryRegionOps xlnx_zynq_devcfg_reg_ops =3D { .read =3D register_read_memory, .write =3D register_write_memory, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c index e834f81..47a0a82 100644 --- a/hw/dma/xlnx_dpdma.c +++ b/hw/dma/xlnx_dpdma.c @@ -552,7 +552,7 @@ static void xlnx_dpdma_write(void *opaque, hwaddr offse= t, static const MemoryRegionOps dma_ops =3D { .read =3D xlnx_dpdma_read, .write =3D xlnx_dpdma_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/gpio/bcm2835_gpio.c b/hw/gpio/bcm2835_gpio.c index ba8dd6c..8b072f5 100644 --- a/hw/gpio/bcm2835_gpio.c +++ b/hw/gpio/bcm2835_gpio.c @@ -275,7 +275,7 @@ static void bcm2835_gpio_reset(DeviceState *dev) static const MemoryRegionOps bcm2835_gpio_ops =3D { .read =3D bcm2835_gpio_read, .write =3D bcm2835_gpio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_bcm2835_gpio =3D { diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c index a51af72..d60e5d3 100644 --- a/hw/gpio/imx_gpio.c +++ b/hw/gpio/imx_gpio.c @@ -267,7 +267,7 @@ static const MemoryRegionOps imx_gpio_ops =3D { .write =3D imx_gpio_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_imx_gpio =3D { diff --git a/hw/gpio/mpc8xxx.c b/hw/gpio/mpc8xxx.c index 6ff56dc..76d9eb8 100644 --- a/hw/gpio/mpc8xxx.c +++ b/hw/gpio/mpc8xxx.c @@ -180,7 +180,7 @@ static void mpc8xxx_gpio_set_irq(void * opaque, int irq= , int level) static const MemoryRegionOps mpc8xxx_gpio_ops =3D { .read =3D mpc8xxx_gpio_read, .write =3D mpc8xxx_gpio_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void mpc8xxx_gpio_initfn(Object *obj) diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c index dd6c16a..f49ef56 100644 --- a/hw/gpio/nrf51_gpio.c +++ b/hw/gpio/nrf51_gpio.c @@ -225,7 +225,7 @@ static void nrf51_gpio_write(void *opaque, hwaddr offse= t, static const MemoryRegionOps gpio_ops =3D { .read =3D nrf51_gpio_read, .write =3D nrf51_gpio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, }; diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c index e2785c5..7307717 100644 --- a/hw/gpio/omap_gpio.c +++ b/hw/gpio/omap_gpio.c @@ -177,7 +177,7 @@ static void omap_gpio_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_gpio_ops =3D { .read =3D omap_gpio_read, .write =3D omap_gpio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_gpio_reset(struct omap_gpio_s *s) @@ -592,7 +592,7 @@ static const MemoryRegionOps omap2_gpio_module_ops =3D { .write =3D omap2_gpio_module_writep, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_gpif_reset(DeviceState *dev) @@ -675,7 +675,7 @@ static void omap2_gpif_top_write(void *opaque, hwaddr a= ddr, static const MemoryRegionOps omap2_gpif_top_ops =3D { .read =3D omap2_gpif_top_read, .write =3D omap2_gpif_top_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_gpio_init(Object *obj) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 02c01fd..c976233 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -339,7 +339,7 @@ static void pl061_set_irq(void * opaque, int irq, int l= evel) static const MemoryRegionOps pl061_ops =3D { .read =3D pl061_read, .write =3D pl061_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pl061_luminary_init(Object *obj) diff --git a/hw/gpio/puv3_gpio.c b/hw/gpio/puv3_gpio.c index 54d30ca..f1c5120 100644 --- a/hw/gpio/puv3_gpio.c +++ b/hw/gpio/puv3_gpio.c @@ -98,7 +98,7 @@ static const MemoryRegionOps puv3_gpio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void puv3_gpio_realize(DeviceState *dev, Error **errp) diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c index f2f1f67..d939004 100644 --- a/hw/gpio/zaurus.c +++ b/hw/gpio/zaurus.c @@ -156,7 +156,7 @@ static void scoop_write(void *opaque, hwaddr addr, static const MemoryRegionOps scoop_ops =3D { .read =3D scoop_read, .write =3D scoop_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void scoop_gpio_set(void *opaque, int line, int level) diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c index e94614a..9369c36 100644 --- a/hw/hppa/dino.c +++ b/hw/hppa/dino.c @@ -309,7 +309,7 @@ static MemTxResult dino_chip_write_with_attrs(void *opa= que, hwaddr addr, static const MemoryRegionOps dino_chip_ops =3D { .read_with_attrs =3D dino_chip_read_with_attrs, .write_with_attrs =3D dino_chip_write_with_attrs, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, @@ -357,7 +357,7 @@ static void dino_config_data_write(void *opaque, hwaddr= addr, static const MemoryRegionOps dino_config_data_ops =3D { .read =3D dino_config_data_read, .write =3D dino_config_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned = len) @@ -378,7 +378,7 @@ static const MemoryRegionOps dino_config_addr_ops =3D { .write =3D dino_config_addr_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque, diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 662838d..974adaa 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -113,7 +113,7 @@ static void machine_hppa_init(MachineState *machine) if (serial_hd(0)) { uint32_t addr =3D DINO_UART_HPA + 0x800; serial_mm_init(addr_space, addr, 0, serial_irq, - 115200, serial_hd(0), DEVICE_BIG_ENDIAN); + 115200, serial_hd(0), MO_BE); } /* SCSI disk setup. */ diff --git a/hw/hppa/pci.c b/hw/hppa/pci.c index b6606d9..4cf8094 100644 --- a/hw/hppa/pci.c +++ b/hw/hppa/pci.c @@ -24,7 +24,7 @@ static void ignore_write(void *opaque, hwaddr addr, uint6= 4_t v, unsigned size) const MemoryRegionOps hppa_pci_ignore_ops =3D { .read =3D ignore_read, .write =3D ignore_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 8, @@ -54,7 +54,7 @@ static void bw_conf1_write(void *opaque, hwaddr addr, const MemoryRegionOps hppa_pci_conf1_ops =3D { .read =3D bw_conf1_read, .write =3D bw_conf1_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 4, @@ -77,7 +77,7 @@ static void special_write(void *opaque, hwaddr addr, const MemoryRegionOps hppa_pci_iack_ops =3D { .read =3D iack_read, .write =3D special_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/hyperv/hyperv_testdev.c b/hw/hyperv/hyperv_testdev.c index 0d343a8..823c790 100644 --- a/hw/hyperv/hyperv_testdev.c +++ b/hw/hyperv/hyperv_testdev.c @@ -288,7 +288,7 @@ static const MemoryRegionOps synic_test_sint_ops =3D { .write =3D hv_test_dev_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void hv_test_dev_realizefn(DeviceState *d, Error **errp) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 219ad38..f8811c0 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -364,13 +364,13 @@ static void aspeed_i2c_ctrl_write(void *opaque, hwadd= r offset, static const MemoryRegionOps aspeed_i2c_bus_ops =3D { .read =3D aspeed_i2c_bus_read, .write =3D aspeed_i2c_bus_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps aspeed_i2c_ctrl_ops =3D { .read =3D aspeed_i2c_ctrl_read, .write =3D aspeed_i2c_ctrl_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const VMStateDescription aspeed_i2c_bus_vmstate =3D { diff --git a/hw/i2c/exynos4210_i2c.c b/hw/i2c/exynos4210_i2c.c index 70a97a3..0823e66 100644 --- a/hw/i2c/exynos4210_i2c.c +++ b/hw/i2c/exynos4210_i2c.c @@ -264,7 +264,7 @@ static void exynos4210_i2c_write(void *opaque, hwaddr o= ffset, static const MemoryRegionOps exynos4210_i2c_ops =3D { .read =3D exynos4210_i2c_read, .write =3D exynos4210_i2c_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription exynos4210_i2c_vmstate =3D { diff --git a/hw/i2c/imx_i2c.c b/hw/i2c/imx_i2c.c index ce7a94c..d9900cd 100644 --- a/hw/i2c/imx_i2c.c +++ b/hw/i2c/imx_i2c.c @@ -276,7 +276,7 @@ static const MemoryRegionOps imx_i2c_ops =3D { .write =3D imx_i2c_write, .valid.min_access_size =3D 1, .valid.max_access_size =3D 2, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription imx_i2c_vmstate =3D { diff --git a/hw/i2c/microbit_i2c.c b/hw/i2c/microbit_i2c.c index 214be07..e756b1c 100644 --- a/hw/i2c/microbit_i2c.c +++ b/hw/i2c/microbit_i2c.c @@ -70,7 +70,7 @@ static void microbit_i2c_write(void *opaque, hwaddr addr,= uint64_t data, static const MemoryRegionOps microbit_i2c_ops =3D { .read =3D microbit_i2c_read, .write =3D microbit_i2c_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, }; diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c index e9a1127..63efec6 100644 --- a/hw/i2c/mpc_i2c.c +++ b/hw/i2c/mpc_i2c.c @@ -304,7 +304,7 @@ static const MemoryRegionOps i2c_ops =3D { .read =3D mpc_i2c_read, .write =3D mpc_i2c_write, .valid.max_access_size =3D 1, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription mpc_i2c_vmstate =3D { diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c index d7ebeae..99a328a 100644 --- a/hw/i2c/omap_i2c.c +++ b/hw/i2c/omap_i2c.c @@ -469,7 +469,7 @@ static const MemoryRegionOps omap_i2c_ops =3D { .write =3D omap_i2c_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_i2c_init(Object *obj) diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index e48544f..87b35af 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -451,7 +451,7 @@ static const MemoryRegionOps pm_smbus_ops =3D { .write =3D smb_ioport_writeb, .valid.min_access_size =3D 1, .valid.max_access_size =3D 1, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; bool pm_smbus_vmstate_needed(void) diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c index 462729d..1ab2381 100644 --- a/hw/i2c/ppc4xx_i2c.c +++ b/hw/i2c/ppc4xx_i2c.c @@ -335,7 +335,7 @@ static const MemoryRegionOps ppc4xx_i2c_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 1, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void ppc4xx_i2c_init(Object *o) diff --git a/hw/i2c/versatile_i2c.c b/hw/i2c/versatile_i2c.c index 1ac2a6f..3738bdd 100644 --- a/hw/i2c/versatile_i2c.c +++ b/hw/i2c/versatile_i2c.c @@ -77,7 +77,7 @@ static void versatile_i2c_write(void *opaque, hwaddr offs= et, static const MemoryRegionOps versatile_i2c_ops =3D { .read =3D versatile_i2c_read, .write =3D versatile_i2c_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void versatile_i2c_init(Object *obj) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 4a4e2c7..0612296 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1378,7 +1378,7 @@ static MemTxResult amdvi_mem_ir_read(void *opaque, hw= addr addr, static const MemoryRegionOps amdvi_ir_ops =3D { .read_with_attrs =3D amdvi_mem_ir_read, .write_with_attrs =3D amdvi_mem_ir_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1452,7 +1452,7 @@ static AddressSpace *amdvi_host_dma_iommu(PCIBus *bus= , void *opaque, int devfn) static const MemoryRegionOps mmio_mem_ops =3D { .read =3D amdvi_mmio_read, .write =3D amdvi_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 8, diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index de86f53..e9dd1ab 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2993,7 +2993,7 @@ static const VMStateDescription vtd_vmstate =3D { static const MemoryRegionOps vtd_mem_ops =3D { .read =3D vtd_mem_read, .write =3D vtd_mem_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 8, @@ -3270,7 +3270,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwa= ddr addr, static const MemoryRegionOps vtd_mem_ir_ops =3D { .read_with_attrs =3D vtd_mem_ir_read, .write_with_attrs =3D vtd_mem_ir_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index 91fb622..e645447 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -207,7 +207,7 @@ static void kvm_apic_mem_write(void *opaque, hwaddr add= r, static const MemoryRegionOps kvm_apic_io_ops =3D { .read =3D kvm_apic_mem_read, .write =3D kvm_apic_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void kvm_apic_reset(APICCommonState *s) diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 9c2ab4a..9c65e41 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -717,7 +717,7 @@ static uint64_t vapic_read(void *opaque, hwaddr addr, u= nsigned size) static const MemoryRegionOps vapic_ops =3D { .write =3D vapic_write, .read =3D vapic_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void vapic_realize(DeviceState *dev, Error **errp) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 549c437..c2507b5 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -813,7 +813,7 @@ static const MemoryRegionOps port92_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void port92_initfn(Object *obj) @@ -1985,7 +1985,7 @@ DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci= _bus) static const MemoryRegionOps ioport80_io_ops =3D { .write =3D ioport80_write, .read =3D ioport80_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -1995,7 +1995,7 @@ static const MemoryRegionOps ioport80_io_ops =3D { static const MemoryRegionOps ioportF0_io_ops =3D { .write =3D ioportF0_write, .read =3D ioportF0_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/i386/vmport.c b/hw/i386/vmport.c index 3bf8cfe..a30032d 100644 --- a/hw/i386/vmport.c +++ b/hw/i386/vmport.c @@ -139,7 +139,7 @@ static const MemoryRegionOps vmport_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void vmport_realizefn(DeviceState *dev, Error **errp) diff --git a/hw/i386/xen/xen_apic.c b/hw/i386/xen/xen_apic.c index 7c7a60b..2a28057 100644 --- a/hw/i386/xen/xen_apic.c +++ b/hw/i386/xen/xen_apic.c @@ -36,7 +36,7 @@ static void xen_apic_mem_write(void *opaque, hwaddr addr, static const MemoryRegionOps xen_apic_io_ops =3D { .read =3D xen_apic_mem_read, .write =3D xen_apic_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void xen_apic_realize(DeviceState *dev, Error **errp) diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c index 7a972e4..af56c59 100644 --- a/hw/i386/xen/xen_platform.c +++ b/hw/i386/xen/xen_platform.c @@ -329,7 +329,7 @@ static const MemoryRegionOps platform_fixed_io_ops =3D { .max_access_size =3D 4, .unaligned =3D true, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void platform_fixed_ioport_init(PCIXenPlatformState* s) @@ -427,7 +427,7 @@ static void platform_mmio_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps platform_mmio_handler =3D { .read =3D &platform_mmio_read, .write =3D &platform_mmio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void platform_mmio_setup(PCIXenPlatformState *d) diff --git a/hw/i386/xen/xen_pvdevice.c b/hw/i386/xen/xen_pvdevice.c index 23748f3..b65fdd2 100644 --- a/hw/i386/xen/xen_pvdevice.c +++ b/hw/i386/xen/xen_pvdevice.c @@ -69,7 +69,7 @@ static void xen_pv_mmio_write(void *opaque, hwaddr addr, static const MemoryRegionOps xen_pv_mmio_ops =3D { .read =3D &xen_pv_mmio_read, .write =3D &xen_pv_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const VMStateDescription vmstate_xen_pvdevice =3D { diff --git a/hw/ide/ahci-allwinner.c b/hw/ide/ahci-allwinner.c index de08d87..714267c 100644 --- a/hw/ide/ahci-allwinner.c +++ b/hw/ide/ahci-allwinner.c @@ -82,7 +82,7 @@ static const MemoryRegionOps allwinner_ahci_mem_ops =3D { .write =3D allwinner_ahci_mem_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void allwinner_ahci_init(Object *obj) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 00ba422..871b75b 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -521,7 +521,7 @@ static void ahci_mem_write(void *opaque, hwaddr addr, static const MemoryRegionOps ahci_mem_ops =3D { .read =3D ahci_mem_read, .write =3D ahci_mem_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t ahci_idp_read(void *opaque, hwaddr addr, @@ -557,7 +557,7 @@ static void ahci_idp_write(void *opaque, hwaddr addr, static const MemoryRegionOps ahci_idp_ops =3D { .read =3D ahci_idp_read, .write =3D ahci_idp_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 54571fe..b1dbe8d 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -351,7 +351,7 @@ static const MemoryRegionOps pmac_ide_ops =3D { .write =3D pmac_ide_write, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const VMStateDescription vmstate_pmac =3D { diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c index 70a5801..88b71e6 100644 --- a/hw/ide/mmio.c +++ b/hw/ide/mmio.c @@ -84,7 +84,7 @@ static void mmio_ide_write(void *opaque, hwaddr addr, static const MemoryRegionOps mmio_ide_ops =3D { .read =3D mmio_ide_read, .write =3D mmio_ide_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t mmio_ide_status_read(void *opaque, hwaddr addr, @@ -104,7 +104,7 @@ static void mmio_ide_cmd_write(void *opaque, hwaddr add= r, static const MemoryRegionOps mmio_ide_cs_ops =3D { .read =3D mmio_ide_status_read, .write =3D mmio_ide_cmd_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const VMStateDescription vmstate_ide_mmio =3D { diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 4c6fb9a..7cb42f4 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -62,7 +62,7 @@ static void pci_ide_cmd_write(void *opaque, hwaddr addr, const MemoryRegionOps pci_ide_cmd_le_ops =3D { .read =3D pci_ide_cmd_read, .write =3D pci_ide_cmd_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t pci_ide_data_read(void *opaque, hwaddr addr, unsigned size) @@ -100,7 +100,7 @@ static void pci_ide_data_write(void *opaque, hwaddr add= r, const MemoryRegionOps pci_ide_data_le_ops =3D { .read =3D pci_ide_data_read, .write =3D pci_ide_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void bmdma_start_dma(IDEDMA *dma, IDEState *s, @@ -338,7 +338,7 @@ static void bmdma_addr_write(void *opaque, hwaddr addr, MemoryRegionOps bmdma_addr_ioport_ops =3D { .read =3D bmdma_addr_read, .write =3D bmdma_addr_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static bool ide_bmdma_current_needed(void *opaque) diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index d7590d4..30635e1 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -208,7 +208,7 @@ static void sii3112_reg_write(void *opaque, hwaddr addr, static const MemoryRegionOps sii3112_reg_ops =3D { .read =3D sii3112_reg_read, .write =3D sii3112_reg_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; /* the PCI irq level is the logical OR of the two channels */ diff --git a/hw/input/milkymist-softusb.c b/hw/input/milkymist-softusb.c index f779cd4..f4e38f7 100644 --- a/hw/input/milkymist-softusb.c +++ b/hw/input/milkymist-softusb.c @@ -127,7 +127,7 @@ softusb_write(void *opaque, hwaddr addr, uint64_t value, static const MemoryRegionOps softusb_mmio_ops =3D { .read =3D softusb_read, .write =3D softusb_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 47a606f..dd78587 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -456,7 +456,7 @@ static const MemoryRegionOps i8042_mmio_ops =3D { .write =3D kbd_mm_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, @@ -518,7 +518,7 @@ static const MemoryRegionOps i8042_data_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps i8042_cmd_ops =3D { @@ -528,7 +528,7 @@ static const MemoryRegionOps i8042_cmd_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void i8042_initfn(Object *obj) diff --git a/hw/input/pl050.c b/hw/input/pl050.c index b79bf16..a9565ea 100644 --- a/hw/input/pl050.c +++ b/hw/input/pl050.c @@ -137,7 +137,7 @@ static void pl050_write(void *opaque, hwaddr offset, static const MemoryRegionOps pl050_ops =3D { .read =3D pl050_read, .write =3D pl050_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pl050_realize(DeviceState *dev, Error **errp) diff --git a/hw/input/pxa2xx_keypad.c b/hw/input/pxa2xx_keypad.c index 93db9ed..c68f229 100644 --- a/hw/input/pxa2xx_keypad.c +++ b/hw/input/pxa2xx_keypad.c @@ -285,7 +285,7 @@ static void pxa2xx_keypad_write(void *opaque, hwaddr of= fset, static const MemoryRegionOps pxa2xx_keypad_ops =3D { .read =3D pxa2xx_keypad_read, .write =3D pxa2xx_keypad_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_pxa2xx_keypad =3D { diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 080bdd7..bb406e8 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -137,7 +137,7 @@ static void aw_a10_pic_write(void *opaque, hwaddr offse= t, uint64_t value, static const MemoryRegionOps aw_a10_pic_ops =3D { .read =3D aw_a10_pic_read, .write =3D aw_a10_pic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_aw_a10_pic =3D { diff --git a/hw/intc/apic.c b/hw/intc/apic.c index bce8991..6379c66 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -878,7 +878,7 @@ static const MemoryRegionOps apic_io_ops =3D { .impl.max_access_size =3D 4, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void apic_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 77427a4..4d21836 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1999,38 +1999,38 @@ static const MemoryRegionOps gic_ops[2] =3D { { .read_with_attrs =3D gic_dist_read, .write_with_attrs =3D gic_dist_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }, { .read_with_attrs =3D gic_thiscpu_read, .write_with_attrs =3D gic_thiscpu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, } }; static const MemoryRegionOps gic_cpu_ops =3D { .read_with_attrs =3D gic_do_cpu_read, .write_with_attrs =3D gic_do_cpu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const MemoryRegionOps gic_virt_ops[2] =3D { { .read_with_attrs =3D gic_thiscpu_hyp_read, .write_with_attrs =3D gic_thiscpu_hyp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }, { .read_with_attrs =3D gic_thisvcpu_read, .write_with_attrs =3D gic_thisvcpu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, } }; static const MemoryRegionOps gic_viface_ops =3D { .read_with_attrs =3D gic_do_hyp_read, .write_with_attrs =3D gic_do_hyp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void arm_gic_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/arm_gicv2m.c b/hw/intc/arm_gicv2m.c index 05f299f..5906828 100644 --- a/hw/intc/arm_gicv2m.c +++ b/hw/intc/arm_gicv2m.c @@ -126,7 +126,7 @@ static void gicv2m_write(void *opaque, hwaddr offset, static const MemoryRegionOps gicv2m_ops =3D { .read =3D gicv2m_read, .write =3D gicv2m_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void gicv2m_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 66eaa97..e869f16 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -352,12 +352,12 @@ static const MemoryRegionOps gic_ops[] =3D { { .read_with_attrs =3D gicv3_dist_read, .write_with_attrs =3D gicv3_dist_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }, { .read_with_attrs =3D gicv3_redist_read, .write_with_attrs =3D gicv3_redist_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, } }; diff --git a/hw/intc/arm_gicv3_its_common.c b/hw/intc/arm_gicv3_its_common.c index efb3d51..fcbbe6d 100644 --- a/hw/intc/arm_gicv3_its_common.c +++ b/hw/intc/arm_gicv3_its_common.c @@ -95,7 +95,7 @@ static MemTxResult gicv3_its_trans_write(void *opaque, hw= addr offset, static const MemoryRegionOps gicv3_its_trans_ops =3D { .read_with_attrs =3D gicv3_its_trans_read, .write_with_attrs =3D gicv3_its_trans_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void gicv3_its_init_mmio(GICv3ITSState *s, const MemoryRegionOps *ops) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 237ccef..975d7cc 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2334,7 +2334,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, static const MemoryRegionOps nvic_sysreg_ops =3D { .read_with_attrs =3D nvic_sysreg_read, .write_with_attrs =3D nvic_sysreg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, @@ -2381,7 +2381,7 @@ static MemTxResult nvic_sysreg_ns_read(void *opaque, = hwaddr addr, static const MemoryRegionOps nvic_sysreg_ns_ops =3D { .read_with_attrs =3D nvic_sysreg_ns_read, .write_with_attrs =3D nvic_sysreg_ns_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static MemTxResult nvic_systick_write(void *opaque, hwaddr addr, @@ -2412,7 +2412,7 @@ static MemTxResult nvic_systick_read(void *opaque, hw= addr addr, static const MemoryRegionOps nvic_systick_ops =3D { .read_with_attrs =3D nvic_systick_read, .write_with_attrs =3D nvic_systick_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int nvic_post_load(void *opaque, int version_id) diff --git a/hw/intc/aspeed_vic.c b/hw/intc/aspeed_vic.c index 266a309..2556b54 100644 --- a/hw/intc/aspeed_vic.c +++ b/hw/intc/aspeed_vic.c @@ -283,7 +283,7 @@ static void aspeed_vic_write(void *opaque, hwaddr offse= t, uint64_t data, static const MemoryRegionOps aspeed_vic_ops =3D { .read =3D aspeed_vic_read, .write =3D aspeed_vic_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, .valid.unaligned =3D false, diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c index 61d3764..918f46b 100644 --- a/hw/intc/bcm2835_ic.c +++ b/hw/intc/bcm2835_ic.c @@ -168,7 +168,7 @@ static void bcm2835_ic_write(void *opaque, hwaddr offse= t, uint64_t val, static const MemoryRegionOps bcm2835_ic_ops =3D { .read =3D bcm2835_ic_read, .write =3D bcm2835_ic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/intc/bcm2836_control.c b/hw/intc/bcm2836_control.c index 66417c8..14774a7 100644 --- a/hw/intc/bcm2836_control.c +++ b/hw/intc/bcm2836_control.c @@ -302,7 +302,7 @@ static void bcm2836_control_write(void *opaque, hwaddr = offset, static const MemoryRegionOps bcm2836_control_ops =3D { .read =3D bcm2836_control_read, .write =3D bcm2836_control_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/intc/etraxfs_pic.c b/hw/intc/etraxfs_pic.c index 20e1391..9afe1e1 100644 --- a/hw/intc/etraxfs_pic.c +++ b/hw/intc/etraxfs_pic.c @@ -111,7 +111,7 @@ static void pic_write(void *opaque, hwaddr addr, static const MemoryRegionOps pic_ops =3D { .read =3D pic_read, .write =3D pic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c index 6fed0e8..3e7294b 100644 --- a/hw/intc/exynos4210_combiner.c +++ b/hw/intc/exynos4210_combiner.c @@ -401,7 +401,7 @@ static void exynos4210_combiner_reset(DeviceState *d) static const MemoryRegionOps exynos4210_combiner_ops =3D { .read =3D exynos4210_combiner_read, .write =3D exynos4210_combiner_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 21c77a5..3d6002b 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -313,7 +313,7 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr, static const MemoryRegionOps grlib_irqmp_ops =3D { .read =3D grlib_irqmp_read, .write =3D grlib_irqmp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/intc/heathrow_pic.c b/hw/intc/heathrow_pic.c index c282ac4..083be15 100644 --- a/hw/intc/heathrow_pic.c +++ b/hw/intc/heathrow_pic.c @@ -109,7 +109,7 @@ static uint64_t heathrow_read(void *opaque, hwaddr addr, static const MemoryRegionOps heathrow_ops =3D { .read =3D heathrow_read, .write =3D heathrow_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void heathrow_set_irq(void *opaque, int num, int level) diff --git a/hw/intc/imx_avic.c b/hw/intc/imx_avic.c index 83a4101..0ad9f54 100644 --- a/hw/intc/imx_avic.c +++ b/hw/intc/imx_avic.c @@ -308,7 +308,7 @@ static void imx_avic_write(void *opaque, hwaddr offset, static const MemoryRegionOps imx_avic_ops =3D { .read =3D imx_avic_read, .write =3D imx_avic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void imx_avic_reset(DeviceState *dev) diff --git a/hw/intc/imx_gpcv2.c b/hw/intc/imx_gpcv2.c index a83333b..e54b353 100644 --- a/hw/intc/imx_gpcv2.c +++ b/hw/intc/imx_gpcv2.c @@ -64,7 +64,7 @@ static void imx_gpcv2_write(void *opaque, hwaddr offset, static const struct MemoryRegionOps imx_gpcv2_ops =3D { .read =3D imx_gpcv2_read, .write =3D imx_gpcv2_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index e99c37c..1603f4d 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -403,7 +403,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t va= l, static const MemoryRegionOps ioapic_io_ops =3D { .read =3D ioapic_mem_read, .write =3D ioapic_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void ioapic_machine_done_notify(Notifier *notifier, void *data) diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 33ab51c..9d93664 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -385,7 +385,7 @@ static void gic_reset(void *opaque) static const MemoryRegionOps gic_ops =3D { .read =3D gic_read, .write =3D gic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .max_access_size =3D 8, }, diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c index 053e67c..07aa4df 100644 --- a/hw/intc/omap_intc.c +++ b/hw/intc/omap_intc.c @@ -330,7 +330,7 @@ static void omap_inth_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_inth_mem_ops =3D { .read =3D omap_inth_read, .write =3D omap_inth_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -606,7 +606,7 @@ static void omap2_inth_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap2_inth_mem_ops =3D { .read =3D omap2_inth_read, .write =3D omap2_inth_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c index 9cb310a..32c37ce 100644 --- a/hw/intc/ompic.c +++ b/hw/intc/ompic.c @@ -95,7 +95,7 @@ static void ompic_write(void *opaque, hwaddr addr, uint64= _t data, unsigned size) static const MemoryRegionOps ompic_ops =3D { .read =3D ompic_read, .write =3D ompic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .max_access_size =3D 8, }, diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 9b4fc6c..b573202 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -1148,7 +1148,7 @@ static uint64_t openpic_cpu_read(void *opaque, hwaddr= addr, unsigned len) static const MemoryRegionOps openpic_glb_ops_le =3D { .write =3D openpic_gbl_write, .read =3D openpic_gbl_read, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1158,7 +1158,7 @@ static const MemoryRegionOps openpic_glb_ops_le =3D { static const MemoryRegionOps openpic_glb_ops_be =3D { .write =3D openpic_gbl_write, .read =3D openpic_gbl_read, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1168,7 +1168,7 @@ static const MemoryRegionOps openpic_glb_ops_be =3D { static const MemoryRegionOps openpic_tmr_ops_le =3D { .write =3D openpic_tmr_write, .read =3D openpic_tmr_read, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1178,7 +1178,7 @@ static const MemoryRegionOps openpic_tmr_ops_le =3D { static const MemoryRegionOps openpic_tmr_ops_be =3D { .write =3D openpic_tmr_write, .read =3D openpic_tmr_read, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1188,7 +1188,7 @@ static const MemoryRegionOps openpic_tmr_ops_be =3D { static const MemoryRegionOps openpic_cpu_ops_le =3D { .write =3D openpic_cpu_write, .read =3D openpic_cpu_read, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1198,7 +1198,7 @@ static const MemoryRegionOps openpic_cpu_ops_le =3D { static const MemoryRegionOps openpic_cpu_ops_be =3D { .write =3D openpic_cpu_write, .read =3D openpic_cpu_read, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1208,7 +1208,7 @@ static const MemoryRegionOps openpic_cpu_ops_be =3D { static const MemoryRegionOps openpic_src_ops_le =3D { .write =3D openpic_src_write, .read =3D openpic_src_read, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1218,7 +1218,7 @@ static const MemoryRegionOps openpic_src_ops_le =3D { static const MemoryRegionOps openpic_src_ops_be =3D { .write =3D openpic_src_write, .read =3D openpic_src_read, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1228,7 +1228,7 @@ static const MemoryRegionOps openpic_src_ops_be =3D { static const MemoryRegionOps openpic_msi_ops_be =3D { .read =3D openpic_msi_read, .write =3D openpic_msi_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1238,7 +1238,7 @@ static const MemoryRegionOps openpic_msi_ops_be =3D { static const MemoryRegionOps openpic_summary_ops_be =3D { .read =3D openpic_summary_read, .write =3D openpic_summary_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/intc/openpic_kvm.c b/hw/intc/openpic_kvm.c index 49fc6fa..4581121 100644 --- a/hw/intc/openpic_kvm.c +++ b/hw/intc/openpic_kvm.c @@ -109,7 +109,7 @@ static uint64_t kvm_openpic_read(void *opaque, hwaddr a= ddr, unsigned size) static const MemoryRegionOps kvm_openpic_mem_ops =3D { .write =3D kvm_openpic_write, .read =3D kvm_openpic_read, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/intc/pl190.c b/hw/intc/pl190.c index b4f31ef..2dbe29d 100644 --- a/hw/intc/pl190.c +++ b/hw/intc/pl190.c @@ -220,7 +220,7 @@ static void pl190_write(void *opaque, hwaddr offset, static const MemoryRegionOps pl190_ops =3D { .read =3D pl190_read, .write =3D pl190_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pl190_reset(DeviceState *d) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 4dc92ef..edea170 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -1186,7 +1186,7 @@ static uint64_t pnv_xive_ic_reg_read(void *opaque, hw= addr offset, unsigned size) static const MemoryRegionOps pnv_xive_ic_reg_ops =3D { .read =3D pnv_xive_ic_reg_read, .write =3D pnv_xive_ic_reg_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -1285,7 +1285,7 @@ static uint64_t pnv_xive_ic_notify_read(void *opaque,= hwaddr addr, static const MemoryRegionOps pnv_xive_ic_notify_ops =3D { .read =3D pnv_xive_ic_notify_read, .write =3D pnv_xive_ic_notify_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -1319,7 +1319,7 @@ static uint64_t pnv_xive_ic_lsi_read(void *opaque, hw= addr addr, unsigned size) static const MemoryRegionOps pnv_xive_ic_lsi_ops =3D { .read =3D pnv_xive_ic_lsi_read, .write =3D pnv_xive_ic_lsi_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -1384,7 +1384,7 @@ static uint64_t xive_tm_indirect_read(void *opaque, h= waddr offset, static const MemoryRegionOps xive_tm_indirect_ops =3D { .read =3D xive_tm_indirect_read, .write =3D xive_tm_indirect_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 8, @@ -1418,7 +1418,7 @@ static void pnv_xive_xscom_write(void *opaque, hwaddr= addr, static const MemoryRegionOps pnv_xive_xscom_ops =3D { .read =3D pnv_xive_xscom_read, .write =3D pnv_xive_xscom_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -1514,7 +1514,7 @@ static void pnv_xive_vc_write(void *opaque, hwaddr of= fset, static const MemoryRegionOps pnv_xive_vc_ops =3D { .read =3D pnv_xive_vc_read, .write =3D pnv_xive_vc_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -1549,7 +1549,7 @@ static void pnv_xive_pc_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps pnv_xive_pc_ops =3D { .read =3D pnv_xive_pc_read, .write =3D pnv_xive_pc_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, diff --git a/hw/intc/puv3_intc.c b/hw/intc/puv3_intc.c index e2f6d98..670899a 100644 --- a/hw/intc/puv3_intc.c +++ b/hw/intc/puv3_intc.c @@ -100,7 +100,7 @@ static const MemoryRegionOps puv3_intc_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void puv3_intc_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/sh_intc.c b/hw/intc/sh_intc.c index bac7886..3bf8868 100644 --- a/hw/intc/sh_intc.c +++ b/hw/intc/sh_intc.c @@ -289,7 +289,7 @@ static void sh_intc_write(void *opaque, hwaddr offset, static const MemoryRegionOps sh_intc_ops =3D { .read =3D sh_intc_read, .write =3D sh_intc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id) diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c index ca52875..5a09e8b 100644 --- a/hw/intc/slavio_intctl.c +++ b/hw/intc/slavio_intctl.c @@ -134,7 +134,7 @@ static void slavio_intctl_mem_writel(void *opaque, hwad= dr addr, static const MemoryRegionOps slavio_intctl_mem_ops =3D { .read =3D slavio_intctl_mem_readl, .write =3D slavio_intctl_mem_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -204,7 +204,7 @@ static void slavio_intctlm_mem_writel(void *opaque, hwa= ddr addr, static const MemoryRegionOps slavio_intctlm_mem_ops =3D { .read =3D slavio_intctlm_mem_readl, .write =3D slavio_intctlm_mem_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/intc/xics_pnv.c b/hw/intc/xics_pnv.c index 67f2702..7acd6ec 100644 --- a/hw/intc/xics_pnv.c +++ b/hw/intc/xics_pnv.c @@ -149,7 +149,7 @@ bad_access: static const MemoryRegionOps pnv_icp_ops =3D { .read =3D pnv_icp_read, .write =3D pnv_icp_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index d5363e9..61034d9 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -142,7 +142,7 @@ pic_write(void *opaque, hwaddr addr, static const MemoryRegionOps pic_ops =3D { .read =3D pic_read, .write =3D pic_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/intc/xive.c b/hw/intc/xive.c index cf77bdb..e2a0802 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -479,7 +479,7 @@ static uint64_t xive_tm_read(void *opaque, hwaddr offse= t, unsigned size) const MemoryRegionOps xive_tm_ops =3D { .read =3D xive_tm_read, .write =3D xive_tm_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 8, @@ -950,7 +950,7 @@ out: static const MemoryRegionOps xive_source_esb_ops =3D { .read =3D xive_source_esb_read, .write =3D xive_source_esb_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -1645,7 +1645,7 @@ static void xive_end_source_write(void *opaque, hwadd= r addr, static const MemoryRegionOps xive_end_source_ops =3D { .read =3D xive_end_source_read, .write =3D xive_end_source_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, diff --git a/hw/intc/xlnx-pmu-iomod-intc.c b/hw/intc/xlnx-pmu-iomod-intc.c index 0b8ff89..c4bab81 100644 --- a/hw/intc/xlnx-pmu-iomod-intc.c +++ b/hw/intc/xlnx-pmu-iomod-intc.c @@ -464,7 +464,7 @@ static void xlnx_pmu_io_intc_reset(DeviceState *dev) static const MemoryRegionOps xlnx_pmu_io_intc_ops =3D { .read =3D register_read_memory, .write =3D register_write_memory, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/intc/xlnx-zynqmp-ipi.c b/hw/intc/xlnx-zynqmp-ipi.c index 0dad6c0..7ac94bb 100644 --- a/hw/intc/xlnx-zynqmp-ipi.c +++ b/hw/intc/xlnx-zynqmp-ipi.c @@ -295,7 +295,7 @@ static void xlnx_zynqmp_obs_handler(void *opaque, int n= , int level) static const MemoryRegionOps xlnx_zynqmp_ipi_ops =3D { .read =3D register_read_memory, .write =3D register_write_memory, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/ipack/tpci200.c b/hw/ipack/tpci200.c index d4d8510..8bf866c 100644 --- a/hw/ipack/tpci200.c +++ b/hw/ipack/tpci200.c @@ -524,7 +524,7 @@ static void tpci200_write_las3(void *opaque, hwaddr add= r, uint64_t val, static const MemoryRegionOps tpci200_cfg_ops =3D { .read =3D tpci200_read_cfg, .write =3D tpci200_write_cfg, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4 @@ -538,7 +538,7 @@ static const MemoryRegionOps tpci200_cfg_ops =3D { static const MemoryRegionOps tpci200_las0_ops =3D { .read =3D tpci200_read_las0, .write =3D tpci200_write_las0, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 2, .max_access_size =3D 2 @@ -548,7 +548,7 @@ static const MemoryRegionOps tpci200_las0_ops =3D { static const MemoryRegionOps tpci200_las1_ops =3D { .read =3D tpci200_read_las1, .write =3D tpci200_write_las1, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 2 @@ -558,7 +558,7 @@ static const MemoryRegionOps tpci200_las1_ops =3D { static const MemoryRegionOps tpci200_las2_ops =3D { .read =3D tpci200_read_las2, .write =3D tpci200_write_las2, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 2 @@ -568,7 +568,7 @@ static const MemoryRegionOps tpci200_las2_ops =3D { static const MemoryRegionOps tpci200_las3_ops =3D { .read =3D tpci200_read_las3, .write =3D tpci200_write_las3, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1 diff --git a/hw/ipmi/isa_ipmi_bt.c b/hw/ipmi/isa_ipmi_bt.c index 1846d5b..4fefbcf 100644 --- a/hw/ipmi/isa_ipmi_bt.c +++ b/hw/ipmi/isa_ipmi_bt.c @@ -320,7 +320,7 @@ static const MemoryRegionOps ipmi_bt_io_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ipmi_bt_set_atn(IPMIInterface *ii, int val, int irq) diff --git a/hw/ipmi/isa_ipmi_kcs.c b/hw/ipmi/isa_ipmi_kcs.c index 068f341..2671fdc 100644 --- a/hw/ipmi/isa_ipmi_kcs.c +++ b/hw/ipmi/isa_ipmi_kcs.c @@ -313,7 +313,7 @@ const MemoryRegionOps ipmi_kcs_io_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ipmi_kcs_set_atn(IPMIInterface *ii, int val, int irq) diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index a7081bd..1a9e66e 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -569,7 +569,7 @@ static void ich9_lpc_reset(DeviceState *qdev) static const MemoryRegionOps rcrb_mmio_ops =3D { .read =3D ich9_cc_read, .write =3D ich9_cc_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ich9_lpc_machine_ready(Notifier *n, void *opaque) @@ -620,7 +620,7 @@ static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr = addr, unsigned len) static const MemoryRegionOps ich9_rst_cnt_ops =3D { .read =3D ich9_rst_cnt_read, .write =3D ich9_rst_cnt_write, - .endianness =3D DEVICE_LITTLE_ENDIAN + .endianness =3D MO_LE }; static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name, diff --git a/hw/isa/pc87312.c b/hw/isa/pc87312.c index 85dbc94..8718b2d 100644 --- a/hw/isa/pc87312.c +++ b/hw/isa/pc87312.c @@ -265,7 +265,7 @@ static uint64_t pc87312_io_read(void *opaque, hwaddr ad= dr, unsigned int size) static const MemoryRegionOps pc87312_io_ops =3D { .read =3D pc87312_io_read, .write =3D pc87312_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 12c460590..4281928 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -108,7 +108,7 @@ static uint64_t superio_ioport_readb(void *opaque, hwad= dr addr, unsigned size) static const MemoryRegionOps superio_ops =3D { .read =3D superio_ioport_readb, .write =3D superio_ioport_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index 1c17f83..1b7712e 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -548,7 +548,7 @@ static const MemoryRegionOps m5206_mbar_ops =3D { .write =3D m5206_mbar_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, M68kCPU *cpu) diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 6f6efae..7fdeb16 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -138,7 +138,7 @@ static uint64_t m5208_timer_read(void *opaque, hwaddr a= ddr, static const MemoryRegionOps m5208_timer_ops =3D { .read =3D m5208_timer_read, .write =3D m5208_timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t m5208_sys_read(void *opaque, hwaddr addr, @@ -172,7 +172,7 @@ static void m5208_sys_write(void *opaque, hwaddr addr, static const MemoryRegionOps m5208_sys_ops =3D { .read =3D m5208_sys_read, .write =3D m5208_sys_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c index a613aed..c38a347 100644 --- a/hw/m68k/mcf_intc.c +++ b/hw/m68k/mcf_intc.c @@ -159,7 +159,7 @@ static void mcf_intc_reset(DeviceState *dev) static const MemoryRegionOps mcf_intc_ops =3D { .read =3D mcf_intc_read, .write =3D mcf_intc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void mcf_intc_instance_init(Object *obj) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_= ml605_mmu.c index a88bf16..857c659 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -122,7 +122,7 @@ petalogix_ml605_init(MachineState *machine) serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2, irq[UART16550_IRQ], 115200, serial_hd(0), - DEVICE_LITTLE_ENDIAN); + MO_LE); /* 2 timers at irq 2 @ 100 Mhz. */ dev =3D qdev_create(NULL, "xlnx.xps-timer"); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 9eeccbe..89babaa 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -165,7 +165,7 @@ static void boston_lcd_write(void *opaque, hwaddr addr, static const MemoryRegionOps boston_lcd_ops =3D { .read =3D boston_lcd_read, .write =3D boston_lcd_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t boston_platreg_read(void *opaque, hwaddr addr, @@ -244,7 +244,7 @@ static void boston_platreg_write(void *opaque, hwaddr a= ddr, static const MemoryRegionOps boston_platreg_ops =3D { .read =3D boston_platreg_read, .write =3D boston_platreg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const TypeInfo boston_device =3D { @@ -504,7 +504,7 @@ static void boston_mach_init(MachineState *machine) s->uart =3D serial_mm_init(sys_mem, 0x17ffe000, 2, get_cps_irq(&s->cps, 3), 10000000, - serial_hd(0), DEVICE_NATIVE_ENDIAN); + serial_hd(0), MO_TE); lcd =3D g_new(MemoryRegion, 1); memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8= ); diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 2fa313f..7ed4d5c 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -972,7 +972,7 @@ static uint64_t gt64120_readl(void *opaque, static const MemoryRegionOps isd_mem_ops =3D { .read =3D gt64120_readl, .write =3D gt64120_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index fa8775d..397c96e 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -84,7 +84,7 @@ static void rtc_write(void *opaque, hwaddr addr, static const MemoryRegionOps rtc_ops =3D { .read =3D rtc_read, .write =3D rtc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t dma_dummy_read(void *opaque, hwaddr addr, @@ -105,7 +105,7 @@ static void dma_dummy_write(void *opaque, hwaddr addr, static const MemoryRegionOps dma_dummy_ops =3D { .read =3D dma_dummy_read, .write =3D dma_dummy_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; #define MAGNUM_BIOS_SIZE_MAX 0x7e000 @@ -320,12 +320,12 @@ static void mips_jazz_init(MachineState *machine, if (serial_hd(0)) { serial_mm_init(address_space, 0x80006000, 0, qdev_get_gpio_in(rc4030, 8), 8000000/16, - serial_hd(0), DEVICE_NATIVE_ENDIAN); + serial_hd(0), MO_TE); } if (serial_hd(1)) { serial_mm_init(address_space, 0x80007000, 0, qdev_get_gpio_in(rc4030, 9), 8000000/16, - serial_hd(1), DEVICE_NATIVE_ENDIAN); + serial_hd(1), MO_TE); } /* Parallel port */ diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 20e019b..efb6690 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -511,7 +511,7 @@ static void malta_fpga_write(void *opaque, hwaddr addr, static const MemoryRegionOps malta_fpga_ops =3D { .read =3D malta_fpga_read, .write =3D malta_fpga_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void malta_fpga_reset(void *opaque) @@ -572,7 +572,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *ad= dress_space, malta_fgpa_display_event, NULL, s, NULL, true= ); s->uart =3D serial_mm_init(address_space, base + 0x900, 3, uart_irq, - 230400, uart_chr, DEVICE_NATIVE_ENDIAN); + 230400, uart_chr, MO_TE); malta_fpga_reset(s); qemu_register_reset(malta_fpga_reset, s); diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 93dbf76..a013ac7 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -70,7 +70,7 @@ static uint64_t mips_qemu_read (void *opaque, hwaddr addr, static const MemoryRegionOps mips_qemu_ops =3D { .read =3D mips_qemu_read, .write =3D mips_qemu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; typedef struct ResetData { diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c index 4307f00..a750f0a 100644 --- a/hw/misc/a9scu.c +++ b/hw/misc/a9scu.c @@ -94,7 +94,7 @@ static void a9_scu_write(void *opaque, hwaddr offset, static const MemoryRegionOps a9_scu_ops =3D { .read =3D a9_scu_read, .write =3D a9_scu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void a9_scu_reset(DeviceState *dev) diff --git a/hw/misc/applesmc.c b/hw/misc/applesmc.c index 2d7eb3c..a577b9e 100644 --- a/hw/misc/applesmc.c +++ b/hw/misc/applesmc.c @@ -285,7 +285,7 @@ static void qdev_applesmc_isa_reset(DeviceState *dev) static const MemoryRegionOps applesmc_data_io_ops =3D { .write =3D applesmc_io_data_write, .read =3D applesmc_io_data_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -295,7 +295,7 @@ static const MemoryRegionOps applesmc_data_io_ops =3D { static const MemoryRegionOps applesmc_cmd_io_ops =3D { .write =3D applesmc_io_cmd_write, .read =3D applesmc_io_cmd_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -305,7 +305,7 @@ static const MemoryRegionOps applesmc_cmd_io_ops =3D { static const MemoryRegionOps applesmc_err_io_ops =3D { .write =3D applesmc_io_err_write, .read =3D applesmc_io_err_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/misc/arm11scu.c b/hw/misc/arm11scu.c index 84275df..cc7b21e 100644 --- a/hw/misc/arm11scu.c +++ b/hw/misc/arm11scu.c @@ -57,7 +57,7 @@ static void mpcore_scu_write(void *opaque, hwaddr offset, static const MemoryRegionOps mpcore_scu_ops =3D { .read =3D mpcore_scu_read, .write =3D mpcore_scu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void arm11_scu_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/arm_integrator_debug.c b/hw/misc/arm_integrator_debug.c index 2646107..917fe1f 100644 --- a/hw/misc/arm_integrator_debug.c +++ b/hw/misc/arm_integrator_debug.c @@ -73,7 +73,7 @@ static void intdbg_control_write(void *opaque, hwaddr off= set, static const MemoryRegionOps intdbg_control_ops =3D { .read =3D intdbg_control_read, .write =3D intdbg_control_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void intdbg_control_init(Object *obj) diff --git a/hw/misc/arm_l2x0.c b/hw/misc/arm_l2x0.c index b88f40a..b071920 100644 --- a/hw/misc/arm_l2x0.c +++ b/hw/misc/arm_l2x0.c @@ -157,7 +157,7 @@ static void l2x0_priv_reset(DeviceState *dev) static const MemoryRegionOps l2x0_mem_ops =3D { .read =3D l2x0_priv_read, .write =3D l2x0_priv_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void l2x0_priv_init(Object *obj) diff --git a/hw/misc/arm_sysctl.c b/hw/misc/arm_sysctl.c index 457dfad..736a708 100644 --- a/hw/misc/arm_sysctl.c +++ b/hw/misc/arm_sysctl.c @@ -561,7 +561,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offse= t, static const MemoryRegionOps arm_sysctl_ops =3D { .read =3D arm_sysctl_read, .write =3D arm_sysctl_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void arm_sysctl_gpio_set(void *opaque, int line, int level) diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c index 05c08f3..3da0f02 100644 --- a/hw/misc/armsse-cpuid.c +++ b/hw/misc/armsse-cpuid.c @@ -84,7 +84,7 @@ static void armsse_cpuid_write(void *opaque, hwaddr offse= t, static const MemoryRegionOps armsse_cpuid_ops =3D { .read =3D armsse_cpuid_read, .write =3D armsse_cpuid_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, /* byte/halfword accesses are just zero-padded on reads and writes */ .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c index 514321a..b57f892 100644 --- a/hw/misc/armsse-mhu.c +++ b/hw/misc/armsse-mhu.c @@ -139,7 +139,7 @@ static void armsse_mhu_write(void *opaque, hwaddr offse= t, static const MemoryRegionOps armsse_mhu_ops =3D { .read =3D armsse_mhu_read, .write =3D armsse_mhu_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 71a0d4b..fca5fe5 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -276,7 +276,7 @@ static void aspeed_scu_write(void *opaque, hwaddr offse= t, uint64_t data, static const MemoryRegionOps aspeed_scu_ops =3D { .read =3D aspeed_scu_read, .write =3D aspeed_scu_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, .valid.unaligned =3D false, diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index b84676d..6444afb 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -169,7 +169,7 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr= , uint64_t data, static const MemoryRegionOps aspeed_sdmc_ops =3D { .read =3D aspeed_sdmc_read, .write =3D aspeed_sdmc_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c index eebd4ad..3568a40 100644 --- a/hw/misc/aspeed_xdma.c +++ b/hw/misc/aspeed_xdma.c @@ -106,7 +106,7 @@ static void aspeed_xdma_write(void *opaque, hwaddr addr= , uint64_t val, static const MemoryRegionOps aspeed_xdma_ops =3D { .read =3D aspeed_xdma_read, .write =3D aspeed_xdma_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/misc/bcm2835_mbox.c b/hw/misc/bcm2835_mbox.c index a87da5e..0e19b3f 100644 --- a/hw/misc/bcm2835_mbox.c +++ b/hw/misc/bcm2835_mbox.c @@ -237,7 +237,7 @@ static void bcm2835_mbox_write(void *opaque, hwaddr off= set, static const MemoryRegionOps bcm2835_mbox_ops =3D { .read =3D bcm2835_mbox_read, .write =3D bcm2835_mbox_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index 0bf789c..0085902 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -343,7 +343,7 @@ static void bcm2835_property_write(void *opaque, hwaddr= offset, static const MemoryRegionOps bcm2835_property_ops =3D { .read =3D bcm2835_property_read, .write =3D bcm2835_property_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/misc/bcm2835_rng.c b/hw/misc/bcm2835_rng.c index e882c87..8e0b329 100644 --- a/hw/misc/bcm2835_rng.c +++ b/hw/misc/bcm2835_rng.c @@ -91,7 +91,7 @@ static void bcm2835_rng_write(void *opaque, hwaddr offset, static const MemoryRegionOps bcm2835_rng_ops =3D { .read =3D bcm2835_rng_read, .write =3D bcm2835_rng_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_bcm2835_rng =3D { diff --git a/hw/misc/debugexit.c b/hw/misc/debugexit.c index 8e4a2fc..c34960e 100644 --- a/hw/misc/debugexit.c +++ b/hw/misc/debugexit.c @@ -40,7 +40,7 @@ static const MemoryRegionOps debug_exit_ops =3D { .write =3D debug_exit_write, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void debug_exit_realizefn(DeviceState *d, Error **errp) diff --git a/hw/misc/eccmemctl.c b/hw/misc/eccmemctl.c index 8386db0..f01b397 100644 --- a/hw/misc/eccmemctl.c +++ b/hw/misc/eccmemctl.c @@ -228,7 +228,7 @@ static uint64_t ecc_mem_read(void *opaque, hwaddr addr, static const MemoryRegionOps ecc_mem_ops =3D { .read =3D ecc_mem_read, .write =3D ecc_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -257,7 +257,7 @@ static uint64_t ecc_diag_mem_read(void *opaque, hwaddr = addr, static const MemoryRegionOps ecc_diag_mem_ops =3D { .read =3D ecc_diag_mem_read, .write =3D ecc_diag_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/misc/edu.c b/hw/misc/edu.c index 3b6dba2..73252d0 100644 --- a/hw/misc/edu.c +++ b/hw/misc/edu.c @@ -294,7 +294,7 @@ static void edu_mmio_write(void *opaque, hwaddr addr, u= int64_t val, static const MemoryRegionOps edu_mmio_ops =3D { .read =3D edu_mmio_read, .write =3D edu_mmio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 8, diff --git a/hw/misc/exynos4210_clk.c b/hw/misc/exynos4210_clk.c index 821d9ea..b83bb88 100644 --- a/hw/misc/exynos4210_clk.c +++ b/hw/misc/exynos4210_clk.c @@ -100,7 +100,7 @@ static void exynos4210_clk_write(void *opaque, hwaddr o= ffset, static const MemoryRegionOps exynos4210_clk_ops =3D { .read =3D exynos4210_clk_read, .write =3D exynos4210_clk_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/misc/exynos4210_pmu.c b/hw/misc/exynos4210_pmu.c index 8712774..75617f9 100644 --- a/hw/misc/exynos4210_pmu.c +++ b/hw/misc/exynos4210_pmu.c @@ -457,7 +457,7 @@ static void exynos4210_pmu_write(void *opaque, hwaddr o= ffset, static const MemoryRegionOps exynos4210_pmu_ops =3D { .read =3D exynos4210_pmu_read, .write =3D exynos4210_pmu_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/misc/exynos4210_rng.c b/hw/misc/exynos4210_rng.c index b88fe3a..644f647 100644 --- a/hw/misc/exynos4210_rng.c +++ b/hw/misc/exynos4210_rng.c @@ -215,7 +215,7 @@ static void exynos4210_rng_write(void *opaque, hwaddr o= ffset, static const MemoryRegionOps exynos4210_rng_ops =3D { .read =3D exynos4210_rng_read, .write =3D exynos4210_rng_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void exynos4210_rng_reset(DeviceState *dev) diff --git a/hw/misc/grlib_ahb_apb_pnp.c b/hw/misc/grlib_ahb_apb_pnp.c index 7338461..a85624e 100644 --- a/hw/misc/grlib_ahb_apb_pnp.c +++ b/hw/misc/grlib_ahb_apb_pnp.c @@ -137,7 +137,7 @@ static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr= offset, unsigned size) static const MemoryRegionOps grlib_ahb_pnp_ops =3D { .read =3D grlib_ahb_pnp_read, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp) @@ -233,7 +233,7 @@ static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr= offset, unsigned size) static const MemoryRegionOps grlib_apb_pnp_ops =3D { .read =3D grlib_apb_pnp_read, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void grlib_apb_pnp_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c index 693ea81..9a7fbe7 100644 --- a/hw/misc/imx25_ccm.c +++ b/hw/misc/imx25_ccm.c @@ -266,7 +266,7 @@ static void imx25_ccm_write(void *opaque, hwaddr offset= , uint64_t value, static const struct MemoryRegionOps imx25_ccm_ops =3D { .read =3D imx25_ccm_read, .write =3D imx25_ccm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/misc/imx2_wdt.c b/hw/misc/imx2_wdt.c index 5576778..07e97a2 100644 --- a/hw/misc/imx2_wdt.c +++ b/hw/misc/imx2_wdt.c @@ -37,7 +37,7 @@ static void imx2_wdt_write(void *opaque, hwaddr addr, static const MemoryRegionOps imx2_wdt_ops =3D { .read =3D imx2_wdt_read, .write =3D imx2_wdt_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c index 38a19aa..08a5969 100644 --- a/hw/misc/imx31_ccm.c +++ b/hw/misc/imx31_ccm.c @@ -292,7 +292,7 @@ static void imx31_ccm_write(void *opaque, hwaddr offset= , uint64_t value, static const struct MemoryRegionOps imx31_ccm_ops =3D { .read =3D imx31_ccm_read, .write =3D imx31_ccm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c index 9478007..e93f4a1 100644 --- a/hw/misc/imx6_ccm.c +++ b/hw/misc/imx6_ccm.c @@ -696,7 +696,7 @@ static void imx6_analog_write(void *opaque, hwaddr offs= et, uint64_t value, static const struct MemoryRegionOps imx6_ccm_ops =3D { .read =3D imx6_ccm_read, .write =3D imx6_ccm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { /* * Our device would not work correctly if the guest was doing @@ -713,7 +713,7 @@ static const struct MemoryRegionOps imx6_ccm_ops =3D { static const struct MemoryRegionOps imx6_analog_ops =3D { .read =3D imx6_analog_read, .write =3D imx6_analog_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c index 878ffcd..85f40ac 100644 --- a/hw/misc/imx6_src.c +++ b/hw/misc/imx6_src.c @@ -262,7 +262,7 @@ static void imx6_src_write(void *opaque, hwaddr offset,= uint64_t value, static const struct MemoryRegionOps imx6_src_ops =3D { .read =3D imx6_src_read, .write =3D imx6_src_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c index 37b472d..88acb69 100644 --- a/hw/misc/imx6ul_ccm.c +++ b/hw/misc/imx6ul_ccm.c @@ -801,7 +801,7 @@ static void imx6ul_analog_write(void *opaque, hwaddr of= fset, uint64_t value, static const struct MemoryRegionOps imx6ul_ccm_ops =3D { .read =3D imx6ul_ccm_read, .write =3D imx6ul_ccm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { /* * Our device would not work correctly if the guest was doing @@ -818,7 +818,7 @@ static const struct MemoryRegionOps imx6ul_ccm_ops =3D { static const struct MemoryRegionOps imx6ul_analog_ops =3D { .read =3D imx6ul_analog_read, .write =3D imx6ul_analog_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c index d9bdcf1..3305316 100644 --- a/hw/misc/imx7_ccm.c +++ b/hw/misc/imx7_ccm.c @@ -116,7 +116,7 @@ static void imx7_set_clr_tog_write(void *opaque, hwaddr= offset, static const struct MemoryRegionOps imx7_set_clr_tog_ops =3D { .read =3D imx7_set_clr_tog_read, .write =3D imx7_set_clr_tog_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { /* * Our device would not work correctly if the guest was doing @@ -132,7 +132,7 @@ static const struct MemoryRegionOps imx7_set_clr_tog_op= s =3D { static const struct MemoryRegionOps imx7_digprog_ops =3D { .read =3D imx7_set_clr_tog_read, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/misc/imx7_gpr.c b/hw/misc/imx7_gpr.c index 09d57d4..3cb144b 100644 --- a/hw/misc/imx7_gpr.c +++ b/hw/misc/imx7_gpr.c @@ -79,7 +79,7 @@ static void imx7_gpr_write(void *opaque, hwaddr offset, static const struct MemoryRegionOps imx7_gpr_ops =3D { .read =3D imx7_gpr_read, .write =3D imx7_gpr_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c index 55b962a..373d586 100644 --- a/hw/misc/imx7_snvs.c +++ b/hw/misc/imx7_snvs.c @@ -37,7 +37,7 @@ static void imx7_snvs_write(void *opaque, hwaddr offset, static const struct MemoryRegionOps imx7_snvs_ops =3D { .read =3D imx7_snvs_read, .write =3D imx7_snvs_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 58fd94b..7cb1424 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -560,7 +560,7 @@ static MemTxResult iotkit_secctl_ns_write(void *opaque,= hwaddr addr, static const MemoryRegionOps iotkit_secctl_s_ops =3D { .read_with_attrs =3D iotkit_secctl_s_read, .write_with_attrs =3D iotkit_secctl_s_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, @@ -570,7 +570,7 @@ static const MemoryRegionOps iotkit_secctl_s_ops =3D { static const MemoryRegionOps iotkit_secctl_ns_ops =3D { .read_with_attrs =3D iotkit_secctl_ns_read, .write_with_attrs =3D iotkit_secctl_ns_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 00d4faa..6969a18 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -388,7 +388,7 @@ static void iotkit_sysctl_write(void *opaque, hwaddr of= fset, static const MemoryRegionOps iotkit_sysctl_ops =3D { .read =3D iotkit_sysctl_read, .write =3D iotkit_sysctl_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, /* byte/halfword accesses are just zero-padded on reads and writes */ .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index 3e1cf0e..7f4133f 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -88,7 +88,7 @@ static void iotkit_sysinfo_write(void *opaque, hwaddr off= set, static const MemoryRegionOps iotkit_sysinfo_ops =3D { .read =3D iotkit_sysinfo_read, .write =3D iotkit_sysinfo_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, /* byte/halfword accesses are just zero-padded on reads and writes */ .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index f9cc66a..bc69cd7 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -275,7 +275,7 @@ static uint64_t ivshmem_io_read(void *opaque, hwaddr ad= dr, static const MemoryRegionOps ivshmem_mmio_ops =3D { .read =3D ivshmem_io_read, .write =3D ivshmem_io_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 4f532ef..ad6d6b5 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -477,7 +477,7 @@ static void mos6522_cuda_write(void *opaque, hwaddr add= r, uint64_t val, static const MemoryRegionOps mos6522_cuda_ops =3D { .read =3D mos6522_cuda_read, .write =3D mos6522_cuda_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/misc/macio/gpio.c b/hw/misc/macio/gpio.c index 31811ab..c4c9a68 100644 --- a/hw/misc/macio/gpio.c +++ b/hw/misc/macio/gpio.c @@ -144,7 +144,7 @@ static uint64_t macio_gpio_read(void *opaque, hwaddr ad= dr, unsigned size) static const MemoryRegionOps macio_gpio_ops =3D { .read =3D macio_gpio_read, .write =3D macio_gpio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c index 548625a..4554b28 100644 --- a/hw/misc/macio/mac_dbdma.c +++ b/hw/misc/macio/mac_dbdma.c @@ -793,7 +793,7 @@ static uint64_t dbdma_read(void *opaque, hwaddr addr, static const MemoryRegionOps dbdma_ops =3D { .read =3D dbdma_read, .write =3D dbdma_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 8249209..693bb26 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -284,7 +284,7 @@ static uint64_t timer_read(void *opaque, hwaddr addr, u= nsigned size) static const MemoryRegionOps timer_ops =3D { .read =3D timer_read, .write =3D timer_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void macio_newworld_realize(PCIDevice *d, Error **errp) diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 753561d..fb0d132 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -664,7 +664,7 @@ static void mos6522_pmu_write(void *opaque, hwaddr addr= , uint64_t val, static const MemoryRegionOps mos6522_pmu_ops =3D { .read =3D mos6522_pmu_read, .write =3D mos6522_pmu_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/misc/milkymist-hpdmc.c b/hw/misc/milkymist-hpdmc.c index 701c79e..33ecefb 100644 --- a/hw/misc/milkymist-hpdmc.c +++ b/hw/misc/milkymist-hpdmc.c @@ -113,7 +113,7 @@ static const MemoryRegionOps hpdmc_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void milkymist_hpdmc_reset(DeviceState *d) diff --git a/hw/misc/milkymist-pfpu.c b/hw/misc/milkymist-pfpu.c index 1c27f1a..e7c777b 100644 --- a/hw/misc/milkymist-pfpu.c +++ b/hw/misc/milkymist-pfpu.c @@ -475,7 +475,7 @@ static const MemoryRegionOps pfpu_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void milkymist_pfpu_reset(DeviceState *d) diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c index edec164..f09cf1f 100644 --- a/hw/misc/mips_cmgcr.c +++ b/hw/misc/mips_cmgcr.c @@ -170,7 +170,7 @@ static void gcr_write(void *opaque, hwaddr addr, uint64= _t data, unsigned size) static const MemoryRegionOps gcr_ops =3D { .read =3D gcr_read, .write =3D gcr_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .max_access_size =3D 8, }, diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index 446b1ad..2244ee4 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips_cpc.c @@ -111,7 +111,7 @@ static uint64_t cpc_read(void *opaque, hwaddr offset, u= nsigned size) static const MemoryRegionOps cpc_ops =3D { .read =3D cpc_read, .write =3D cpc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .max_access_size =3D 8, }, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index e8ba4a3..7369d7c 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -141,7 +141,7 @@ static const MemoryRegionOps itc_tag_ops =3D { .impl =3D { .max_access_size =3D 8, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static inline uint32_t get_num_cells(MIPSITUState *s) @@ -482,7 +482,7 @@ static void itc_storage_write(void *opaque, hwaddr addr= , uint64_t data, static const MemoryRegionOps itc_storage_ops =3D { .read =3D itc_storage_read, .write =3D itc_storage_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void itc_reset_cells(MIPSITUState *s) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index e72ed69..60f4208 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -364,7 +364,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t = val, unsigned size) static const MemoryRegionOps mos6522_ops =3D { .read =3D mos6522_read, .write =3D mos6522_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index b97ad42..7d894e4 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -220,7 +220,7 @@ static void mps2_fpgaio_write(void *opaque, hwaddr offs= et, uint64_t value, static const MemoryRegionOps mps2_fpgaio_ops =3D { .read =3D mps2_fpgaio_read, .write =3D mps2_fpgaio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void mps2_fpgaio_reset(DeviceState *dev) diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 1fdf5d2..9a089e3 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -215,7 +215,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset,= uint64_t value, static const MemoryRegionOps mps2_scc_ops =3D { .read =3D mps2_scc_read, .write =3D mps2_scc_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void mps2_scc_reset(DeviceState *dev) diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c index 21a2863..33282dc 100644 --- a/hw/misc/msf2-sysreg.c +++ b/hw/misc/msf2-sysreg.c @@ -94,7 +94,7 @@ static void msf2_sysreg_write(void *opaque, hwaddr offset, static const MemoryRegionOps sysreg_ops =3D { .read =3D msf2_sysreg_read, .write =3D msf2_sysreg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void msf2_sysreg_init(Object *obj) diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c index fd18303..db26d16 100644 --- a/hw/misc/mst_fpga.c +++ b/hw/misc/mst_fpga.c @@ -191,7 +191,7 @@ mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t val= ue, static const MemoryRegionOps mst_fpga_ops =3D { .read =3D mst_fpga_readb, .write =3D mst_fpga_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int mst_fpga_post_load(void *opaque, int version_id) diff --git a/hw/misc/nrf51_rng.c b/hw/misc/nrf51_rng.c index 96ef433..9614446 100644 --- a/hw/misc/nrf51_rng.c +++ b/hw/misc/nrf51_rng.c @@ -137,7 +137,7 @@ static void rng_write(void *opaque, hwaddr offset, static const MemoryRegionOps rng_ops =3D { .read =3D rng_read, .write =3D rng_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4 }; diff --git a/hw/misc/omap_gpmc.c b/hw/misc/omap_gpmc.c index 84f9e4c..00da920 100644 --- a/hw/misc/omap_gpmc.c +++ b/hw/misc/omap_gpmc.c @@ -212,7 +212,7 @@ static void omap_nand_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_nand_ops =3D { .read =3D omap_nand_read, .write =3D omap_nand_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void fill_prefetch_fifo(struct omap_gpmc_s *s) @@ -369,7 +369,7 @@ static void omap_gpmc_prefetch_write(void *opaque, hwad= dr addr, static const MemoryRegionOps omap_prefetch_ops =3D { .read =3D omap_gpmc_prefetch_read, .write =3D omap_gpmc_prefetch_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl.min_access_size =3D 1, .impl.max_access_size =3D 1, }; @@ -819,7 +819,7 @@ static void omap_gpmc_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_gpmc_ops =3D { .read =3D omap_gpmc_read, .write =3D omap_gpmc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, diff --git a/hw/misc/omap_l4.c b/hw/misc/omap_l4.c index c217728..c09cbad 100644 --- a/hw/misc/omap_l4.c +++ b/hw/misc/omap_l4.c @@ -107,7 +107,7 @@ static void omap_l4ta_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_l4ta_ops =3D { .read =3D omap_l4ta_read, .write =3D omap_l4ta_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, diff --git a/hw/misc/omap_sdrc.c b/hw/misc/omap_sdrc.c index 7b38c55..f9863de 100644 --- a/hw/misc/omap_sdrc.c +++ b/hw/misc/omap_sdrc.c @@ -152,7 +152,7 @@ static void omap_sdrc_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_sdrc_ops =3D { .read =3D omap_sdrc_read, .write =3D omap_sdrc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, diff --git a/hw/misc/omap_tap.c b/hw/misc/omap_tap.c index 3f595e8..d005ac2 100644 --- a/hw/misc/omap_tap.c +++ b/hw/misc/omap_tap.c @@ -106,7 +106,7 @@ static void omap_tap_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_tap_ops =3D { .read =3D omap_tap_read, .write =3D omap_tap_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void omap_tap_init(struct omap_target_agent_s *ta, diff --git a/hw/misc/pc-testdev.c b/hw/misc/pc-testdev.c index 1f9abd5..34a9227 100644 --- a/hw/misc/pc-testdev.c +++ b/hw/misc/pc-testdev.c @@ -78,7 +78,7 @@ static const MemoryRegionOps test_irq_ops =3D { .write =3D test_irq_line_write, .valid.min_access_size =3D 1, .valid.max_access_size =3D 1, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void test_ioport_write(void *opaque, hwaddr addr, uint64_t data, @@ -104,7 +104,7 @@ static uint64_t test_ioport_read(void *opaque, hwaddr a= ddr, unsigned len) static const MemoryRegionOps test_ioport_ops =3D { .read =3D test_ioport_read, .write =3D test_ioport_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps test_ioport_byte_ops =3D { @@ -114,7 +114,7 @@ static const MemoryRegionOps test_ioport_byte_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 1, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t test_flush_page_read(void *opaque, hwaddr addr, unsigned s= ize) @@ -142,7 +142,7 @@ static const MemoryRegionOps test_flush_ops =3D { .write =3D test_flush_page_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t test_iomem_read(void *opaque, hwaddr addr, unsigned len) @@ -165,7 +165,7 @@ static void test_iomem_write(void *opaque, hwaddr addr,= uint64_t val, static const MemoryRegionOps test_iomem_ops =3D { .read =3D test_iomem_read, .write =3D test_iomem_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void testdev_realizefn(DeviceState *d, Error **errp) diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c index d4d89df..ee9c575 100644 --- a/hw/misc/pci-testdev.c +++ b/hw/misc/pci-testdev.c @@ -222,7 +222,7 @@ pci_testdev_pio_write(void *opaque, hwaddr addr, uint64= _t val, static const MemoryRegionOps pci_testdev_mmio_ops =3D { .read =3D pci_testdev_read, .write =3D pci_testdev_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -232,7 +232,7 @@ static const MemoryRegionOps pci_testdev_mmio_ops =3D { static const MemoryRegionOps pci_testdev_pio_ops =3D { .read =3D pci_testdev_read, .write =3D pci_testdev_pio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/misc/puv3_pm.c b/hw/misc/puv3_pm.c index b538b4a..f9a13dd 100644 --- a/hw/misc/puv3_pm.c +++ b/hw/misc/puv3_pm.c @@ -118,7 +118,7 @@ static const MemoryRegionOps puv3_pm_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void puv3_pm_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/slavio_misc.c b/hw/misc/slavio_misc.c index 9c2cf04..bbff86f 100644 --- a/hw/misc/slavio_misc.c +++ b/hw/misc/slavio_misc.c @@ -142,7 +142,7 @@ static uint64_t slavio_cfg_mem_readb(void *opaque, hwad= dr addr, static const MemoryRegionOps slavio_cfg_mem_ops =3D { .read =3D slavio_cfg_mem_readb, .write =3D slavio_cfg_mem_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -172,7 +172,7 @@ static uint64_t slavio_diag_mem_readb(void *opaque, hwa= ddr addr, static const MemoryRegionOps slavio_diag_mem_ops =3D { .read =3D slavio_diag_mem_readb, .write =3D slavio_diag_mem_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -202,7 +202,7 @@ static uint64_t slavio_mdm_mem_readb(void *opaque, hwad= dr addr, static const MemoryRegionOps slavio_mdm_mem_ops =3D { .read =3D slavio_mdm_mem_readb, .write =3D slavio_mdm_mem_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -240,7 +240,7 @@ static uint64_t slavio_aux1_mem_readb(void *opaque, hwa= ddr addr, static const MemoryRegionOps slavio_aux1_mem_ops =3D { .read =3D slavio_aux1_mem_readb, .write =3D slavio_aux1_mem_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -277,7 +277,7 @@ static uint64_t slavio_aux2_mem_readb(void *opaque, hwa= ddr addr, static const MemoryRegionOps slavio_aux2_mem_ops =3D { .read =3D slavio_aux2_mem_readb, .write =3D slavio_aux2_mem_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -305,7 +305,7 @@ static uint64_t apc_mem_readb(void *opaque, hwaddr addr, static const MemoryRegionOps apc_mem_ops =3D { .read =3D apc_mem_readb, .write =3D apc_mem_writeb, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -350,7 +350,7 @@ static void slavio_sysctrl_mem_writel(void *opaque, hwa= ddr addr, static const MemoryRegionOps slavio_sysctrl_mem_ops =3D { .read =3D slavio_sysctrl_mem_readl, .write =3D slavio_sysctrl_mem_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -392,7 +392,7 @@ static void slavio_led_mem_writew(void *opaque, hwaddr = addr, static const MemoryRegionOps slavio_led_mem_ops =3D { .read =3D slavio_led_mem_readw, .write =3D slavio_led_mem_writew, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 2, .max_access_size =3D 2, diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c index aa59b43..1efe7e2 100644 --- a/hw/misc/stm32f2xx_syscfg.c +++ b/hw/misc/stm32f2xx_syscfg.c @@ -126,7 +126,7 @@ static void stm32f2xx_syscfg_write(void *opaque, hwaddr= addr, static const MemoryRegionOps stm32f2xx_syscfg_ops =3D { .read =3D stm32f2xx_syscfg_read, .write =3D stm32f2xx_syscfg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void stm32f2xx_syscfg_init(Object *obj) diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index 45a3e31..2924fc2 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -332,7 +332,7 @@ static MemTxResult tz_mpc_reg_write(void *opaque, hwadd= r addr, static const MemoryRegionOps tz_mpc_reg_ops =3D { .read_with_attrs =3D tz_mpc_reg_read, .write_with_attrs =3D tz_mpc_reg_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, @@ -408,7 +408,7 @@ static MemTxResult tz_mpc_mem_blocked_write(void *opaqu= e, hwaddr addr, static const MemoryRegionOps tz_mpc_mem_blocked_ops =3D { .read_with_attrs =3D tz_mpc_mem_blocked_read, .write_with_attrs =3D tz_mpc_mem_blocked_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 1, .valid.max_access_size =3D 8, .impl.min_access_size =3D 1, diff --git a/hw/misc/tz-msc.c b/hw/misc/tz-msc.c index 52b96ba..bf68480 100644 --- a/hw/misc/tz-msc.c +++ b/hw/misc/tz-msc.c @@ -206,7 +206,7 @@ static MemTxResult tz_msc_write(void *opaque, hwaddr ad= dr, uint64_t val, static const MemoryRegionOps tz_msc_ops =3D { .read_with_attrs =3D tz_msc_read, .write_with_attrs =3D tz_msc_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void tz_msc_reset(DeviceState *dev) diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c index 2a14a26..fd2bb07 100644 --- a/hw/misc/tz-ppc.c +++ b/hw/misc/tz-ppc.c @@ -179,7 +179,7 @@ static MemTxResult tz_ppc_write(void *opaque, hwaddr ad= dr, uint64_t val, static const MemoryRegionOps tz_ppc_ops =3D { .read_with_attrs =3D tz_ppc_read, .write_with_attrs =3D tz_ppc_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static bool tz_ppc_dummy_accepts(void *opaque, hwaddr addr, diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c index 7f8e42c..2991bce 100644 --- a/hw/misc/unimp.c +++ b/hw/misc/unimp.c @@ -47,7 +47,7 @@ static const MemoryRegionOps unimp_ops =3D { .impl.max_access_size =3D 8, .valid.min_access_size =3D 1, .valid.max_access_size =3D 8, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void unimp_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/zynq-xadc.c b/hw/misc/zynq-xadc.c index f1e4860..1fefac4 100644 --- a/hw/misc/zynq-xadc.c +++ b/hw/misc/zynq-xadc.c @@ -251,7 +251,7 @@ static void zynq_xadc_write(void *opaque, hwaddr offset= , uint64_t val, static const MemoryRegionOps xadc_ops =3D { .read =3D zynq_xadc_read, .write =3D zynq_xadc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void zynq_xadc_init(Object *obj) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 6b51ae5..75a01d0 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -415,7 +415,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, static const MemoryRegionOps slcr_ops =3D { .read =3D zynq_slcr_read, .write =3D zynq_slcr_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void zynq_slcr_init(Object *obj) diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c index d771d39..be6888c 100644 --- a/hw/moxie/moxiesim.c +++ b/hw/moxie/moxiesim.c @@ -141,7 +141,7 @@ static void moxiesim_init(MachineState *machine) /* A single 16450 sits at offset 0x3f8. */ if (serial_hd(0)) { serial_mm_init(address_space_mem, 0x3f8, 0, env->irq[4], - 8000000/16, serial_hd(0), DEVICE_LITTLE_ENDIAN); + 8000000 / 16, serial_hd(0), MO_LE); } } diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index eecda52..fe02b4b 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -418,7 +418,7 @@ static void aw_emac_set_link(NetClientState *nc) static const MemoryRegionOps aw_emac_mem_ops =3D { .read =3D aw_emac_read, .write =3D aw_emac_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index d412085..fb00600 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1515,7 +1515,7 @@ static void gem_write(void *opaque, hwaddr offset, ui= nt64_t val, static const MemoryRegionOps gem_ops =3D { .read =3D gem_read, .write =3D gem_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void gem_set_link(NetClientState *nc) diff --git a/hw/net/can/can_kvaser_pci.c b/hw/net/can/can_kvaser_pci.c index df639f8..8661c17 100644 --- a/hw/net/can/can_kvaser_pci.c +++ b/hw/net/can/can_kvaser_pci.c @@ -190,7 +190,7 @@ static void kvaser_pci_xilinx_io_write(void *opaque, hw= addr addr, uint64_t data, static const MemoryRegionOps kvaser_pci_s5920_io_ops =3D { .read =3D kvaser_pci_s5920_io_read, .write =3D kvaser_pci_s5920_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -200,7 +200,7 @@ static const MemoryRegionOps kvaser_pci_s5920_io_ops = =3D { static const MemoryRegionOps kvaser_pci_sja_io_ops =3D { .read =3D kvaser_pci_sja_io_read, .write =3D kvaser_pci_sja_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .max_access_size =3D 1, }, @@ -209,7 +209,7 @@ static const MemoryRegionOps kvaser_pci_sja_io_ops =3D { static const MemoryRegionOps kvaser_pci_xilinx_io_ops =3D { .read =3D kvaser_pci_xilinx_io_read, .write =3D kvaser_pci_xilinx_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .max_access_size =3D 1, }, diff --git a/hw/net/can/can_mioe3680_pci.c b/hw/net/can/can_mioe3680_pci.c index 7af0993..013dae3 100644 --- a/hw/net/can/can_mioe3680_pci.c +++ b/hw/net/can/can_mioe3680_pci.c @@ -135,7 +135,7 @@ static void mioe3680_pci_sja2_io_write(void *opaque, hw= addr addr, uint64_t data, static const MemoryRegionOps mioe3680_pci_sja1_io_ops =3D { .read =3D mioe3680_pci_sja1_io_read, .write =3D mioe3680_pci_sja1_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .max_access_size =3D 1, }, @@ -144,7 +144,7 @@ static const MemoryRegionOps mioe3680_pci_sja1_io_ops = =3D { static const MemoryRegionOps mioe3680_pci_sja2_io_ops =3D { .read =3D mioe3680_pci_sja2_io_read, .write =3D mioe3680_pci_sja2_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .max_access_size =3D 1, }, diff --git a/hw/net/can/can_pcm3680_pci.c b/hw/net/can/can_pcm3680_pci.c index 3f7312a..2207b5b 100644 --- a/hw/net/can/can_pcm3680_pci.c +++ b/hw/net/can/can_pcm3680_pci.c @@ -135,7 +135,7 @@ static void pcm3680i_pci_sja2_io_write(void *opaque, hw= addr addr, uint64_t data, static const MemoryRegionOps pcm3680i_pci_sja1_io_ops =3D { .read =3D pcm3680i_pci_sja1_io_read, .write =3D pcm3680i_pci_sja1_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .max_access_size =3D 1, }, @@ -144,7 +144,7 @@ static const MemoryRegionOps pcm3680i_pci_sja1_io_ops = =3D { static const MemoryRegionOps pcm3680i_pci_sja2_io_ops =3D { .read =3D pcm3680i_pci_sja2_io_read, .write =3D pcm3680i_pci_sja2_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .max_access_size =3D 1, }, diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index bdb0b3b..b5c191c 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -651,7 +651,7 @@ static const MemoryRegionOps dp8393x_ops =3D { .write =3D dp8393x_write, .impl.min_access_size =3D 2, .impl.max_access_size =3D 2, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void dp8393x_watchdog(void *opaque) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index a023ceb..4605407 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -1341,7 +1341,7 @@ e1000_mmio_read(void *opaque, hwaddr addr, unsigned s= ize) static const MemoryRegionOps e1000_mmio_ops =3D { .read =3D e1000_mmio_read, .write =3D e1000_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1368,7 +1368,7 @@ static void e1000_io_write(void *opaque, hwaddr addr, static const MemoryRegionOps e1000_io_ops =3D { .read =3D e1000_io_read, .write =3D e1000_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static bool is_version_1(void *opaque, int version_id) diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 581f7d0..abcd6d3 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -179,7 +179,7 @@ e1000e_io_write(void *opaque, hwaddr addr, static const MemoryRegionOps mmio_ops =3D { .read =3D e1000e_mmio_read, .write =3D e1000e_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -189,7 +189,7 @@ static const MemoryRegionOps mmio_ops =3D { static const MemoryRegionOps io_ops =3D { .read =3D e1000e_io_read, .write =3D e1000e_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 6607c91..b0d3265 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -1601,7 +1601,7 @@ static void eepro100_write(void *opaque, hwaddr addr, static const MemoryRegionOps eepro100_ops =3D { .read =3D eepro100_read, .write =3D eepro100_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t= size) diff --git a/hw/net/etraxfs_eth.c b/hw/net/etraxfs_eth.c index 4cfbf11..f748f5e 100644 --- a/hw/net/etraxfs_eth.c +++ b/hw/net/etraxfs_eth.c @@ -569,7 +569,7 @@ static void eth_set_link(NetClientState *nc) static const MemoryRegionOps eth_ops =3D { .read =3D eth_read, .write =3D eth_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index 2a8b99a..9e5f1cb 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -281,7 +281,7 @@ static void etsec_write(void *opaque, static const MemoryRegionOps etsec_ops =3D { .read =3D etsec_read, .write =3D etsec_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index d2cded5..6d0d6a4 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -979,7 +979,7 @@ static const MemoryRegionOps ftgmac100_ops =3D { .write =3D ftgmac100_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ftgmac100_cleanup(NetClientState *nc) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 404154e..eaf73ef 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1278,7 +1278,7 @@ static const MemoryRegionOps imx_eth_ops =3D { .write =3D imx_eth_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void imx_eth_cleanup(NetClientState *nc) diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index f6120be..f9b6801 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -1304,13 +1304,13 @@ static uint64_t lan9118_16bit_mode_read(void *opaqu= e, hwaddr offset, static const MemoryRegionOps lan9118_mem_ops =3D { .read =3D lan9118_readl, .write =3D lan9118_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const MemoryRegionOps lan9118_16bit_mem_ops =3D { .read =3D lan9118_16bit_mode_read, .write =3D lan9118_16bit_mode_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static NetClientInfo net_lan9118_info =3D { diff --git a/hw/net/lance.c b/hw/net/lance.c index 2978c01..662e444 100644 --- a/hw/net/lance.c +++ b/hw/net/lance.c @@ -74,7 +74,7 @@ static uint64_t lance_mem_read(void *opaque, hwaddr addr, static const MemoryRegionOps lance_mem_ops =3D { .read =3D lance_mem_read, .write =3D lance_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 2, .max_access_size =3D 2, diff --git a/hw/net/mcf_fec.c b/hw/net/mcf_fec.c index 78468fa..bf37375 100644 --- a/hw/net/mcf_fec.c +++ b/hw/net/mcf_fec.c @@ -624,7 +624,7 @@ static ssize_t mcf_fec_receive(NetClientState *nc, cons= t uint8_t *buf, size_t si static const MemoryRegionOps mcf_fec_ops =3D { .read =3D mcf_fec_read, .write =3D mcf_fec_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static NetClientInfo net_mcf_fec_info =3D { diff --git a/hw/net/milkymist-minimac2.c b/hw/net/milkymist-minimac2.c index 41ef7a4..40aee51 100644 --- a/hw/net/milkymist-minimac2.c +++ b/hw/net/milkymist-minimac2.c @@ -431,7 +431,7 @@ static const MemoryRegionOps minimac2_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void milkymist_minimac2_reset(DeviceState *d) diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c index 1cf4b57..8fe407b 100644 --- a/hw/net/ne2000.c +++ b/hw/net/ne2000.c @@ -686,7 +686,7 @@ static void ne2000_write(void *opaque, hwaddr addr, static const MemoryRegionOps ne2000_ops =3D { .read =3D ne2000_read, .write =3D ne2000_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; /***********************************************************/ diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c index 600d09c..41bfa37 100644 --- a/hw/net/pcnet-pci.c +++ b/hw/net/pcnet-pci.c @@ -137,7 +137,7 @@ static void pcnet_ioport_write(void *opaque, hwaddr add= r, static const MemoryRegionOps pcnet_io_ops =3D { .read =3D pcnet_ioport_read, .write =3D pcnet_ioport_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const VMStateDescription vmstate_pci_pcnet =3D { @@ -160,7 +160,7 @@ static const MemoryRegionOps pcnet_mmio_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void pci_physical_memory_write(void *dma_opaque, hwaddr addr, diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c index bd54612..2fe64db 100644 --- a/hw/net/rocker/rocker.c +++ b/hw/net/rocker/rocker.c @@ -1196,7 +1196,7 @@ static uint64_t rocker_mmio_read(void *opaque, hwaddr= addr, unsigned size) static const MemoryRegionOps rocker_mmio_ops =3D { .read =3D rocker_mmio_read, .write =3D rocker_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 8, diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c index 0927317..f51bc7c 100644 --- a/hw/net/rtl8139.c +++ b/hw/net/rtl8139.c @@ -3311,7 +3311,7 @@ static const MemoryRegionOps rtl8139_io_ops =3D { .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void rtl8139_timer(void *opaque) diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c index 4a612ee..f7d53bf 100644 --- a/hw/net/smc91c111.c +++ b/hw/net/smc91c111.c @@ -757,7 +757,7 @@ static const MemoryRegionOps smc91c111_mem_ops =3D { .write =3D smc91c111_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static NetClientInfo net_smc91c111_info =3D { diff --git a/hw/net/stellaris_enet.c b/hw/net/stellaris_enet.c index 2f645bf..aac322d 100644 --- a/hw/net/stellaris_enet.c +++ b/hw/net/stellaris_enet.c @@ -456,7 +456,7 @@ static void stellaris_enet_write(void *opaque, hwaddr o= ffset, static const MemoryRegionOps stellaris_enet_ops =3D { .read =3D stellaris_enet_read, .write =3D stellaris_enet_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void stellaris_enet_reset(DeviceState *dev) diff --git a/hw/net/sungem.c b/hw/net/sungem.c index 89bcf74..549fd2d 100644 --- a/hw/net/sungem.c +++ b/hw/net/sungem.c @@ -924,7 +924,7 @@ static uint64_t sungem_mmio_greg_read(void *opaque, hwa= ddr addr, unsigned size) static const MemoryRegionOps sungem_mmio_greg_ops =3D { .read =3D sungem_mmio_greg_read, .write =3D sungem_mmio_greg_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -993,7 +993,7 @@ static uint64_t sungem_mmio_txdma_read(void *opaque, hw= addr addr, unsigned size) static const MemoryRegionOps sungem_mmio_txdma_ops =3D { .read =3D sungem_mmio_txdma_read, .write =3D sungem_mmio_txdma_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1066,7 +1066,7 @@ static uint64_t sungem_mmio_rxdma_read(void *opaque, = hwaddr addr, unsigned size) static const MemoryRegionOps sungem_mmio_rxdma_ops =3D { .read =3D sungem_mmio_rxdma_read, .write =3D sungem_mmio_rxdma_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1163,7 +1163,7 @@ static uint64_t sungem_mmio_mac_read(void *opaque, hw= addr addr, unsigned size) static const MemoryRegionOps sungem_mmio_mac_ops =3D { .read =3D sungem_mmio_mac_read, .write =3D sungem_mmio_mac_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1229,7 +1229,7 @@ static uint64_t sungem_mmio_mif_read(void *opaque, hw= addr addr, unsigned size) static const MemoryRegionOps sungem_mmio_mif_ops =3D { .read =3D sungem_mmio_mif_read, .write =3D sungem_mmio_mif_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1284,7 +1284,7 @@ static uint64_t sungem_mmio_pcs_read(void *opaque, hw= addr addr, unsigned size) static const MemoryRegionOps sungem_mmio_pcs_ops =3D { .read =3D sungem_mmio_pcs_read, .write =3D sungem_mmio_pcs_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/net/sunhme.c b/hw/net/sunhme.c index 8b8603e..2df010d 100644 --- a/hw/net/sunhme.c +++ b/hw/net/sunhme.c @@ -287,7 +287,7 @@ static uint64_t sunhme_seb_read(void *opaque, hwaddr ad= dr, static const MemoryRegionOps sunhme_seb_ops =3D { .read =3D sunhme_seb_read, .write =3D sunhme_seb_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -330,7 +330,7 @@ static uint64_t sunhme_etx_read(void *opaque, hwaddr ad= dr, static const MemoryRegionOps sunhme_etx_ops =3D { .read =3D sunhme_etx_read, .write =3D sunhme_etx_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -363,7 +363,7 @@ static uint64_t sunhme_erx_read(void *opaque, hwaddr ad= dr, static const MemoryRegionOps sunhme_erx_ops =3D { .read =3D sunhme_erx_read, .write =3D sunhme_erx_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -406,7 +406,7 @@ static uint64_t sunhme_mac_read(void *opaque, hwaddr ad= dr, static const MemoryRegionOps sunhme_mac_ops =3D { .read =3D sunhme_mac_read, .write =3D sunhme_mac_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -528,7 +528,7 @@ static uint64_t sunhme_mif_read(void *opaque, hwaddr ad= dr, static const MemoryRegionOps sunhme_mif_ops =3D { .read =3D sunhme_mif_read, .write =3D sunhme_mif_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index 10d01d0..cc64b91 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -2159,7 +2159,7 @@ vmxnet3_msix_load(QEMUFile *f, void *opaque, int vers= ion_id) static const MemoryRegionOps b0_ops =3D { .read =3D vmxnet3_io_bar0_read, .write =3D vmxnet3_io_bar0_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -2169,7 +2169,7 @@ static const MemoryRegionOps b0_ops =3D { static const MemoryRegionOps b1_ops =3D { .read =3D vmxnet3_io_bar1_read, .write =3D vmxnet3_io_bar1_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/net/xgmac.c b/hw/net/xgmac.c index f49df95..edcc4b2 100644 --- a/hw/net/xgmac.c +++ b/hw/net/xgmac.c @@ -309,7 +309,7 @@ static void enet_write(void *opaque, hwaddr addr, static const MemoryRegionOps enet_mem_ops =3D { .read =3D enet_read, .write =3D enet_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static int eth_can_rx(XgmacState *s) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index feeaca6..4df665f 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -661,7 +661,7 @@ static void enet_write(void *opaque, hwaddr addr, static const MemoryRegionOps enet_ops =3D { .read =3D enet_read, .write =3D enet_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static int eth_can_rx(XilinxAXIEnet *s) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 8f3a8f8..e1fb6b8 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -167,7 +167,7 @@ eth_write(void *opaque, hwaddr addr, static const MemoryRegionOps eth_ops =3D { .read =3D eth_read, .write =3D eth_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 2c3388f..112fe40 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -91,7 +91,7 @@ static void nios2_10m50_ghrd_init(MachineState *machine) /* Register: Altera 16550 UART */ serial_mm_init(address_space_mem, 0xf8001600, 2, irq[1], 115200, - serial_hd(0), DEVICE_NATIVE_ENDIAN); + serial_hd(0), MO_TE); /* Register: Timer sys_clk_timer */ dev =3D qdev_create(NULL, "ALTR.timer"); diff --git a/hw/nvram/ds1225y.c b/hw/nvram/ds1225y.c index fd49283..7afeffa 100644 --- a/hw/nvram/ds1225y.c +++ b/hw/nvram/ds1225y.c @@ -69,7 +69,7 @@ static const MemoryRegionOps nvram_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static int nvram_post_load(void *opaque, int version_id) diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index dcfd6d2..438e8d4 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -523,14 +523,14 @@ static bool fw_cfg_comb_valid(void *opaque, hwaddr ad= dr, static const MemoryRegionOps fw_cfg_ctl_mem_ops =3D { .read =3D fw_cfg_ctl_mem_read, .write =3D fw_cfg_ctl_mem_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid.accepts =3D fw_cfg_ctl_mem_valid, }; static const MemoryRegionOps fw_cfg_data_mem_ops =3D { .read =3D fw_cfg_data_read, .write =3D fw_cfg_data_mem_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -541,14 +541,14 @@ static const MemoryRegionOps fw_cfg_data_mem_ops =3D { static const MemoryRegionOps fw_cfg_comb_mem_ops =3D { .read =3D fw_cfg_data_read, .write =3D fw_cfg_comb_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.accepts =3D fw_cfg_comb_valid, }; static const MemoryRegionOps fw_cfg_dma_mem_ops =3D { .read =3D fw_cfg_dma_mem_read, .write =3D fw_cfg_dma_mem_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid.accepts =3D fw_cfg_dma_mem_valid, .valid.max_access_size =3D 8, .impl.max_access_size =3D 8, diff --git a/hw/nvram/mac_nvram.c b/hw/nvram/mac_nvram.c index a60426c..028d167 100644 --- a/hw/nvram/mac_nvram.c +++ b/hw/nvram/mac_nvram.c @@ -76,7 +76,7 @@ static const MemoryRegionOps macio_nvram_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 1, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static const VMStateDescription vmstate_macio_nvram =3D { diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c index eca0cb3..557b1d1 100644 --- a/hw/nvram/nrf51_nvm.c +++ b/hw/nvram/nrf51_nvm.c @@ -96,7 +96,7 @@ static const MemoryRegionOps ficr_ops =3D { .write =3D ficr_write, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN + .endianness =3D MO_LE }; /* @@ -189,7 +189,7 @@ static const MemoryRegionOps uicr_ops =3D { .write =3D uicr_write, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN + .endianness =3D MO_LE }; @@ -268,7 +268,7 @@ static const MemoryRegionOps io_ops =3D { .write =3D io_write, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; @@ -301,7 +301,7 @@ static const MemoryRegionOps flash_ops =3D { .write =3D flash_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void nrf51_nvm_init(Object *obj) diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index b85f0df..e0de12b 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -164,7 +164,7 @@ static void openrisc_sim_init(MachineState *machine) } serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, - 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); + 115200, serial_hd(0), MO_TE); openrisc_load_kernel(ram_size, kernel_filename); } diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index dde4437..1625118 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -311,7 +311,7 @@ static uint64_t bonito_readl(void *opaque, hwaddr addr, static const MemoryRegionOps bonito_ops =3D { .read =3D bonito_readl, .write =3D bonito_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -344,7 +344,7 @@ static uint64_t bonito_pciconf_readl(void *opaque, hwad= dr addr, static const MemoryRegionOps bonito_pciconf_ops =3D { .read =3D bonito_pciconf_readl, .write =3D bonito_pciconf_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -381,7 +381,7 @@ static void bonito_ldma_writel(void *opaque, hwaddr add= r, static const MemoryRegionOps bonito_ldma_ops =3D { .read =3D bonito_ldma_readl, .write =3D bonito_ldma_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -418,7 +418,7 @@ static void bonito_cop_writel(void *opaque, hwaddr addr, static const MemoryRegionOps bonito_cop_ops =3D { .read =3D bonito_cop_readl, .write =3D bonito_cop_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -524,7 +524,7 @@ static const MemoryRegionOps bonito_spciconf_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; #define BONITO_IRQ_BASE 32 diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 9ae8c0d..bf3ff13 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -75,7 +75,7 @@ static void designware_pcie_root_msi_write(void *opaque, = hwaddr addr, static const MemoryRegionOps designware_pci_host_msi_ops =3D { .write =3D designware_pcie_root_msi_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -235,7 +235,7 @@ static void designware_pcie_root_data_write(void *opaqu= e, hwaddr addr, static const MemoryRegionOps designware_pci_host_conf_ops =3D { .read =3D designware_pcie_root_data_read, .write =3D designware_pcie_root_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, @@ -620,7 +620,7 @@ static void designware_pcie_host_mmio_write(void *opaqu= e, hwaddr addr, static const MemoryRegionOps designware_pci_mmio_ops =3D { .read =3D designware_pcie_host_mmio_read, .write =3D designware_pcie_host_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index d9c70f7..c817fa5 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -691,7 +691,7 @@ static uint64_t rcr_read(void *opaque, hwaddr addr, uns= igned len) static const MemoryRegionOps rcr_ops =3D { .read =3D rcr_read, .write =3D rcr_write, - .endianness =3D DEVICE_LITTLE_ENDIAN + .endianness =3D MO_LE }; static void piix3_realize(PCIDevice *dev, Error **errp) diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 21eaa30..4c19008 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -338,7 +338,7 @@ static void pci_reg_write4(void *opaque, hwaddr addr, static const MemoryRegionOps e500_pci_reg_ops =3D { .read =3D pci_reg_read4, .write =3D pci_reg_write4, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index c564f23..bf94693 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -108,7 +108,7 @@ static uint64_t raven_pci_io_read(void *opaque, hwaddr = addr, static const MemoryRegionOps raven_pci_io_ops =3D { .read =3D raven_pci_io_read, .write =3D raven_pci_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t raven_intack_read(void *opaque, hwaddr addr, @@ -186,7 +186,7 @@ static void raven_io_write(void *opaque, hwaddr addr, static const MemoryRegionOps raven_io_ops =3D { .read =3D raven_io_read, .write =3D raven_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl.max_access_size =3D 4, .valid.unaligned =3D true, }; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 0a010be..27f39eb 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -288,12 +288,12 @@ static void tseg_blackhole_write(void *opaque, hwaddr= addr, uint64_t val, static const MemoryRegionOps tseg_blackhole_ops =3D { .read =3D tseg_blackhole_read, .write =3D tseg_blackhole_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; /* PCIe MMCFG */ diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index 2cec111..de12397 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -247,7 +247,7 @@ static uint64_t sabre_config_read(void *opaque, static const MemoryRegionOps sabre_config_ops =3D { .read =3D sabre_config_read, .write =3D sabre_config_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void sabre_pci_config_write(void *opaque, hwaddr addr, @@ -368,7 +368,7 @@ static void sabre_reset(DeviceState *d) static const MemoryRegionOps pci_config_ops =3D { .read =3D sabre_pci_config_read, .write =3D sabre_pci_config_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void sabre_realize(DeviceState *dev, Error **errp) diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c index 680fefd..0a51d2b 100644 --- a/hw/pci-host/uninorth.c +++ b/hw/pci-host/uninorth.c @@ -108,7 +108,7 @@ static uint64_t unin_data_read(void *opaque, hwaddr add= r, static const MemoryRegionOps unin_data_ops =3D { .read =3D unin_data_read, .write =3D unin_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void pci_unin_init_irqs(UNINHostState *s) @@ -564,7 +564,7 @@ static uint64_t unin_read(void *opaque, hwaddr addr, un= signed size) static const MemoryRegionOps unin_ops =3D { .read =3D unin_read, .write =3D unin_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void unin_init(Object *obj) diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c index 791b321..1310f0c 100644 --- a/hw/pci-host/versatile.c +++ b/hw/pci-host/versatile.c @@ -240,7 +240,7 @@ static uint64_t pci_vpb_reg_read(void *opaque, hwaddr a= ddr, static const MemoryRegionOps pci_vpb_reg_ops =3D { .read =3D pci_vpb_reg_read, .write =3D pci_vpb_reg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -306,7 +306,7 @@ static uint64_t pci_vpb_config_read(void *opaque, hwadd= r addr, static const MemoryRegionOps pci_vpb_config_ops =3D { .read =3D pci_vpb_config_read, .write =3D pci_vpb_config_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int pci_vpb_map_irq(PCIDevice *d, int irq_num) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index d39dcf3..e9acb1e 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -195,7 +195,7 @@ static void msix_table_mmio_write(void *opaque, hwaddr = addr, static const MemoryRegionOps msix_table_mmio_ops =3D { .read =3D msix_table_mmio_read, .write =3D msix_table_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -223,7 +223,7 @@ static void msix_pba_mmio_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps msix_pba_mmio_ops =3D { .read =3D msix_pba_mmio_read, .write =3D msix_pba_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index c5f9244..fc1b837 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -190,25 +190,25 @@ static uint64_t pci_host_data_read(void *opaque, const MemoryRegionOps pci_host_conf_le_ops =3D { .read =3D pci_host_config_read, .write =3D pci_host_config_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; const MemoryRegionOps pci_host_conf_be_ops =3D { .read =3D pci_host_config_read, .write =3D pci_host_config_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; const MemoryRegionOps pci_host_data_le_ops =3D { .read =3D pci_host_data_read, .write =3D pci_host_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; const MemoryRegionOps pci_host_data_be_ops =3D { .read =3D pci_host_data_read, .write =3D pci_host_data_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static const TypeInfo pci_host_type_info =3D { diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index d6768b8..5e120dc 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -72,7 +72,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque, static const MemoryRegionOps pcie_mmcfg_ops =3D { .read =3D pcie_mmcfg_data_read, .write =3D pcie_mmcfg_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void pcie_host_init(Object *obj) diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index 5a10c6e..6c56edb 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -477,7 +477,7 @@ static void shpc_mmio_write(void *opaque, hwaddr addr, static const MemoryRegionOps shpc_mmio_ops =3D { .read =3D shpc_mmio_read, .write =3D shpc_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { /* SHPC ECN requires dword accesses, but the original 1.0 spec doe= sn't. * It's easier to suppport all sizes than worry about it. */ diff --git a/hw/pcmcia/pxa2xx.c b/hw/pcmcia/pxa2xx.c index 8993b78..4d7002e 100644 --- a/hw/pcmcia/pxa2xx.c +++ b/hw/pcmcia/pxa2xx.c @@ -117,19 +117,19 @@ static void pxa2xx_pcmcia_io_write(void *opaque, hwad= dr offset, static const MemoryRegionOps pxa2xx_pcmcia_common_ops =3D { .read =3D pxa2xx_pcmcia_common_read, .write =3D pxa2xx_pcmcia_common_write, - .endianness =3D DEVICE_NATIVE_ENDIAN + .endianness =3D MO_TE }; static const MemoryRegionOps pxa2xx_pcmcia_attr_ops =3D { .read =3D pxa2xx_pcmcia_attr_read, .write =3D pxa2xx_pcmcia_attr_write, - .endianness =3D DEVICE_NATIVE_ENDIAN + .endianness =3D MO_TE }; static const MemoryRegionOps pxa2xx_pcmcia_io_ops =3D { .read =3D pxa2xx_pcmcia_io_read, .write =3D pxa2xx_pcmcia_io_write, - .endianness =3D DEVICE_NATIVE_ENDIAN + .endianness =3D MO_TE }; static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index a3eac7f..d1f3749 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -927,13 +927,13 @@ void ppce500_init(MachineState *machine) if (serial_hd(0)) { serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 0, qdev_get_gpio_in(mpicdev, 42), 399193, - serial_hd(0), DEVICE_BIG_ENDIAN); + serial_hd(0), MO_BE); } if (serial_hd(1)) { serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 0, qdev_get_gpio_in(mpicdev, 42), 399193, - serial_hd(1), DEVICE_BIG_ENDIAN); + serial_hd(1), MO_BE); } /* I2C */ dev =3D qdev_create(NULL, "mpc-i2c"); diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c index 2b7cc14..758d4ae 100644 --- a/hw/ppc/mpc8544_guts.c +++ b/hw/ppc/mpc8544_guts.c @@ -111,7 +111,7 @@ static void mpc8544_guts_write(void *opaque, hwaddr add= r, static const MemoryRegionOps mpc8544_guts_ops =3D { .read =3D mpc8544_guts_read, .write =3D mpc8544_guts_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index c6411ec..ff06eef 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -98,7 +98,7 @@ static const MemoryRegionOps pnv_core_power8_xscom_ops = =3D { .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; @@ -156,7 +156,7 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = =3D { .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) @@ -377,7 +377,7 @@ static const MemoryRegionOps pnv_quad_xscom_ops =3D { .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void pnv_quad_realize(DeviceState *dev, Error **errp) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index a9f150c..503e5a5 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -336,7 +336,7 @@ static const MemoryRegionOps pnv_lpc_xscom_ops =3D { .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size) @@ -404,7 +404,7 @@ static const MemoryRegionOps pnv_lpc_mmio_ops =3D { .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void pnv_lpc_eval_irqs(PnvLpcController *lpc) @@ -507,7 +507,7 @@ static void lpc_hc_write(void *opaque, hwaddr addr, uin= t64_t val, static const MemoryRegionOps lpc_hc_ops =3D { .read =3D lpc_hc_read, .write =3D lpc_hc_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -586,7 +586,7 @@ static void opb_master_write(void *opaque, hwaddr addr, static const MemoryRegionOps opb_master_ops =3D { .read =3D opb_master_read, .write =3D opb_master_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c index 636f91f..78a2a0b 100644 --- a/hw/ppc/pnv_occ.c +++ b/hw/ppc/pnv_occ.c @@ -91,7 +91,7 @@ static const MemoryRegionOps pnv_occ_power8_xscom_ops =3D= { .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) @@ -162,7 +162,7 @@ static const MemoryRegionOps pnv_occ_power9_xscom_ops = =3D { .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void pnv_occ_power9_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index d7b6f5d..3e1946c 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -417,7 +417,7 @@ static void pnv_psi_mmio_write(void *opaque, hwaddr add= r, static const MemoryRegionOps psi_mmio_ops =3D { .read =3D pnv_psi_mmio_read, .write =3D pnv_psi_mmio_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -442,7 +442,7 @@ static void pnv_psi_xscom_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps pnv_psi_xscom_ops =3D { .read =3D pnv_psi_xscom_read, .write =3D pnv_psi_xscom_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -737,7 +737,7 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr = addr, static const MemoryRegionOps pnv_psi_p9_mmio_ops =3D { .read =3D pnv_psi_p9_mmio_read, .write =3D pnv_psi_p9_mmio_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -774,7 +774,7 @@ static void pnv_psi_p9_xscom_write(void *opaque, hwaddr= addr, static const MemoryRegionOps pnv_psi_p9_xscom_ops =3D { .read =3D pnv_psi_p9_xscom_read, .write =3D pnv_psi_p9_xscom_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, .valid =3D { .min_access_size =3D 8, .max_access_size =3D 8, diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 2b81c75..7c93228 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -210,7 +210,7 @@ const MemoryRegionOps pnv_xscom_ops =3D { .valid.max_access_size =3D 8, .impl.min_access_size =3D 8, .impl.max_access_size =3D 8, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 13318a9..672c664 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -110,7 +110,7 @@ static const MemoryRegionOps ref405ep_fpga_ops =3D { .impl.max_access_size =3D 1, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void ref405ep_fpga_reset (void *opaque) @@ -382,7 +382,7 @@ static const MemoryRegionOps taihu_cpld_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void taihu_cpld_reset (void *opaque) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index edb6b2d..3e6c8fd 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -334,7 +334,7 @@ static const MemoryRegionOps opba_ops =3D { .impl.max_access_size =3D 1, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void ppc4xx_opba_reset (void *opaque) @@ -723,7 +723,7 @@ static void ppc405_gpio_write(void *opaque, hwaddr addr= , uint64_t value, static const MemoryRegionOps ppc405_gpio_ops =3D { .read =3D ppc405_gpio_read, .write =3D ppc405_gpio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void ppc405_gpio_reset (void *opaque) @@ -1105,7 +1105,7 @@ static const MemoryRegionOps gpt_ops =3D { .write =3D ppc4xx_gpt_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void ppc4xx_gpt_cb (void *opaque) @@ -1482,12 +1482,12 @@ CPUPPCState *ppc405cr_init(MemoryRegion *address_sp= ace_mem, if (serial_hd(0) !=3D NULL) { serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_hd(0), - DEVICE_BIG_ENDIAN); + MO_BE); } if (serial_hd(1) !=3D NULL) { serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_hd(1), - DEVICE_BIG_ENDIAN); + MO_BE); } /* IIC controller */ sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); @@ -1845,12 +1845,12 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_sp= ace_mem, if (serial_hd(0) !=3D NULL) { serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_hd(0), - DEVICE_BIG_ENDIAN); + MO_BE); } if (serial_hd(1) !=3D NULL) { serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_hd(1), - DEVICE_BIG_ENDIAN); + MO_BE); } /* OCM */ ppc405_ocm_init(env); diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index b4da099..c5904aa 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -234,12 +234,12 @@ static void bamboo_init(MachineState *machine) if (serial_hd(0) !=3D NULL) { serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE, serial_hd(0), - DEVICE_BIG_ENDIAN); + MO_BE); } if (serial_hd(1) !=3D NULL) { serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE, serial_hd(1), - DEVICE_BIG_ENDIAN); + MO_BE); } if (pcibus) { diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index ca54631..a6e7280 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -393,7 +393,7 @@ static uint64_t ppc440_pcix_reg_read4(void *opaque, hwa= ddr addr, static const MemoryRegionOps pci_reg_ops =3D { .read =3D ppc440_pcix_reg_read4, .write =3D ppc440_pcix_reg_write4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ppc440_pcix_reset(DeviceState *dev) @@ -464,7 +464,7 @@ static uint64_t pci_host_data_read(void *opaque, const MemoryRegionOps ppc440_pcix_host_data_ops =3D { .read =3D pci_host_data_read, .write =3D pci_host_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ppc440_pcix_realize(DeviceState *dev, Error **errp) diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c index e7cf8d5..ceca956 100644 --- a/hw/ppc/ppc4xx_pci.c +++ b/hw/ppc/ppc4xx_pci.c @@ -227,7 +227,7 @@ static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwad= dr offset, static const MemoryRegionOps pci_reg_ops =3D { .read =3D ppc4xx_pci_reg_read4, .write =3D ppc4xx_pci_reg_write4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void ppc4xx_pci_reset(void *opaque) diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index 0060fcb..d4fa92f 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -173,7 +173,7 @@ static uint64_t spin_read(void *opaque, hwaddr addr, un= signed len) static const MemoryRegionOps spin_rw_ops =3D { .read =3D spin_read, .write =3D spin_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void ppce500_spin_initfn(Object *obj) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index fbcddc5..b0a22ed 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -412,12 +412,12 @@ static void sam460ex_init(MachineState *machine) if (serial_hd(0) !=3D NULL) { serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1], PPC_SERIAL_MM_BAUDBASE, serial_hd(0), - DEVICE_BIG_ENDIAN); + MO_BE); } if (serial_hd(1) !=3D NULL) { serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1], PPC_SERIAL_MM_BAUDBASE, serial_hd(1), - DEVICE_BIG_ENDIAN); + MO_BE); } /* Load U-Boot image. */ diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 9003fe9..16df70c 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -763,7 +763,7 @@ static const MemoryRegionOps spapr_msi_ops =3D { /* There is no .read as the read result is undefined by PCI spec */ .read =3D NULL, .write =3D spapr_msi_write, - .endianness =3D DEVICE_LITTLE_ENDIAN + .endianness =3D MO_LE }; /* diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 834053a..9f8a73c 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -242,7 +242,7 @@ static void virtex_init(MachineState *machine) } serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550= _IRQ], - 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); + 115200, serial_hd(0), MO_LE); /* 2 timers at irq 2 @ 62 Mhz. */ dev =3D qdev_create(NULL, "xlnx.xps-timer"); diff --git a/hw/rdma/vmw/pvrdma_main.c b/hw/rdma/vmw/pvrdma_main.c index adcf79c..fb09241 100644 --- a/hw/rdma/vmw/pvrdma_main.c +++ b/hw/rdma/vmw/pvrdma_main.c @@ -439,7 +439,7 @@ static void pvrdma_regs_write(void *opaque, hwaddr addr= , uint64_t val, static const MemoryRegionOps regs_ops =3D { .read =3D pvrdma_regs_read, .write =3D pvrdma_regs_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D sizeof(uint32_t), .max_access_size =3D sizeof(uint32_t), @@ -507,7 +507,7 @@ static void pvrdma_uar_write(void *opaque, hwaddr addr,= uint64_t val, static const MemoryRegionOps uar_ops =3D { .read =3D pvrdma_uar_read, .write =3D pvrdma_uar_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D sizeof(uint32_t), .max_access_size =3D sizeof(uint32_t), diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 591d70d..7ab6d79 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -176,7 +176,7 @@ static void sifive_clint_write(void *opaque, hwaddr add= r, uint64_t value, static const MemoryRegionOps sifive_clint_ops =3D { .read =3D sifive_clint_read, .write =3D sifive_clint_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c index 06bd811..61c7103 100644 --- a/hw/riscv/sifive_gpio.c +++ b/hw/riscv/sifive_gpio.c @@ -272,7 +272,7 @@ static void sifive_gpio_write(void *opaque, hwaddr offs= et, static const MemoryRegionOps gpio_ops =3D { .read =3D sifive_gpio_read, .write =3D sifive_gpio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, }; diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 0950e89..5f156e8 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -354,7 +354,7 @@ err: static const MemoryRegionOps sifive_plic_ops =3D { .read =3D sifive_plic_read, .write =3D sifive_plic_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c index f406682..6dc1461 100644 --- a/hw/riscv/sifive_prci.c +++ b/hw/riscv/sifive_prci.c @@ -73,7 +73,7 @@ static void sifive_prci_write(void *opaque, hwaddr addr, static const MemoryRegionOps sifive_prci_ops =3D { .read =3D sifive_prci_read, .write =3D sifive_prci_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c index 24a04d7..a7a8e73 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/riscv/sifive_test.c @@ -51,7 +51,7 @@ static void sifive_test_write(void *opaque, hwaddr addr, static const MemoryRegionOps sifive_test_ops =3D { .read =3D sifive_test_read, .write =3D sifive_test_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index 3b3f94f..fa1ba98 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -132,7 +132,7 @@ uart_write(void *opaque, hwaddr addr, static const MemoryRegionOps uart_ops =3D { .read =3D uart_read, .write =3D uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 25faf3b..3283954 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -502,7 +502,7 @@ static void riscv_virt_board_init(MachineState *machine) serial_mm_init(system_memory, memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, - serial_hd(0), DEVICE_LITTLE_ENDIAN); + serial_hd(0), MO_LE); g_free(plic_hart_config); } diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 2c6e084..451c279 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -689,7 +689,7 @@ static uint64_t s390_msi_ctrl_read(void *opaque, hwaddr= addr, unsigned size) static const MemoryRegionOps s390_msi_ctrl_ops =3D { .write =3D s390_msi_ctrl_write, .read =3D s390_msi_ctrl_read, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; void s390_pci_iommu_enable(S390PCIIOMMU *iommu) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 342f500..e7804a8 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -291,7 +291,7 @@ static void esp_pci_dma_memory_write(void *opaque, uint= 8_t *buf, int len) static const MemoryRegionOps esp_pci_io_ops =3D { .read =3D esp_pci_io_read, .write =3D esp_pci_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 4, diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 7508d03..fec501c 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -635,7 +635,7 @@ static uint64_t sysbus_esp_mem_read(void *opaque, hwadd= r addr, static const MemoryRegionOps sysbus_esp_mem_ops =3D { .read =3D sysbus_esp_mem_read, .write =3D sysbus_esp_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.accepts =3D esp_mem_accepts, }; diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 10468c1..7e17555 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -2091,7 +2091,7 @@ static uint64_t lsi_mmio_read(void *opaque, hwaddr ad= dr, static const MemoryRegionOps lsi_mmio_ops =3D { .read =3D lsi_mmio_read, .write =3D lsi_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, @@ -2115,7 +2115,7 @@ static uint64_t lsi_ram_read(void *opaque, hwaddr add= r, static const MemoryRegionOps lsi_ram_ops =3D { .read =3D lsi_ram_read, .write =3D lsi_ram_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t lsi_io_read(void *opaque, hwaddr addr, @@ -2135,7 +2135,7 @@ static void lsi_io_write(void *opaque, hwaddr addr, static const MemoryRegionOps lsi_io_ops =3D { .read =3D lsi_io_read, .write =3D lsi_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 1, .max_access_size =3D 1, diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 0c43999..f06b7c6 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -2153,7 +2153,7 @@ static void megasas_mmio_write(void *opaque, hwaddr a= ddr, static const MemoryRegionOps megasas_mmio_ops =3D { .read =3D megasas_mmio_read, .write =3D megasas_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 8, .max_access_size =3D 8, @@ -2175,7 +2175,7 @@ static void megasas_port_write(void *opaque, hwaddr a= ddr, static const MemoryRegionOps megasas_port_ops =3D { .read =3D megasas_port_read, .write =3D megasas_port_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -2197,7 +2197,7 @@ static void megasas_queue_write(void *opaque, hwaddr = addr, static const MemoryRegionOps megasas_queue_ops =3D { .read =3D megasas_queue_read, .write =3D megasas_queue_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 8, .max_access_size =3D 8, diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c index 3f94d5a..c3d8144 100644 --- a/hw/scsi/mptsas.c +++ b/hw/scsi/mptsas.c @@ -1085,7 +1085,7 @@ static void mptsas_mmio_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps mptsas_mmio_ops =3D { .read =3D mptsas_mmio_read, .write =3D mptsas_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1095,7 +1095,7 @@ static const MemoryRegionOps mptsas_mmio_ops =3D { static const MemoryRegionOps mptsas_port_ops =3D { .read =3D mptsas_mmio_read, .write =3D mptsas_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -1120,7 +1120,7 @@ static void mptsas_diag_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps mptsas_diag_ops =3D { .read =3D mptsas_diag_read, .write =3D mptsas_diag_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 14641df..9600846 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -1086,7 +1086,7 @@ pvscsi_cleanup_msi(PVSCSIState *s) static const MemoryRegionOps pvscsi_ops =3D { .read =3D pvscsi_io_read, .write =3D pvscsi_io_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/sd/bcm2835_sdhost.c b/hw/sd/bcm2835_sdhost.c index 2778fb0..f799c37 100644 --- a/hw/sd/bcm2835_sdhost.c +++ b/hw/sd/bcm2835_sdhost.c @@ -370,7 +370,7 @@ static void bcm2835_sdhost_write(void *opaque, hwaddr o= ffset, static const MemoryRegionOps bcm2835_sdhost_ops =3D { .read =3D bcm2835_sdhost_read, .write =3D bcm2835_sdhost_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_bcm2835_sdhost =3D { diff --git a/hw/sd/milkymist-memcard.c b/hw/sd/milkymist-memcard.c index b8d2347..52e3037 100644 --- a/hw/sd/milkymist-memcard.c +++ b/hw/sd/milkymist-memcard.c @@ -236,7 +236,7 @@ static const MemoryRegionOps memcard_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void milkymist_memcard_reset(DeviceState *d) diff --git a/hw/sd/omap_mmc.c b/hw/sd/omap_mmc.c index d0c98ca..9a9626d 100644 --- a/hw/sd/omap_mmc.c +++ b/hw/sd/omap_mmc.c @@ -570,7 +570,7 @@ static void omap_mmc_write(void *opaque, hwaddr offset, static const MemoryRegionOps omap_mmc_ops =3D { .read =3D omap_mmc_read, .write =3D omap_mmc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void omap_mmc_cover_cb(void *opaque, int line, int level) diff --git a/hw/sd/pl181.c b/hw/sd/pl181.c index 81b406d..7c632b1 100644 --- a/hw/sd/pl181.c +++ b/hw/sd/pl181.c @@ -449,7 +449,7 @@ static void pl181_write(void *opaque, hwaddr offset, static const MemoryRegionOps pl181_ops =3D { .read =3D pl181_read, .write =3D pl181_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pl181_reset(DeviceState *d) diff --git a/hw/sd/pxa2xx_mmci.c b/hw/sd/pxa2xx_mmci.c index 81ff5ce..c9ffeb9 100644 --- a/hw/sd/pxa2xx_mmci.c +++ b/hw/sd/pxa2xx_mmci.c @@ -472,7 +472,7 @@ static void pxa2xx_mmci_write(void *opaque, static const MemoryRegionOps pxa2xx_mmci_ops =3D { .read =3D pxa2xx_mmci_read, .write =3D pxa2xx_mmci_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 7b80b1d..664dcf3 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1286,7 +1286,7 @@ static const MemoryRegionOps sdhci_mmio_ops =3D { .max_access_size =3D 4, .unaligned =3D false }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) @@ -1741,7 +1741,7 @@ static const MemoryRegionOps usdhc_mmio_ops =3D { .max_access_size =3D 4, .unaligned =3D false }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void imx_usdhc_init(Object *obj) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index f22c79c..1e7d693 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -176,7 +176,7 @@ static const MemoryRegionOps r2d_fpga_ops =3D { .write =3D r2d_fpga_write, .impl.min_access_size =3D 2, .impl.max_access_size =3D 2, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 2fb6e61..20f5816 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -487,7 +487,7 @@ static const MemoryRegionOps sh7750_mem_ops =3D { .write =3D sh7750_mem_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* sh775x interrupt controller tables for sh_intc.c @@ -748,7 +748,7 @@ static void sh7750_mmct_write(void *opaque, hwaddr addr, static const MemoryRegionOps sh7750_mmct_ops =3D { .read =3D sh7750_mmct_read, .write =3D sh7750_mmct_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) diff --git a/hw/sh4/sh_pci.c b/hw/sh4/sh_pci.c index b15f264..4006210 100644 --- a/hw/sh4/sh_pci.c +++ b/hw/sh4/sh_pci.c @@ -103,7 +103,7 @@ static uint64_t sh_pci_reg_read (void *p, hwaddr addr, static const MemoryRegionOps sh_pci_reg_ops =3D { .read =3D sh_pci_reg_read, .write =3D sh_pci_reg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index 45a61ec..61a7493 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -235,7 +235,7 @@ static void iommu_mem_write(void *opaque, hwaddr addr, static const MemoryRegionOps iommu_mem_ops =3D { .read =3D iommu_mem_read, .write =3D iommu_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c index dc0ce7e..dc5bb11 100644 --- a/hw/sparc64/niagara.c +++ b/hw/sparc64/niagara.c @@ -158,7 +158,7 @@ static void niagara_init(MachineState *machine) } if (serial_hd(0)) { serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200, - serial_hd(0), DEVICE_BIG_ENDIAN); + serial_hd(0), MO_BE); } create_unimplemented_device("sun4v-iob", NIAGARA_IOBBASE, NIAGARA_IOBS= IZE); sun4v_rtc_init(NIAGARA_RTC_BASE); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 5d87be8..9016271 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -249,7 +249,7 @@ static void power_mem_write(void *opaque, hwaddr addr, static const MemoryRegionOps power_mem_ops =3D { .read =3D power_mem_read, .write =3D power_mem_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, @@ -320,7 +320,7 @@ static void ebus_realize(PCIDevice *pci_dev, Error **er= rp) i =3D 0; if (s->console_serial_base) { serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, - 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); + 0, NULL, 115200, serial_hd(i), MO_BE); i++; } serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index 9178277..5073098 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -280,7 +280,7 @@ static uint64_t iommu_mem_read(void *opaque, hwaddr add= r, unsigned size) static const MemoryRegionOps iommu_mem_ops =3D { .read =3D iommu_mem_read, .write =3D iommu_mem_write, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static void iommu_reset(DeviceState *d) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 81f2fb7..fc33c80 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -399,7 +399,7 @@ static void aspeed_smc_flash_default_write(void *opaque= , hwaddr addr, static const MemoryRegionOps aspeed_smc_flash_default_ops =3D { .read =3D aspeed_smc_flash_default_read, .write =3D aspeed_smc_flash_default_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, @@ -707,7 +707,7 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr= addr, uint64_t data, static const MemoryRegionOps aspeed_smc_flash_ops =3D { .read =3D aspeed_smc_flash_read, .write =3D aspeed_smc_flash_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, @@ -818,7 +818,7 @@ static void aspeed_smc_write(void *opaque, hwaddr addr,= uint64_t data, static const MemoryRegionOps aspeed_smc_ops =3D { .read =3D aspeed_smc_read, .write =3D aspeed_smc_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.unaligned =3D true, }; diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 5cec9b5..9b4ec27 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -397,7 +397,7 @@ static void imx_spi_write(void *opaque, hwaddr offset, = uint64_t value, static const struct MemoryRegionOps imx_spi_ops =3D { .read =3D imx_spi_read, .write =3D imx_spi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c index 4c9da5d..ecba086 100644 --- a/hw/ssi/mss-spi.c +++ b/hw/ssi/mss-spi.c @@ -359,7 +359,7 @@ static void spi_write(void *opaque, hwaddr addr, static const MemoryRegionOps spi_ops =3D { .read =3D spi_read, .write =3D spi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4 diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c index f278a55..749c2ea 100644 --- a/hw/ssi/omap_spi.c +++ b/hw/ssi/omap_spi.c @@ -342,7 +342,7 @@ static void omap_mcspi_write(void *opaque, hwaddr addr, static const MemoryRegionOps omap_mcspi_ops =3D { .read =3D omap_mcspi_read, .write =3D omap_mcspi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int c= hnum, diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c index fec73ca..9cd9194 100644 --- a/hw/ssi/pl022.c +++ b/hw/ssi/pl022.c @@ -226,7 +226,7 @@ static void pl022_reset(DeviceState *dev) static const MemoryRegionOps pl022_ops =3D { .read =3D pl022_read, .write =3D pl022_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static int pl022_post_load(void *opaque, int version_id) diff --git a/hw/ssi/stm32f2xx_spi.c b/hw/ssi/stm32f2xx_spi.c index 4249101..4f465f4 100644 --- a/hw/ssi/stm32f2xx_spi.c +++ b/hw/ssi/stm32f2xx_spi.c @@ -166,7 +166,7 @@ static void stm32f2xx_spi_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps stm32f2xx_spi_ops =3D { .read =3D stm32f2xx_spi_read, .write =3D stm32f2xx_spi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_stm32f2xx_spi =3D { diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 1379cb1..f21c5e0 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -313,7 +313,7 @@ done: static const MemoryRegionOps spi_ops =3D { .read =3D spi_read, .write =3D spi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index b29e0a4..de66b9d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -1029,7 +1029,7 @@ no_reg_update: static const MemoryRegionOps spips_ops =3D { .read =3D xilinx_spips_read, .write =3D xilinx_spips_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q) @@ -1120,13 +1120,13 @@ static void xlnx_zynqmp_qspips_write(void *opaque, = hwaddr addr, static const MemoryRegionOps qspips_ops =3D { .read =3D xilinx_spips_read, .write =3D xilinx_qspips_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps xlnx_zynqmp_qspips_ops =3D { .read =3D xlnx_zynqmp_qspips_read, .write =3D xlnx_zynqmp_qspips_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; #define LQSPI_CACHE_SIZE 1024 @@ -1238,7 +1238,7 @@ static MemTxResult lqspi_write(void *opaque, hwaddr o= ffset, uint64_t value, static const MemoryRegionOps lqspi_ops =3D { .read_with_attrs =3D lqspi_read, .write_with_attrs =3D lqspi_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 09e2a7b..8071bd2 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -254,7 +254,7 @@ static const MemoryRegionOps a9_gtimer_this_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const MemoryRegionOps a9_gtimer_ops =3D { @@ -264,7 +264,7 @@ static const MemoryRegionOps a9_gtimer_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void a9_gtimer_reset(DeviceState *dev) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 763e109..6bc32d1 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -178,7 +178,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, = uint64_t value, static const MemoryRegionOps a10_pit_ops =3D { .read =3D a10_pit_read, .write =3D a10_pit_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static Property a10_pit_properties[] =3D { diff --git a/hw/timer/altera_timer.c b/hw/timer/altera_timer.c index 5c1d9e4..74771af 100644 --- a/hw/timer/altera_timer.c +++ b/hw/timer/altera_timer.c @@ -145,7 +145,7 @@ static void timer_write(void *opaque, hwaddr addr, static const MemoryRegionOps timer_ops =3D { .read =3D timer_read, .write =3D timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4 diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 93044aa..0e86be0 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -190,7 +190,7 @@ static const MemoryRegionOps arm_thistimer_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const MemoryRegionOps timerblock_ops =3D { @@ -200,7 +200,7 @@ static const MemoryRegionOps timerblock_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void timerblock_reset(TimerBlock *tb) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index f0a7534..0b534c5 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -265,7 +265,7 @@ static void sp804_write(void *opaque, hwaddr offset, static const MemoryRegionOps sp804_ops =3D { .read =3D sp804_read, .write =3D sp804_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_sp804 =3D { @@ -346,7 +346,7 @@ static void icp_pit_write(void *opaque, hwaddr offset, static const MemoryRegionOps icp_pit_ops =3D { .read =3D icp_pit_read, .write =3D icp_pit_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void icp_pit_init(Object *obj) diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index 9464074..3adb363 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -191,7 +191,7 @@ static MemTxResult systick_write(void *opaque, hwaddr a= ddr, static const MemoryRegionOps systick_ops =3D { .read_with_attrs =3D systick_read, .write_with_attrs =3D systick_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, }; diff --git a/hw/timer/aspeed_rtc.c b/hw/timer/aspeed_rtc.c index 19f061c..9f96530 100644 --- a/hw/timer/aspeed_rtc.c +++ b/hw/timer/aspeed_rtc.c @@ -130,7 +130,7 @@ static void aspeed_rtc_reset(DeviceState *d) static const MemoryRegionOps aspeed_rtc_ops =3D { .read =3D aspeed_rtc_read, .write =3D aspeed_rtc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_aspeed_rtc =3D { diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 29cc5e8..1aca23d 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -448,7 +448,7 @@ static void aspeed_timer_write(void *opaque, hwaddr off= set, uint64_t value, static const MemoryRegionOps aspeed_timer_ops =3D { .read =3D aspeed_timer_read, .write =3D aspeed_timer_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, .valid.unaligned =3D false, diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c index 115d935..f049ecc 100644 --- a/hw/timer/cadence_ttc.c +++ b/hw/timer/cadence_ttc.c @@ -389,7 +389,7 @@ static void cadence_ttc_write(void *opaque, hwaddr offs= et, static const MemoryRegionOps cadence_ttc_ops =3D { .read =3D cadence_ttc_read, .write =3D cadence_ttc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void cadence_timer_reset(CadenceTimerState *s) diff --git a/hw/timer/cmsdk-apb-dualtimer.c b/hw/timer/cmsdk-apb-dualtimer.c index 383f6e1..f8c4e83 100644 --- a/hw/timer/cmsdk-apb-dualtimer.c +++ b/hw/timer/cmsdk-apb-dualtimer.c @@ -373,7 +373,7 @@ static void cmsdk_apb_dualtimer_write(void *opaque, hwa= ddr offset, static const MemoryRegionOps cmsdk_apb_dualtimer_ops =3D { .read =3D cmsdk_apb_dualtimer_read, .write =3D cmsdk_apb_dualtimer_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, /* byte/halfword accesses are just zero-padded on reads and writes */ .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, diff --git a/hw/timer/cmsdk-apb-timer.c b/hw/timer/cmsdk-apb-timer.c index 2e7318b..b9c1677 100644 --- a/hw/timer/cmsdk-apb-timer.c +++ b/hw/timer/cmsdk-apb-timer.c @@ -169,7 +169,7 @@ static void cmsdk_apb_timer_write(void *opaque, hwaddr = offset, uint64_t value, static const MemoryRegionOps cmsdk_apb_timer_ops =3D { .read =3D cmsdk_apb_timer_read, .write =3D cmsdk_apb_timer_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void cmsdk_apb_timer_tick(void *opaque) diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c index c818ed1..4c387f2 100644 --- a/hw/timer/digic-timer.c +++ b/hw/timer/digic-timer.c @@ -121,7 +121,7 @@ static const MemoryRegionOps digic_timer_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void digic_timer_init(Object *obj) diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index 53834e1..56324fc 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -297,7 +297,7 @@ timer_write(void *opaque, hwaddr addr, static const MemoryRegionOps timer_ops =3D { .read =3D timer_read, .write =3D timer_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 874c7b8..0fc67e5 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1412,7 +1412,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr= offset, static const MemoryRegionOps exynos4210_mct_ops =3D { .read =3D exynos4210_mct_read, .write =3D exynos4210_mct_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* MCT init */ diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c index 9bc0327..5df719a 100644 --- a/hw/timer/exynos4210_pwm.c +++ b/hw/timer/exynos4210_pwm.c @@ -375,7 +375,7 @@ static void exynos4210_pwm_reset(DeviceState *d) static const MemoryRegionOps exynos4210_pwm_ops =3D { .read =3D exynos4210_pwm_read, .write =3D exynos4210_pwm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* diff --git a/hw/timer/exynos4210_rtc.c b/hw/timer/exynos4210_rtc.c index 0ecedf7..f62277c 100644 --- a/hw/timer/exynos4210_rtc.c +++ b/hw/timer/exynos4210_rtc.c @@ -544,7 +544,7 @@ static void exynos4210_rtc_reset(DeviceState *d) static const MemoryRegionOps exynos4210_rtc_ops =3D { .read =3D exynos4210_rtc_read, .write =3D exynos4210_rtc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; /* diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index e45a490..13efd6d 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -313,7 +313,7 @@ static void grlib_gptimer_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps grlib_gptimer_ops =3D { .read =3D grlib_gptimer_read, .write =3D grlib_gptimer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 41024f3..9bd154e 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -675,7 +675,7 @@ static const MemoryRegionOps hpet_ram_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void hpet_reset(DeviceState *d) diff --git a/hw/timer/i8254.c b/hw/timer/i8254.c index 0972c47..4f19817 100644 --- a/hw/timer/i8254.c +++ b/hw/timer/i8254.c @@ -315,7 +315,7 @@ static const MemoryRegionOps pit_ioport_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void pit_post_load(PITCommonState *s) diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c index 7a88316..a286f80 100644 --- a/hw/timer/imx_epit.c +++ b/hw/timer/imx_epit.c @@ -282,7 +282,7 @@ static void imx_epit_cmp(void *opaque) static const MemoryRegionOps imx_epit_ops =3D { .read =3D imx_epit_read, .write =3D imx_epit_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_imx_timer_epit =3D { diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c index 3086c03..d1cb371 100644 --- a/hw/timer/imx_gpt.c +++ b/hw/timer/imx_gpt.c @@ -474,7 +474,7 @@ static void imx_gpt_timeout(void *opaque) static const MemoryRegionOps imx_gpt_ops =3D { .read =3D imx_gpt_read, .write =3D imx_gpt_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; diff --git a/hw/timer/lm32_timer.c b/hw/timer/lm32_timer.c index 6ce876c..476d6ec 100644 --- a/hw/timer/lm32_timer.c +++ b/hw/timer/lm32_timer.c @@ -144,7 +144,7 @@ static void timer_write(void *opaque, hwaddr addr, static const MemoryRegionOps timer_ops =3D { .read =3D timer_read, .write =3D timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c index 030c887..8bfbc36 100644 --- a/hw/timer/m48t59.c +++ b/hw/timer/m48t59.c @@ -518,7 +518,7 @@ static const MemoryRegionOps nvram_ops =3D { .impl.max_access_size =3D 1, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_BIG_ENDIAN, + .endianness =3D MO_BE, }; static const VMStateDescription vmstate_m48t59 =3D { @@ -559,7 +559,7 @@ const MemoryRegionOps m48t59_io_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; /* Initialisation routine */ diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c index ce4550b..8ccd950 100644 --- a/hw/timer/mc146818rtc.c +++ b/hw/timer/mc146818rtc.c @@ -930,7 +930,7 @@ static const MemoryRegionOps cmos_ops =3D { .min_access_size =3D 1, .max_access_size =3D 1, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp) diff --git a/hw/timer/milkymist-sysctl.c b/hw/timer/milkymist-sysctl.c index a9d2508..a35d5f5 100644 --- a/hw/timer/milkymist-sysctl.c +++ b/hw/timer/milkymist-sysctl.c @@ -220,7 +220,7 @@ static const MemoryRegionOps sysctl_mmio_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void timer0_hit(void *opaque) diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c index 6add47a..12cfd5d 100644 --- a/hw/timer/mss-timer.c +++ b/hw/timer/mss-timer.c @@ -197,7 +197,7 @@ timer_write(void *opaque, hwaddr offset, static const MemoryRegionOps timer_ops =3D { .read =3D timer_read, .write =3D timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4 diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c index 29fb81a..26204fa 100644 --- a/hw/timer/nrf51_timer.c +++ b/hw/timer/nrf51_timer.c @@ -300,7 +300,7 @@ static void nrf51_timer_write(void *opaque, hwaddr offs= et, static const MemoryRegionOps rng_ops =3D { .read =3D nrf51_timer_read, .write =3D nrf51_timer_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, }; diff --git a/hw/timer/omap_gptimer.c b/hw/timer/omap_gptimer.c index ae2dc99..c745eab 100644 --- a/hw/timer/omap_gptimer.c +++ b/hw/timer/omap_gptimer.c @@ -488,7 +488,7 @@ static const MemoryRegionOps omap_gp_timer_ops =3D { .write =3D omap_gp_timer_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, diff --git a/hw/timer/omap_synctimer.c b/hw/timer/omap_synctimer.c index 0d75a90..f98a20a 100644 --- a/hw/timer/omap_synctimer.c +++ b/hw/timer/omap_synctimer.c @@ -94,7 +94,7 @@ static const MemoryRegionOps omap_synctimer_ops =3D { .write =3D omap_synctimer_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *t= a, diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c index 1a7e2ee..59b5b66 100644 --- a/hw/timer/pl031.c +++ b/hw/timer/pl031.c @@ -175,7 +175,7 @@ static void pl031_write(void * opaque, hwaddr offset, static const MemoryRegionOps pl031_ops =3D { .read =3D pl031_read, .write =3D pl031_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pl031_init(Object *obj) diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c index 4a8ae37..97195b3 100644 --- a/hw/timer/puv3_ost.c +++ b/hw/timer/puv3_ost.c @@ -98,7 +98,7 @@ static const MemoryRegionOps puv3_ost_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void puv3_ost_tick(void *opaque) diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c index 8c1ef43..0d2afac 100644 --- a/hw/timer/pxa2xx_timer.c +++ b/hw/timer/pxa2xx_timer.c @@ -399,7 +399,7 @@ static void pxa2xx_timer_write(void *opaque, hwaddr off= set, static const MemoryRegionOps pxa2xx_timer_ops =3D { .read =3D pxa2xx_timer_read, .write =3D pxa2xx_timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void pxa2xx_timer_tick(void *opaque) diff --git a/hw/timer/sh_timer.c b/hw/timer/sh_timer.c index 91b18ba..e6804f3 100644 --- a/hw/timer/sh_timer.c +++ b/hw/timer/sh_timer.c @@ -302,7 +302,7 @@ static void tmu012_write(void *opaque, hwaddr offset, static const MemoryRegionOps tmu012_ops =3D { .read =3D tmu012_read, .write =3D tmu012_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void tmu012_init(MemoryRegion *sysmem, hwaddr base, diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c index 005fd59..27bba42 100644 --- a/hw/timer/slavio_timer.c +++ b/hw/timer/slavio_timer.c @@ -319,7 +319,7 @@ static void slavio_timer_mem_writel(void *opaque, hwadd= r addr, static const MemoryRegionOps slavio_timer_mem_ops =3D { .read =3D slavio_timer_mem_readl, .write =3D slavio_timer_mem_writel, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c index 4c49dc4..2a52e0d 100644 --- a/hw/timer/stm32f2xx_timer.c +++ b/hw/timer/stm32f2xx_timer.c @@ -265,7 +265,7 @@ static void stm32f2xx_timer_write(void *opaque, hwaddr = offset, static const MemoryRegionOps stm32f2xx_timer_ops =3D { .read =3D stm32f2xx_timer_read, .write =3D stm32f2xx_timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static const VMStateDescription vmstate_stm32f2xx_timer =3D { diff --git a/hw/timer/sun4v-rtc.c b/hw/timer/sun4v-rtc.c index ba62adc..1fb7775 100644 --- a/hw/timer/sun4v-rtc.c +++ b/hw/timer/sun4v-rtc.c @@ -48,7 +48,7 @@ static void sun4v_rtc_write(void *opaque, hwaddr addr, static const MemoryRegionOps sun4v_rtc_ops =3D { .read =3D sun4v_rtc_read, .write =3D sun4v_rtc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void sun4v_rtc_init(hwaddr addr) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 16bcd03..ab4c543 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -187,7 +187,7 @@ timer_write(void *opaque, hwaddr addr, static const MemoryRegionOps timer_ops =3D { .read =3D timer_read, .write =3D timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c index 36daf0c..ebfc53a 100644 --- a/hw/timer/xlnx-zynqmp-rtc.c +++ b/hw/timer/xlnx-zynqmp-rtc.c @@ -173,7 +173,7 @@ static void rtc_reset(DeviceState *dev) static const MemoryRegionOps rtc_ops =3D { .read =3D register_read_memory, .write =3D register_write_memory, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index db0e3e7..c73873a 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -180,7 +180,7 @@ static void tpm_crb_mmio_write(void *opaque, hwaddr add= r, static const MemoryRegionOps tpm_crb_memory_ops =3D { .read =3D tpm_crb_mmio_read, .write =3D tpm_crb_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, diff --git a/hw/tpm/tpm_tis.c b/hw/tpm/tpm_tis.c index d6b3212..7984f82 100644 --- a/hw/tpm/tpm_tis.c +++ b/hw/tpm/tpm_tis.c @@ -846,7 +846,7 @@ static void tpm_tis_mmio_write(void *opaque, hwaddr add= r, static const MemoryRegionOps tpm_tis_memory_ops =3D { .read =3D tpm_tis_mmio_read, .write =3D tpm_tis_mmio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 4, diff --git a/hw/usb/chipidea.c b/hw/usb/chipidea.c index 3dcd22c..5085a7f 100644 --- a/hw/usb/chipidea.c +++ b/hw/usb/chipidea.c @@ -35,7 +35,7 @@ static void chipidea_write(void *opaque, hwaddr offset, static const struct MemoryRegionOps chipidea_ops =3D { .read =3D chipidea_read, .write =3D chipidea_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { /* * Our device would not work correctly if the guest was doing @@ -76,7 +76,7 @@ static void chipidea_dc_write(void *opaque, hwaddr offset, static const struct MemoryRegionOps chipidea_dc_ops =3D { .read =3D chipidea_dc_read, .write =3D chipidea_dc_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .impl =3D { /* * Our device would not work correctly if the guest was doing diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index cd1f3c7..88e53f6 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -223,7 +223,7 @@ static const MemoryRegionOps fusbh200_ehci_mmio_ops =3D= { .write =3D fusbh200_ehci_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void fusbh200_ehci_init(Object *obj) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 62dab05..79ce13d 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -2357,7 +2357,7 @@ static const MemoryRegionOps ehci_mmio_caps_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 1, .impl.max_access_size =3D 1, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps ehci_mmio_opreg_ops =3D { @@ -2365,7 +2365,7 @@ static const MemoryRegionOps ehci_mmio_opreg_ops =3D { .write =3D ehci_opreg_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps ehci_mmio_port_ops =3D { @@ -2373,7 +2373,7 @@ static const MemoryRegionOps ehci_mmio_port_ops =3D { .write =3D ehci_port_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static USBPortOps ehci_port_ops =3D { diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 4f6fdbc..9d7cc15 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -1774,7 +1774,7 @@ static void ohci_async_cancel_device(OHCIState *ohci,= USBDevice *dev) static const MemoryRegionOps ohci_mem_ops =3D { .read =3D ohci_mem_read, .write =3D ohci_mem_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static USBPortOps ohci_port_ops =3D { diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 98bd5cf..1f0aa49 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1196,7 +1196,7 @@ static const MemoryRegionOps uhci_ioport_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 2, .impl.max_access_size =3D 2, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static USBPortOps uhci_port_ops =3D { diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 5894a18..24d4a85 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3161,7 +3161,7 @@ static const MemoryRegionOps xhci_cap_ops =3D { .valid.max_access_size =3D 4, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps xhci_oper_ops =3D { @@ -3169,7 +3169,7 @@ static const MemoryRegionOps xhci_oper_ops =3D { .write =3D xhci_oper_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps xhci_port_ops =3D { @@ -3177,7 +3177,7 @@ static const MemoryRegionOps xhci_port_ops =3D { .write =3D xhci_port_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps xhci_runtime_ops =3D { @@ -3185,7 +3185,7 @@ static const MemoryRegionOps xhci_runtime_ops =3D { .write =3D xhci_runtime_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps xhci_doorbell_ops =3D { @@ -3193,7 +3193,7 @@ static const MemoryRegionOps xhci_doorbell_ops =3D { .write =3D xhci_doorbell_write, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void xhci_attach(USBPort *usbport) diff --git a/hw/usb/tusb6010.c b/hw/usb/tusb6010.c index a61b0f6..3819198 100644 --- a/hw/usb/tusb6010.c +++ b/hw/usb/tusb6010.c @@ -678,7 +678,7 @@ static const MemoryRegionOps tusb_async_ops =3D { .write =3D tusb_async_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void tusb_otg_tick(void *opaque) diff --git a/hw/vfio/common.c b/hw/vfio/common.c index a859298..8954530 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -274,7 +274,7 @@ uint64_t vfio_region_read(void *opaque, const MemoryRegionOps vfio_region_ops =3D { .read =3D vfio_region_read, .write =3D vfio_region_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid =3D { .min_access_size =3D 1, .max_access_size =3D 8, diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index fb3cc33..d5c0268 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -150,7 +150,7 @@ static void vfio_generic_window_quirk_address_write(voi= d *opaque, hwaddr addr, static const MemoryRegionOps vfio_generic_window_address_quirk =3D { .read =3D vfio_generic_window_quirk_address_read, .write =3D vfio_generic_window_quirk_address_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t vfio_generic_window_quirk_data_read(void *opaque, @@ -193,7 +193,7 @@ static void vfio_generic_window_quirk_data_write(void *= opaque, hwaddr addr, static const MemoryRegionOps vfio_generic_window_data_quirk =3D { .read =3D vfio_generic_window_quirk_data_read, .write =3D vfio_generic_window_quirk_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; /* @@ -243,7 +243,7 @@ static void vfio_generic_quirk_mirror_write(void *opaqu= e, hwaddr addr, static const MemoryRegionOps vfio_generic_mirror_quirk =3D { .read =3D vfio_generic_quirk_mirror_read, .write =3D vfio_generic_quirk_mirror_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; /* Is range1 fully contained within range2? */ @@ -278,7 +278,7 @@ static uint64_t vfio_ati_3c3_quirk_read(void *opaque, static const MemoryRegionOps vfio_ati_3c3_quirk =3D { .read =3D vfio_ati_3c3_quirk_read, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static VFIOQuirk *vfio_quirk_alloc(int nr_mem) @@ -605,7 +605,7 @@ static void vfio_nvidia_3d4_quirk_write(void *opaque, h= waddr addr, static const MemoryRegionOps vfio_nvidia_3d4_quirk =3D { .read =3D vfio_nvidia_3d4_quirk_read, .write =3D vfio_nvidia_3d4_quirk_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque, @@ -663,7 +663,7 @@ static void vfio_nvidia_3d0_quirk_write(void *opaque, h= waddr addr, static const MemoryRegionOps vfio_nvidia_3d0_quirk =3D { .read =3D vfio_nvidia_3d0_quirk_read, .write =3D vfio_nvidia_3d0_quirk_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void vfio_vga_probe_nvidia_3d0_quirk(VFIOPCIDevice *vdev) @@ -752,7 +752,7 @@ static void vfio_nvidia_bar5_quirk_master_write(void *o= paque, hwaddr addr, static const MemoryRegionOps vfio_nvidia_bar5_quirk_master =3D { .read =3D vfio_nvidia_bar5_quirk_master_read, .write =3D vfio_nvidia_bar5_quirk_master_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t vfio_nvidia_bar5_quirk_enable_read(void *opaque, @@ -779,7 +779,7 @@ static void vfio_nvidia_bar5_quirk_enable_write(void *o= paque, hwaddr addr, static const MemoryRegionOps vfio_nvidia_bar5_quirk_enable =3D { .read =3D vfio_nvidia_bar5_quirk_enable_read, .write =3D vfio_nvidia_bar5_quirk_enable_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void vfio_probe_nvidia_bar5_quirk(VFIOPCIDevice *vdev, int nr) @@ -929,7 +929,7 @@ static void vfio_nvidia_quirk_mirror_write(void *opaque= , hwaddr addr, static const MemoryRegionOps vfio_nvidia_mirror_quirk =3D { .read =3D vfio_generic_quirk_mirror_read, .write =3D vfio_nvidia_quirk_mirror_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void vfio_nvidia_bar0_quirk_reset(VFIOPCIDevice *vdev, VFIOQuirk *q= uirk) @@ -1090,7 +1090,7 @@ static const MemoryRegionOps vfio_rtl_address_quirk = =3D { .max_access_size =3D 4, .unaligned =3D false, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t vfio_rtl8168_quirk_data_read(void *opaque, @@ -1130,7 +1130,7 @@ static const MemoryRegionOps vfio_rtl_data_quirk =3D { .max_access_size =3D 4, .unaligned =3D false, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void vfio_probe_rtl8168_bar2_quirk(VFIOPCIDevice *vdev, int nr) @@ -1526,7 +1526,7 @@ static void vfio_igd_quirk_data_write(void *opaque, h= waddr addr, static const MemoryRegionOps vfio_igd_data_quirk =3D { .read =3D vfio_igd_quirk_data_read, .write =3D vfio_igd_quirk_data_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static uint64_t vfio_igd_quirk_index_read(void *opaque, @@ -1554,7 +1554,7 @@ static void vfio_igd_quirk_index_write(void *opaque, = hwaddr addr, static const MemoryRegionOps vfio_igd_index_quirk =3D { .read =3D vfio_igd_quirk_index_read, .write =3D vfio_igd_quirk_index_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index d7a4e18..dab2a89 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -879,7 +879,7 @@ static void vfio_rom_write(void *opaque, hwaddr addr, static const MemoryRegionOps vfio_rom_ops =3D { .read =3D vfio_rom_read, .write =3D vfio_rom_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static void vfio_pci_size_rom(VFIOPCIDevice *vdev) @@ -1027,7 +1027,7 @@ uint64_t vfio_vga_read(void *opaque, hwaddr addr, uns= igned size) static const MemoryRegionOps vfio_vga_ops =3D { .read =3D vfio_vga_read, .write =3D vfio_vga_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; /* diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index 97b7f35..84a3f5e 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -313,7 +313,7 @@ static void virtio_mmio_write(void *opaque, hwaddr offs= et, uint64_t value, static const MemoryRegionOps virtio_mem_ops =3D { .read =3D virtio_mmio_read, .write =3D virtio_mmio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void virtio_mmio_update_irq(DeviceState *opaque, uint16_t vector) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 25875c8..b929e44 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -484,7 +484,7 @@ static const MemoryRegionOps virtio_pci_config_ops =3D { .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static MemoryRegion *virtio_address_space_lookup(VirtIOPCIProxy *proxy, @@ -1387,7 +1387,7 @@ static void virtio_pci_modern_regions_init(VirtIOPCIP= roxy *proxy) .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps isr_ops =3D { .read =3D virtio_pci_isr_read, @@ -1396,7 +1396,7 @@ static void virtio_pci_modern_regions_init(VirtIOPCIP= roxy *proxy) .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps device_ops =3D { .read =3D virtio_pci_device_read, @@ -1405,7 +1405,7 @@ static void virtio_pci_modern_regions_init(VirtIOPCIP= roxy *proxy) .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps notify_ops =3D { .read =3D virtio_pci_notify_read, @@ -1414,7 +1414,7 @@ static void virtio_pci_modern_regions_init(VirtIOPCIP= roxy *proxy) .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const MemoryRegionOps notify_pio_ops =3D { .read =3D virtio_pci_notify_read, @@ -1423,7 +1423,7 @@ static void virtio_pci_modern_regions_init(VirtIOPCIP= roxy *proxy) .min_access_size =3D 1, .max_access_size =3D 4, }, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watch= dog.c index 54ac393..fcfa3b4 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -261,7 +261,7 @@ bad_offset: static const MemoryRegionOps cmsdk_apb_watchdog_ops =3D { .read =3D cmsdk_apb_watchdog_read, .write =3D cmsdk_apb_watchdog_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, /* byte/halfword accesses are just zero-padded on reads and writes */ .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 57fe24a..775f73e 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -202,7 +202,7 @@ static const VMStateDescription vmstate_aspeed_wdt =3D { static const MemoryRegionOps aspeed_wdt_ops =3D { .read =3D aspeed_wdt_read, .write =3D aspeed_wdt_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, .valid.unaligned =3D false, diff --git a/hw/watchdog/wdt_i6300esb.c b/hw/watchdog/wdt_i6300esb.c index 6780f01..11cb1ed 100644 --- a/hw/watchdog/wdt_i6300esb.c +++ b/hw/watchdog/wdt_i6300esb.c @@ -398,7 +398,7 @@ static const MemoryRegionOps i6300esb_ops =3D { .write =3D i6300esb_mem_writefn, .valid.min_access_size =3D 1, .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, }; static const VMStateDescription vmstate_i6300esb =3D { diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index 5539d56..215b615 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -436,7 +436,7 @@ static void xen_pt_bar_write(void *o, hwaddr addr, uint= 64_t val, } static const MemoryRegionOps ops =3D { - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .read =3D xen_pt_bar_read, .write =3D xen_pt_bar_write, }; diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c index fb4b887..d12cc1f 100644 --- a/hw/xen/xen_pt_msi.c +++ b/hw/xen/xen_pt_msi.c @@ -507,7 +507,7 @@ static bool pci_msix_accepts(void *opaque, hwaddr addr, static const MemoryRegionOps pci_msix_ops =3D { .read =3D pci_msix_read, .write =3D pci_msix_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/xtensa/mx_pic.c b/hw/xtensa/mx_pic.c index 7075db9..9f11231 100644 --- a/hw/xtensa/mx_pic.c +++ b/hw/xtensa/mx_pic.c @@ -266,7 +266,7 @@ static void xtensa_mx_pic_ext_reg_write(void *opaque, h= waddr offset, static const MemoryRegionOps xtensa_mx_pic_ops =3D { .read =3D xtensa_mx_pic_ext_reg_read, .write =3D xtensa_mx_pic_ext_reg_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, .valid =3D { .unaligned =3D true, }, diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index f7f3e11..3d4a44a 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -117,7 +117,7 @@ static void xtfpga_fpga_write(void *opaque, hwaddr addr, static const MemoryRegionOps xtfpga_fpga_ops =3D { .read =3D xtfpga_fpga_read, .write =3D xtfpga_fpga_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, @@ -212,7 +212,7 @@ static void xtfpga_io_write(void *opaque, hwaddr addr, static const MemoryRegionOps xtfpga_io_ops =3D { .read =3D xtfpga_io_read, .write =3D xtfpga_io_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machin= e) @@ -311,7 +311,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, M= achineState *machine) } serial_mm_init(system_io, 0x0d050020, 2, extints[0], - 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); + 115200, serial_hd(0), MO_TE); dinfo =3D drive_get(IF_PFLASH, 0, 0); if (dinfo) { diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index c388453..01a29ba 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -27,9 +27,9 @@ enum device_endian { }; #if defined(HOST_WORDS_BIGENDIAN) -#define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN +#define DEVICE_HOST_ENDIAN MO_BE #else -#define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN +#define DEVICE_HOST_ENDIAN MO_LE #endif /* address in the RAM (different from a physical address) */ diff --git a/include/exec/memory.h b/include/exec/memory.h index 975b86a..d7acf6a 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -168,7 +168,7 @@ struct MemoryRegionOps { unsigned size, MemTxAttrs attrs); - enum device_endian endianness; + MemOp endianness; /* Guest-visible constraints: */ struct { /* If nonzero, specify bounds on access sizes beyond which a machi= ne diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h index abd5cf7..3a12485 100644 --- a/include/hw/char/serial.h +++ b/include/hw/char/serial.h @@ -92,7 +92,7 @@ SerialState *serial_init(int base, qemu_irq irq, int baud= base, SerialState *serial_mm_init(MemoryRegion *address_space, hwaddr base, int it_shift, qemu_irq irq, int baudbase, - Chardev *chr, enum device_endian end); + Chardev *chr, MemOp end); /* serial-isa.c */ diff --git a/ioport.c b/ioport.c index 04e360e..e5713e8 100644 --- a/ioport.c +++ b/ioport.c @@ -51,7 +51,7 @@ static void unassigned_io_write(void *opaque, hwaddr addr= , uint64_t val, const MemoryRegionOps unassigned_io_ops =3D { .read =3D unassigned_io_read, .write =3D unassigned_io_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; void cpu_outb(uint32_t addr, uint8_t val) @@ -213,7 +213,7 @@ static void portio_write(void *opaque, hwaddr addr, uin= t64_t data, static const MemoryRegionOps portio_ops =3D { .read =3D portio_read, .write =3D portio_write, - .endianness =3D DEVICE_LITTLE_ENDIAN, + .endianness =3D MO_LE, .valid.unaligned =3D true, .impl.unaligned =3D true, }; diff --git a/memory.c b/memory.c index 89ea4fb..3cabb52 100644 --- a/memory.c +++ b/memory.c @@ -346,18 +346,18 @@ static void flatview_simplify(FlatView *view) static bool memory_region_big_endian(MemoryRegion *mr) { #ifdef TARGET_WORDS_BIGENDIAN - return mr->ops->endianness !=3D DEVICE_LITTLE_ENDIAN; + return mr->ops->endianness !=3D MO_LE; #else - return mr->ops->endianness =3D=3D DEVICE_BIG_ENDIAN; + return mr->ops->endianness =3D=3D MO_BE; #endif } static bool memory_region_wrong_endianness(MemoryRegion *mr) { #ifdef TARGET_WORDS_BIGENDIAN - return mr->ops->endianness =3D=3D DEVICE_LITTLE_ENDIAN; + return mr->ops->endianness =3D=3D MO_LE; #else - return mr->ops->endianness =3D=3D DEVICE_BIG_ENDIAN; + return mr->ops->endianness =3D=3D MO_BE; #endif } @@ -1307,7 +1307,7 @@ static bool unassigned_mem_accepts(void *opaque, hwad= dr addr, const MemoryRegionOps unassigned_mem_ops =3D { .valid.accepts =3D unassigned_mem_accepts, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D MO_TE, }; static uint64_t memory_region_ram_device_read(void *opaque, diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index de658c4..d7e28d0 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -21,8 +21,7 @@ /* warning: addr must be aligned */ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result, - enum device_endian endian) + hwaddr addr, MemTxAttrs attrs, MemTxResult *result, MemOp endian) { uint8_t *ptr; uint64_t val; @@ -40,11 +39,11 @@ static inline uint32_t glue(address_space_ldl_internal,= SUFFIX)(ARG1_DECL, /* I/O case */ r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); #if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { + if (endian =3D=3D MO_LE) { val =3D bswap32(val); } #else - if (endian =3D=3D DEVICE_BIG_ENDIAN) { + if (endian =3D=3D MO_BE) { val =3D bswap32(val); } #endif @@ -52,10 +51,10 @@ static inline uint32_t glue(address_space_ldl_internal,= SUFFIX)(ARG1_DECL, /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { - case DEVICE_LITTLE_ENDIAN: + case MO_LE: val =3D ldl_le_p(ptr); break; - case DEVICE_BIG_ENDIAN: + case MO_BE: val =3D ldl_be_p(ptr); break; default: @@ -78,27 +77,26 @@ uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, res= ult, - DEVICE_NATIVE_ENDIAN); + MO_TE); } uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, res= ult, - DEVICE_LITTLE_ENDIAN); + MO_LE); } uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, res= ult, - DEVICE_BIG_ENDIAN); + MO_BE); } /* warning: addr must be aligned */ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result, - enum device_endian endian) + hwaddr addr, MemTxAttrs attrs, MemTxResult *result, MemOp endian) { uint8_t *ptr; uint64_t val; @@ -116,11 +114,11 @@ static inline uint64_t glue(address_space_ldq_interna= l, SUFFIX)(ARG1_DECL, /* I/O case */ r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); #if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { + if (endian =3D=3D MO_LE) { val =3D bswap64(val); } #else - if (endian =3D=3D DEVICE_BIG_ENDIAN) { + if (endian =3D=3D MO_BE) { val =3D bswap64(val); } #endif @@ -128,10 +126,10 @@ static inline uint64_t glue(address_space_ldq_interna= l, SUFFIX)(ARG1_DECL, /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { - case DEVICE_LITTLE_ENDIAN: + case MO_LE: val =3D ldq_le_p(ptr); break; - case DEVICE_BIG_ENDIAN: + case MO_BE: val =3D ldq_be_p(ptr); break; default: @@ -154,21 +152,21 @@ uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, res= ult, - DEVICE_NATIVE_ENDIAN); + MO_TE); } uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, res= ult, - DEVICE_LITTLE_ENDIAN); + MO_LE); } uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, res= ult, - DEVICE_BIG_ENDIAN); + MO_BE); } uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, @@ -207,8 +205,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, /* warning: addr must be aligned */ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL, - hwaddr addr, MemTxAttrs attrs, MemTxResult *result, - enum device_endian endian) + hwaddr addr, MemTxAttrs attrs, MemTxResult *result, MemOp endian) { uint8_t *ptr; uint64_t val; @@ -226,11 +223,11 @@ static inline uint32_t glue(address_space_lduw_intern= al, SUFFIX)(ARG1_DECL, /* I/O case */ r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); #if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { + if (endian =3D=3D MO_LE) { val =3D bswap16(val); } #else - if (endian =3D=3D DEVICE_BIG_ENDIAN) { + if (endian =3D=3D MO_BE) { val =3D bswap16(val); } #endif @@ -238,10 +235,10 @@ static inline uint32_t glue(address_space_lduw_intern= al, SUFFIX)(ARG1_DECL, /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { - case DEVICE_LITTLE_ENDIAN: + case MO_LE: val =3D lduw_le_p(ptr); break; - case DEVICE_BIG_ENDIAN: + case MO_BE: val =3D lduw_be_p(ptr); break; default: @@ -264,21 +261,21 @@ uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, re= sult, - DEVICE_NATIVE_ENDIAN); + MO_TE); } uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, re= sult, - DEVICE_LITTLE_ENDIAN); + MO_LE); } uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result) { return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, re= sult, - DEVICE_BIG_ENDIAN); + MO_BE); } /* warning: addr must be aligned. The ram page is not masked as dirty @@ -323,7 +320,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, /* warning: addr must be aligned */ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, - MemTxResult *result, enum device_endian endian) + MemTxResult *result, MemOp endian) { uint8_t *ptr; MemoryRegion *mr; @@ -338,11 +335,11 @@ static inline void glue(address_space_stl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); #if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { + if (endian =3D=3D MO_LE) { val =3D bswap32(val); } #else - if (endian =3D=3D DEVICE_BIG_ENDIAN) { + if (endian =3D=3D MO_BE) { val =3D bswap32(val); } #endif @@ -351,10 +348,10 @@ static inline void glue(address_space_stl_internal, S= UFFIX)(ARG1_DECL, /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { - case DEVICE_LITTLE_ENDIAN: + case MO_LE: stl_le_p(ptr, val); break; - case DEVICE_BIG_ENDIAN: + case MO_BE: stl_be_p(ptr, val); break; default: @@ -377,21 +374,21 @@ void glue(address_space_stl, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, - result, DEVICE_NATIVE_ENDIAN); + result, MO_TE); } void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, - result, DEVICE_LITTLE_ENDIAN); + result, MO_LE); } void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs, - result, DEVICE_BIG_ENDIAN); + result, MO_BE); } void glue(address_space_stb, SUFFIX)(ARG1_DECL, @@ -428,7 +425,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL, /* warning: addr must be aligned */ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, - MemTxResult *result, enum device_endian endian) + MemTxResult *result, MemOp endian) { uint8_t *ptr; MemoryRegion *mr; @@ -443,11 +440,11 @@ static inline void glue(address_space_stw_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); #if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { + if (endian =3D=3D MO_LE) { val =3D bswap16(val); } #else - if (endian =3D=3D DEVICE_BIG_ENDIAN) { + if (endian =3D=3D MO_BE) { val =3D bswap16(val); } #endif @@ -456,10 +453,10 @@ static inline void glue(address_space_stw_internal, S= UFFIX)(ARG1_DECL, /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { - case DEVICE_LITTLE_ENDIAN: + case MO_LE: stw_le_p(ptr, val); break; - case DEVICE_BIG_ENDIAN: + case MO_BE: stw_be_p(ptr, val); break; default: @@ -482,26 +479,26 @@ void glue(address_space_stw, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, resul= t, - DEVICE_NATIVE_ENDIAN); + MO_TE); } void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, resul= t, - DEVICE_LITTLE_ENDIAN); + MO_LE); } void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, resul= t, - DEVICE_BIG_ENDIAN); + MO_BE); } static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, - MemTxResult *result, enum device_endian endian) + MemTxResult *result, MemOp endian) { uint8_t *ptr; MemoryRegion *mr; @@ -516,11 +513,11 @@ static void glue(address_space_stq_internal, SUFFIX)(= ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); #if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D DEVICE_LITTLE_ENDIAN) { + if (endian =3D=3D MO_LE) { val =3D bswap64(val); } #else - if (endian =3D=3D DEVICE_BIG_ENDIAN) { + if (endian =3D=3D MO_BE) { val =3D bswap64(val); } #endif @@ -529,10 +526,10 @@ static void glue(address_space_stq_internal, SUFFIX)(= ARG1_DECL, /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); switch (endian) { - case DEVICE_LITTLE_ENDIAN: + case MO_LE: stq_le_p(ptr, val); break; - case DEVICE_BIG_ENDIAN: + case MO_BE: stq_be_p(ptr, val); break; default: @@ -555,21 +552,21 @@ void glue(address_space_stq, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, resul= t, - DEVICE_NATIVE_ENDIAN); + MO_TE); } void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, resul= t, - DEVICE_LITTLE_ENDIAN); + MO_LE); } void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result) { glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, resul= t, - DEVICE_BIG_ENDIAN); + MO_BE); } #undef ARG1_DECL -- 1.8.3.1 ? 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boundary="===============6191646813263185949==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============6191646813263185949== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516674749426346btcom_" --_000_156516674749426346btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable device_endian has been made redundant by MemOp. Signed-off-by: Tony Nguyen --- include/exec/cpu-common.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 01a29ba..7eeb78c 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -18,14 +18,6 @@ void tcg_flush_softmmu_tlb(CPUState *cs); #include "exec/memop.h" -enum device_endian { -#ifdef NEED_CPU_H - DEVICE_NATIVE_ENDIAN =3D MO_TE, -#endif - DEVICE_BIG_ENDIAN =3D MO_BE, - DEVICE_LITTLE_ENDIAN =3D MO_LE, -}; - #if defined(HOST_WORDS_BIGENDIAN) #define DEVICE_HOST_ENDIAN MO_BE #else -- 1.8.3.1 ? --_000_156516674749426346btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

device_endian has been made redundant= by MemOp.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 include/exec/cpu-common.h | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 01a29ba..7eeb78c 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -18,14 +18,6 @@ void tcg_flush_softmmu_tlb(CPUState *cs);
 
 #include "exec/memop.h"
 
-enum device_endian {
-#ifdef NEED_CPU_H
-    DEVICE_NATIVE_ENDIAN =3D MO_TE,
-#endif
-    DEVICE_BIG_ENDIAN =3D MO_BE,
-    DEVICE_LITTLE_ENDIAN =3D MO_LE,
-};
-
 #if defined(HOST_WORDS_BIGENDIAN)
 #define DEVICE_HOST_ENDIAN MO_BE
 #else
-- 
1.8.3.1

​

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charset="utf-8" DEVICE_HOST_ENDIAN is conditional upon HOST_WORDS_BIGENDIAN. Code is cleaner if the single use of DEVICE_HOST_ENDIAN is instead directly conditional upon HOST_WORDS_BIGENDIAN. Signed-off-by: Tony Nguyen --- include/exec/cpu-common.h | 8 -------- memory.c | 6 +++++- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 7eeb78c..b33dc0c 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -16,14 +16,6 @@ void tcg_flush_softmmu_tlb(CPUState *cs); #if !defined(CONFIG_USER_ONLY) -#include "exec/memop.h" - -#if defined(HOST_WORDS_BIGENDIAN) -#define DEVICE_HOST_ENDIAN MO_BE -#else -#define DEVICE_HOST_ENDIAN MO_LE -#endif - /* address in the RAM (different from a physical address) */ #if defined(CONFIG_XEN_BACKEND) typedef uint64_t ram_addr_t; diff --git a/memory.c b/memory.c index 3cabb52..11db6ec 100644 --- a/memory.c +++ b/memory.c @@ -1362,7 +1362,11 @@ static void memory_region_ram_device_write(void *opa= que, hwaddr addr, static const MemoryRegionOps ram_device_mem_ops =3D { .read =3D memory_region_ram_device_read, .write =3D memory_region_ram_device_write, - .endianness =3D DEVICE_HOST_ENDIAN, +#if defined(HOST_WORDS_BIGENDIAN) + .endianness =3D MO_BE, +#else + .endianness =3D MO_LE, +#endif .valid =3D { .min_access_size =3D 1, .max_access_size =3D 8, -- 1.8.3.1 ? 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boundary="===============8022994538016741085==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============8022994538016741085== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516679496657397btcom_" --_000_156516679496657397btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation for collapsing the two byte swaps adjust_endianness and handle_bswap into the former. Call memory_region_dispatch_{read|write} with endianness encoded into the "MemOp op" operand. This patch does not change any behaviour as memory_region_dispatch_{read|write} is yet to handle the endianness. Once it does handle endianness, callers with byte swaps need to collapse them into adjust_endianness. Signed-off-by: Tony Nguyen --- hw/s390x/s390-pci-inst.c | 3 ++- hw/virtio/virtio-pci.c | 2 ++ include/exec/memop.h | 4 ++++ memory_ldst.inc.c | 20 +++++++++++++------- target/mips/op_helper.c | 4 ++-- 5 files changed, 23 insertions(+), 10 deletions(-) diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 0e92a37..d322b86 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -782,7 +782,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8= _t r3, uint64_t gaddr, for (i =3D 0; i < len / 8; i++) { result =3D memory_region_dispatch_write(mr, offset + i * 8, ldq_p(buffer + i * 8), - MO_64, MEMTXATTRS_UNSPECIFIE= D); + MO_64 | MO_TE, + MEMTXATTRS_UNSPECIFIED); if (result !=3D MEMTX_OK) { s390_program_interrupt(env, PGM_OPERAND, 6, ra); return 0; diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index b929e44..70eb161 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -551,6 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy, = hwaddr addr, /* As length is under guest control, handle illegal values. */ return; } + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ memory_region_dispatch_write(mr, addr, val, size_memop(len), MEMTXATTRS_UNSPECIFIED); } @@ -575,6 +576,7 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr= addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ memory_region_dispatch_read(mr, addr, &val, size_memop(len), MEMTXATTRS_UNSPECIFIED); switch (len) { diff --git a/include/exec/memop.h b/include/exec/memop.h index 4a4212d..47a5500 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -122,7 +122,11 @@ static inline MemOp size_memop(unsigned size) /* Power of 2 up to 8. */ assert((size & (size - 1)) =3D=3D 0 && size >=3D 1 && size <=3D 8); #endif +#ifdef NEED_CPU_H + return ctz32(size) | MO_TE; +#else return ctz32(size); +#endif } #endif diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index d7e28d0..ff28b30 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_internal, S= UFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap32(val); @@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_internal,= SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap64(val); @@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16, attrs); + /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ + r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian,= attrs); #if defined(TARGET_WORDS_BIGENDIAN) if (endian =3D=3D MO_LE) { val =3D bswap16(val); @@ -297,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL= , if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | MO_TE, = attrs); } else { ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); stl_p(ptr, val); @@ -343,7 +346,8 @@ static inline void glue(address_space_stl_internal, SUF= FIX)(ARG1_DECL, val =3D bswap32(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -448,7 +452,8 @@ static inline void glue(address_space_stw_internal, SUF= FIX)(ARG1_DECL, val =3D bswap16(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_16, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_16 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -521,7 +526,8 @@ static void glue(address_space_stq_internal, SUFFIX)(AR= G1_DECL, val =3D bswap64(val); } #endif - r =3D memory_region_dispatch_write(mr, addr1, val, MO_64, attrs); + /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ + r =3D memory_region_dispatch_write(mr, addr1, val, MO_64 | endian,= attrs); } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index e79f99d..1b475f3 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, target_ulong a= ddr, uint32_t op) if (op =3D=3D 9) { /* Index Store Tag */ memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); + MO_64 | MO_TE, MEMTXATTRS_UNSPECIFIED= ); } else if (op =3D=3D 5) { /* Index Load Tag */ memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); + MO_64 | MO_TE, MEMTXATTRS_UNSPECIFIED)= ; } #endif } -- 1.8.3.1 ? --_000_156516679496657397btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation for collapsing the two by= te swaps adjust_endianness and
handle_bswap into the former.

Call memory_region_dispatch_{read|write} with endianness encoded into<= /div>
the "MemOp op" operand.

This patch does not change any behaviour as
memory_region_dispatch_{read|write} is yet to handle the endianness.

Once it does handle endianness, callers with byte swaps need to
collapse them into adjust_endianness.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 hw/s390x/s390-pci-inst.c |  3 ++-
 hw/virtio/virtio-pci.c   |  2 ++
 include/exec/memop.h     |  4 ++++= ;
 memory_ldst.inc.c        | 20 +++= ;++++++++++-------
 target/mips/op_helper.c  |  4 ++--
 5 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 0e92a37..d322b86 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -782,7 +782,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t = r1, uint8_t r3, uint64_t gaddr,
     for (i =3D 0; i < len / 8; i++) {
         result =3D memory_region_dispatch_wr= ite(mr, offset + i * 8,
                    =                      = ;      ldq_p(buffer + i * 8),
-                    = ;                     &nb= sp;    MO_64, MEMTXATTRS_UNSPECIFIED);
+                   &= nbsp;                    =      MO_64 | MO_TE,
+                   &= nbsp;                    =      MEMTXATTRS_UNSPECIFIED);
         if (result !=3D MEMTX_OK) {
             s390_program_interrupt= (env, PGM_OPERAND, 6, ra);
             return 0;
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index b929e44..70eb161 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -551,6 +551,7 @@ void virtio_address_space_write(VirtIOPCIProxy= *proxy, hwaddr addr,
         /* As length is under guest control,= handle illegal values. */
         return;
     }
+    /* FIXME: memory_region_dispatch_write ignores MO_B= SWAP.  */
     memory_region_dispatch_write(mr, addr, val, size_m= emop(len),
                    =               MEMTXATTRS_UNSPECIFIED);
 }
@@ -575,6 +576,7 @@ virtio_address_space_read(VirtIOPCIProxy *prox= y, hwaddr addr,
     /* Make sure caller aligned buf properly */
     assert(!(((uintptr_t)buf) & (len - 1)));
 
+    /* FIXME: memory_region_dispatch_read ignores MO_BS= WAP.  */
     memory_region_dispatch_read(mr, addr, &val, si= ze_memop(len),
                    =              MEMTXATTRS_UNSPECIFIED);
     switch (len) {
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 4a4212d..47a5500 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -122,7 +122,11 @@ static inline MemOp size_memop(unsigned size)=
     /* Power of 2 up to 8.  */
     assert((size & (size - 1)) =3D=3D 0 &&= size >=3D 1 && size <=3D 8);
 #endif
+#ifdef NEED_CPU_H
+    return ctz32(size) | MO_TE;
+#else
     return ctz32(size);
+#endif
 }
 
 #endif
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index d7e28d0..ff28b30 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,7 +37,8 @@ static inline uint32_t glue(address_space_ldl_in= ternal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_32 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap32(val);<= /div>
@@ -112,7 +113,8 @@ static inline uint64_t glue(address_space_ldq_= internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_64 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap64(val);<= /div>
@@ -221,7 +223,8 @@ static inline uint32_t glue(address_space_lduw= _internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        r =3D memory_region_dispatch_read(mr, add= r1, &val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_read= ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_read(mr,= addr1, &val, MO_16 | endian, attrs);
 #if defined(TARGET_WORDS_BIGENDIAN)
         if (endian =3D=3D MO_LE) {
             val =3D bswap16(val);<= /div>
@@ -297,7 +300,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(= ARG1_DECL,
     if (l < 4 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
 
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | MO_TE, attrs);
     } else {
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
         stl_p(ptr, val);
@@ -343,7 +346,8 @@ static inline void glue(address_space_stl_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap32(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_32, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_32 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -448,7 +452,8 @@ static inline void glue(address_space_stw_inte= rnal, SUFFIX)(ARG1_DECL,
             val =3D bswap16(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_16, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_16 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -521,7 +526,8 @@ static void glue(address_space_stq_internal, S= UFFIX)(ARG1_DECL,
             val =3D bswap64(val);<= /div>
         }
 #endif
-        r =3D memory_region_dispatch_write(mr, ad= dr1, val, MO_64, attrs);
+        /* FIXME: memory_region_dispatch_writ= e ignores MO_BSWAP.  */
+        r =3D memory_region_dispatch_write(mr= , addr1, val, MO_64 | endian, attrs);
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index e79f99d..1b475f3 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4741,11 +4741,11 @@ void helper_cache(CPUMIPSState *env, targe= t_ulong addr, uint32_t op)
     if (op =3D=3D 9) {
         /* Index Store Tag */
         memory_region_dispatch_write(env->= ;itc_tag, index, env->CP0_TagLo,
-                    = ;                 MO_64, MEMTXATTRS= _UNSPECIFIED);
+                   &= nbsp;                 MO_64 | MO_TE= , MEMTXATTRS_UNSPECIFIED);
     } else if (op =3D=3D 5) {
         /* Index Load Tag */
         memory_region_dispatch_read(env->= itc_tag, index, &env->CP0_TagLo,
-                    = ;                MO_64, MEMTXATTRS_= UNSPECIFIED);
+                   &= nbsp;                MO_64 | MO_TE,= MEMTXATTRS_UNSPECIFIED);
     }
 #endif
 }
-- 
1.8.3.1

​


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boundary="===============4254821071505405456==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============4254821071505405456== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516681911114515btcom_" --_000_156516681911114515btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Preparation for collapsing the two byte swaps adjust_endianness and handle_bswap into the former. Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 170 +++++++++++++++++++++++++----------------------= ---- include/exec/memop.h | 6 ++ memory.c | 11 +--- 3 files changed, 90 insertions(+), 97 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6c83878..86d85cc 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, = int size, static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, target_ulong addr, uintptr_t retaddr= , - MMUAccessType access_type, int size) + MMUAccessType access_type, MemOp op) { CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; @@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBE= ntry *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size= ), - iotlbentry->attrs); + r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry-= >attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, access_type, + cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access= _type, mmu_idx, iotlbentry->attrs, r, retaddr); } if (locked) { @@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, int mmu_idx, uint64_t val, target_ulong addr, - uintptr_t retaddr, int size) + uintptr_t retaddr, MemOp op) { CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; @@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntr= y *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - r =3D memory_region_dispatch_write(mr, mr_offset, val, size_memop(size= ), - iotlbentry->attrs); + r =3D memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry-= >attrs); if (r !=3D MEMTX_OK) { hwaddr physaddr =3D mr_offset + section->offset_within_address_space - section->offset_within_region; - cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, - mmu_idx, iotlbentry->attrs, r, retaddr); + cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), + MMU_DATA_STORE, mmu_idx, iotlbentry->attrs,= r, + retaddr); } if (locked) { qemu_mutex_unlock_iothread(); @@ -1216,14 +1215,15 @@ static void *atomic_mmu_lookup(CPUArchState *env, t= arget_ulong addr, * access type. */ -static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endia= n) +static inline uint64_t handle_bswap(uint64_t val, MemOp op) { - if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) { - switch (size) { - case 1: return val; - case 2: return bswap16(val); - case 4: return bswap32(val); - case 8: return bswap64(val); + if ((memop_big_endian(op) && NEED_BE_BSWAP) || + (!memop_big_endian(op) && NEED_LE_BSWAP)) { + switch (op & MO_SIZE) { + case MO_8: return val; + case MO_16: return bswap16(val); + case MO_32: return bswap32(val); + case MO_64: return bswap64(val); default: g_assert_not_reached(); } @@ -1246,7 +1246,7 @@ typedef uint64_t FullLoadHelper(CPUArchState *env, ta= rget_ulong addr, static inline uint64_t __attribute__((always_inline)) load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, - uintptr_t retaddr, size_t size, bool big_endian, bool code_rea= d, + uintptr_t retaddr, MemOp op, bool code_read, FullLoadHelper *full_load) { uintptr_t mmu_idx =3D get_mmuidx(oi); @@ -1260,6 +1260,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, unsigned a_bits =3D get_alignment_bits(get_memop(oi)); void *haddr; uint64_t res; + size_t size =3D memop_size(op); /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { @@ -1305,9 +1306,10 @@ load_helper(CPUArchState *env, target_ulong addr, TC= GMemOpIdx oi, } } + /* FIXME: io_readx ignores MO_BSWAP. */ res =3D io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], - mmu_idx, addr, retaddr, access_type, size); - return handle_bswap(res, size, big_endian); + mmu_idx, addr, retaddr, access_type, op); + return handle_bswap(res, op); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1324,7 +1326,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, r2 =3D full_load(env, addr2, oi, retaddr); shift =3D (addr & (size - 1)) * 8; - if (big_endian) { + if (memop_big_endian(op)) { /* Big-endian combine. */ res =3D (r1 << shift) | (r2 >> ((size * 8) - shift)); } else { @@ -1336,30 +1338,27 @@ load_helper(CPUArchState *env, target_ulong addr, T= CGMemOpIdx oi, do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); - switch (size) { - case 1: + switch (op) { + case MO_8: res =3D ldub_p(haddr); break; - case 2: - if (big_endian) { - res =3D lduw_be_p(haddr); - } else { - res =3D lduw_le_p(haddr); - } + case MO_BEUW: + res =3D lduw_be_p(haddr); break; - case 4: - if (big_endian) { - res =3D (uint32_t)ldl_be_p(haddr); - } else { - res =3D (uint32_t)ldl_le_p(haddr); - } + case MO_LEUW: + res =3D lduw_le_p(haddr); break; - case 8: - if (big_endian) { - res =3D ldq_be_p(haddr); - } else { - res =3D ldq_le_p(haddr); - } + case MO_BEUL: + res =3D (uint32_t)ldl_be_p(haddr); + break; + case MO_LEUL: + res =3D (uint32_t)ldl_le_p(haddr); + break; + case MO_BEQ: + res =3D ldq_be_p(haddr); + break; + case MO_LEQ: + res =3D ldq_le_p(haddr); break; default: g_assert_not_reached(); @@ -1381,8 +1380,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCG= MemOpIdx oi, static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 1, false, false, - full_ldub_mmu); + return load_helper(env, addr, oi, retaddr, MO_8, false, full_ldub_mmu)= ; } tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, @@ -1394,7 +1392,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *en= v, target_ulong addr, static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, false, false, + return load_helper(env, addr, oi, retaddr, MO_LEUW, false, full_le_lduw_mmu); } @@ -1407,7 +1405,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, true, false, + return load_helper(env, addr, oi, retaddr, MO_BEUW, false, full_be_lduw_mmu); } @@ -1420,7 +1418,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, false, false, + return load_helper(env, addr, oi, retaddr, MO_LEUL, false, full_le_ldul_mmu); } @@ -1433,7 +1431,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env= , target_ulong addr, static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, true, false, + return load_helper(env, addr, oi, retaddr, MO_BEUL, false, full_be_ldul_mmu); } @@ -1446,14 +1444,14 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArchState *e= nv, target_ulong addr, uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, false, false, + return load_helper(env, addr, oi, retaddr, MO_LEQ, false, helper_le_ldq_mmu); } uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, true, false, + return load_helper(env, addr, oi, retaddr, MO_BEQ, false, helper_be_ldq_mmu); } @@ -1499,7 +1497,7 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env= , target_ulong addr, static inline void __attribute__((always_inline)) store_helper(CPUArchState *env, target_ulong addr, uint64_t val, - TCGMemOpIdx oi, uintptr_t retaddr, size_t size, bool big_endi= an) + TCGMemOpIdx oi, uintptr_t retaddr, MemOp op) { uintptr_t mmu_idx =3D get_mmuidx(oi); uintptr_t index =3D tlb_index(env, mmu_idx, addr); @@ -1508,6 +1506,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, const size_t tlb_off =3D offsetof(CPUTLBEntry, addr_write); unsigned a_bits =3D get_alignment_bits(get_memop(oi)); void *haddr; + size_t size =3D memop_size(op); /* Handle CPU specific unaligned behaviour */ if (addr & ((1 << a_bits) - 1)) { @@ -1553,9 +1552,10 @@ store_helper(CPUArchState *env, target_ulong addr, u= int64_t val, } } + /* FIXME: io_writex ignores MO_BSWAP. */ io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, - handle_bswap(val, size, big_endian), - addr, retaddr, size); + handle_bswap(val, op), + addr, retaddr, op); return; } @@ -1591,7 +1591,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, */ for (i =3D 0; i < size; ++i) { uint8_t val8; - if (big_endian) { + if (memop_big_endian(op)) { /* Big-endian extract. */ val8 =3D val >> (((size - 1) * 8) - (i * 8)); } else { @@ -1605,30 +1605,27 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, do_aligned_access: haddr =3D (void *)((uintptr_t)addr + entry->addend); - switch (size) { - case 1: + switch (op) { + case MO_8: stb_p(haddr, val); break; - case 2: - if (big_endian) { - stw_be_p(haddr, val); - } else { - stw_le_p(haddr, val); - } + case MO_BEUW: + stw_be_p(haddr, val); break; - case 4: - if (big_endian) { - stl_be_p(haddr, val); - } else { - stl_le_p(haddr, val); - } + case MO_LEUW: + stw_le_p(haddr, val); break; - case 8: - if (big_endian) { - stq_be_p(haddr, val); - } else { - stq_le_p(haddr, val); - } + case MO_BEUL: + stl_be_p(haddr, val); + break; + case MO_LEUL: + stl_le_p(haddr, val); + break; + case MO_BEQ: + stq_be_p(haddr, val); + break; + case MO_LEQ: + stq_le_p(haddr, val); break; default: g_assert_not_reached(); @@ -1639,43 +1636,43 @@ store_helper(CPUArchState *env, target_ulong addr, = uint64_t val, void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 1, false); + store_helper(env, addr, val, oi, retaddr, MO_8); } void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 2, false); + store_helper(env, addr, val, oi, retaddr, MO_LEUW); } void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 2, true); + store_helper(env, addr, val, oi, retaddr, MO_BEUW); } void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 4, false); + store_helper(env, addr, val, oi, retaddr, MO_LEUL); } void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 4, true); + store_helper(env, addr, val, oi, retaddr, MO_BEUL); } void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 8, false); + store_helper(env, addr, val, oi, retaddr, MO_LEQ); } void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, TCGMemOpIdx oi, uintptr_t retaddr) { - store_helper(env, addr, val, oi, retaddr, 8, true); + store_helper(env, addr, val, oi, retaddr, MO_BEQ); } /* First set of helpers allows passing in of OI and RETADDR. This makes @@ -1740,8 +1737,7 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulon= g addr, uint64_t val, static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 1, false, true, - full_ldub_cmmu); + return load_helper(env, addr, oi, retaddr, MO_8, true, full_ldub_cmmu)= ; } uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, @@ -1753,7 +1749,7 @@ uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target= _ulong addr, static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, false, true, + return load_helper(env, addr, oi, retaddr, MO_LEUW, true, full_le_lduw_cmmu); } @@ -1766,7 +1762,7 @@ uint16_t helper_le_ldw_cmmu(CPUArchState *env, target= _ulong addr, static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 2, true, true, + return load_helper(env, addr, oi, retaddr, MO_BEUW, true, full_be_lduw_cmmu); } @@ -1779,7 +1775,7 @@ uint16_t helper_be_ldw_cmmu(CPUArchState *env, target= _ulong addr, static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, false, true, + return load_helper(env, addr, oi, retaddr, MO_LEUL, true, full_le_ldul_cmmu); } @@ -1792,7 +1788,7 @@ uint32_t helper_le_ldl_cmmu(CPUArchState *env, target= _ulong addr, static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 4, true, true, + return load_helper(env, addr, oi, retaddr, MO_BEUL, true, full_be_ldul_cmmu); } @@ -1805,13 +1801,13 @@ uint32_t helper_be_ldl_cmmu(CPUArchState *env, targ= et_ulong addr, uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, false, true, + return load_helper(env, addr, oi, retaddr, MO_LEQ, true, helper_le_ldq_cmmu); } uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - return load_helper(env, addr, oi, retaddr, 8, true, true, + return load_helper(env, addr, oi, retaddr, MO_BEQ, true, helper_be_ldq_cmmu); } diff --git a/include/exec/memop.h b/include/exec/memop.h index 47a5500..e6e03d9 100644 --- a/include/exec/memop.h +++ b/include/exec/memop.h @@ -129,4 +129,10 @@ static inline MemOp size_memop(unsigned size) #endif } +/* Big endianness from MemOp. */ +static inline bool memop_big_endian(MemOp op) +{ + return (op & MO_BSWAP) =3D=3D MO_BE; +} + #endif diff --git a/memory.c b/memory.c index 11db6ec..264c624 100644 --- a/memory.c +++ b/memory.c @@ -343,15 +343,6 @@ static void flatview_simplify(FlatView *view) } } -static bool memory_region_big_endian(MemoryRegion *mr) -{ -#ifdef TARGET_WORDS_BIGENDIAN - return mr->ops->endianness !=3D MO_LE; -#else - return mr->ops->endianness =3D=3D MO_BE; -#endif -} - static bool memory_region_wrong_endianness(MemoryRegion *mr) { #ifdef TARGET_WORDS_BIGENDIAN @@ -564,7 +555,7 @@ static MemTxResult access_with_adjusted_size(hwaddr add= r, /* FIXME: support unaligned access? */ access_size =3D MAX(MIN(size, access_size_max), access_size_min); access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); - if (memory_region_big_endian(mr)) { + if (memop_big_endian(mr->ops->endianness)) { for (i =3D 0; i < size; i +=3D access_size) { r |=3D access_fn(mr, addr + i, value, access_size, (size - access_size - i) * 8, access_mask, attrs); -- 1.8.3.1 ? --_000_156516681911114515btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Preparation for collapsing the two by= te swaps adjust_endianness and
handle_bswap into the former.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c   | 170 ++++++&#= 43;++++++++++++++&#= 43;+++--------------------------
 include/exec/memop.h |   6 ++
 memory.c             |  11 &#= 43;---
 3 files changed, 90 insertions(+), 97 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c83878..86d85cc 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -881,7 +881,7 @@ static void tlb_fill(CPUState *cpu, target_ulo= ng addr, int size,
 
 static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlb= entry,
                    =       int mmu_idx, target_ulong addr, uintptr_t retaddr,
-                    = ;     MMUAccessType access_type, int size)
+                   &= nbsp;     MMUAccessType access_type, MemOp op)
 {
     CPUState *cpu =3D env_cpu(env);
     hwaddr mr_offset;
@@ -906,14 +906,13 @@ static uint64_t io_readx(CPUArchState *env, = CPUIOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked =3D true;
     }
-    r =3D memory_region_dispatch_read(mr, mr_offset, &v= al, size_memop(size),
-                    = ;                iotlbentry->att= rs);
+    r =3D memory_region_dispatch_read(mr, mr_offset, &a= mp;val, op, iotlbentry->attrs);
     if (r !=3D MEMTX_OK) {
         hwaddr physaddr =3D mr_offset +<= /div>
             section->offset_wit= hin_address_space -
             section->offset_wit= hin_region;
 
-        cpu_transaction_failed(cpu, physaddr, add= r, size, access_type,
+        cpu_transaction_failed(cpu, physaddr,= addr, memop_size(op), access_type,
                    =             mmu_idx, iotlbentry->attrs, r,= retaddr);
     }
     if (locked) {
@@ -925,7 +924,7 @@ static uint64_t io_readx(CPUArchState *env, CP= UIOTLBEntry *iotlbentry,
 
 static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbent= ry,
                    =    int mmu_idx, uint64_t val, target_ulong addr,
-                    = ;  uintptr_t retaddr, int size)
+                   &= nbsp;  uintptr_t retaddr, MemOp op)
 {
     CPUState *cpu =3D env_cpu(env);
     hwaddr mr_offset;
@@ -947,15 +946,15 @@ static void io_writex(CPUArchState *env, CPU= IOTLBEntry *iotlbentry,
         qemu_mutex_lock_iothread();
         locked =3D true;
     }
-    r =3D memory_region_dispatch_write(mr, mr_offset, val, = size_memop(size),
-                    = ;                 iotlbentry->at= trs);
+    r =3D memory_region_dispatch_write(mr, mr_offset, v= al, op, iotlbentry->attrs);
     if (r !=3D MEMTX_OK) {
         hwaddr physaddr =3D mr_offset +<= /div>
             section->offset_wit= hin_address_space -
             section->offset_wit= hin_region;
 
-        cpu_transaction_failed(cpu, physaddr, add= r, size, MMU_DATA_STORE,
-                    = ;           mmu_idx, iotlbentry->attrs, r, reta= ddr);
+        cpu_transaction_failed(cpu, physaddr,= addr, memop_size(op),
+                   &= nbsp;           MMU_DATA_STORE, mmu_idx, iotlbentr= y->attrs, r,
+                   &= nbsp;           retaddr);
     }
     if (locked) {
         qemu_mutex_unlock_iothread();
@@ -1216,14 +1215,15 @@ static void *atomic_mmu_lookup(CPUArchStat= e *env, target_ulong addr,
  * access type.
  */
 
-static inline uint64_t handle_bswap(uint64_t val, int size, bool big_= endian)
+static inline uint64_t handle_bswap(uint64_t val, MemOp op)
 {
-    if ((big_endian && NEED_BE_BSWAP) || (!big_endi= an && NEED_LE_BSWAP)) {
-        switch (size) {
-        case 1: return val;
-        case 2: return bswap16(val);
-        case 4: return bswap32(val);
-        case 8: return bswap64(val);
+    if ((memop_big_endian(op) && NEED_BE_BSWAP)= ||
+        (!memop_big_endian(op) && NEE= D_LE_BSWAP)) {
+        switch (op & MO_SIZE) {
+        case MO_8: return val;
+        case MO_16: return bswap16(val);
+        case MO_32: return bswap32(val);
+        case MO_64: return bswap64(val);
         default:
             g_assert_not_reached()= ;
         }
@@ -1246,7 +1246,7 @@ typedef uint64_t FullLoadHelper(CPUArchState= *env, target_ulong addr,
 
 static inline uint64_t __attribute__((always_inline))
 load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi= ,
-            uintptr_t retaddr, size_t s= ize, bool big_endian, bool code_read,
+            uintptr_t retaddr, MemO= p op, bool code_read,
             FullLoadHelper *full_l= oad)
 {
     uintptr_t mmu_idx =3D get_mmuidx(oi);
@@ -1260,6 +1260,7 @@ load_helper(CPUArchState *env, target_ulong = addr, TCGMemOpIdx oi,
     unsigned a_bits =3D get_alignment_bits(get_memop(o= i));
     void *haddr;
     uint64_t res;
+    size_t size =3D memop_size(op);
 
     /* Handle CPU specific unaligned behaviour */
     if (addr & ((1 << a_bits) - 1)) {
@@ -1305,9 +1306,10 @@ load_helper(CPUArchState *env, target_ulong= addr, TCGMemOpIdx oi,
             }
         }
 
+        /* FIXME: io_readx ignores MO_BSWAP. =  */
         res =3D io_readx(env, &env_tlb(e= nv)->d[mmu_idx].iotlb[index],
-                    = ;   mmu_idx, addr, retaddr, access_type, size);
-        return handle_bswap(res, size, big_endian= );
+                   &= nbsp;   mmu_idx, addr, retaddr, access_type, op);
+        return handle_bswap(res, op);
     }
 
     /* Handle slow unaligned access (it spans two page= s or IO).  */
@@ -1324,7 +1326,7 @@ load_helper(CPUArchState *env, target_ulong = addr, TCGMemOpIdx oi,
         r2 =3D full_load(env, addr2, oi, ret= addr);
         shift =3D (addr & (size - 1)) * = 8;
 
-        if (big_endian) {
+        if (memop_big_endian(op)) {
             /* Big-endian combine.=  */
             res =3D (r1 << s= hift) | (r2 >> ((size * 8) - shift));
         } else {
@@ -1336,30 +1338,27 @@ load_helper(CPUArchState *env, target_ulon= g addr, TCGMemOpIdx oi,
 
  do_aligned_access:
     haddr =3D (void *)((uintptr_t)addr + entry->= ;addend);
-    switch (size) {
-    case 1:
+    switch (op) {
+    case MO_8:
         res =3D ldub_p(haddr);
         break;
-    case 2:
-        if (big_endian) {
-            res =3D lduw_be_p(haddr);
-        } else {
-            res =3D lduw_le_p(haddr);
-        }
+    case MO_BEUW:
+        res =3D lduw_be_p(haddr);
         break;
-    case 4:
-        if (big_endian) {
-            res =3D (uint32_t)ldl_be_p(= haddr);
-        } else {
-            res =3D (uint32_t)ldl_le_p(= haddr);
-        }
+    case MO_LEUW:
+        res =3D lduw_le_p(haddr);
         break;
-    case 8:
-        if (big_endian) {
-            res =3D ldq_be_p(haddr);
-        } else {
-            res =3D ldq_le_p(haddr);
-        }
+    case MO_BEUL:
+        res =3D (uint32_t)ldl_be_p(haddr);
+        break;
+    case MO_LEUL:
+        res =3D (uint32_t)ldl_le_p(haddr);
+        break;
+    case MO_BEQ:
+        res =3D ldq_be_p(haddr);
+        break;
+    case MO_LEQ:
+        res =3D ldq_le_p(haddr);
         break;
     default:
         g_assert_not_reached();
@@ -1381,8 +1380,7 @@ load_helper(CPUArchState *env, target_ulong = addr, TCGMemOpIdx oi,
 static uint64_t full_ldub_mmu(CPUArchState *env, target_ulong ad= dr,
                    =            TCGMemOpIdx oi, uintptr_t retaddr)=
 {
-    return load_helper(env, addr, oi, retaddr, 1, false, fa= lse,
-                    = ;   full_ldub_mmu);
+    return load_helper(env, addr, oi, retaddr, MO_8, fa= lse, full_ldub_mmu);
 }
 
 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_u= long addr,
@@ -1394,7 +1392,7 @@ tcg_target_ulong helper_ret_ldub_mmu(CPUArch= State *env, target_ulong addr,
 static uint64_t full_le_lduw_mmu(CPUArchState *env, target_ulong= addr,
                    =               TCGMemOpIdx oi, uintptr_t = retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 2, false, fa= lse,
+    return load_helper(env, addr, oi, retaddr, MO_LEUW,= false,
                    =     full_le_lduw_mmu);
 }
 
@@ -1407,7 +1405,7 @@ tcg_target_ulong helper_le_lduw_mmu(CPUArchS= tate *env, target_ulong addr,
 static uint64_t full_be_lduw_mmu(CPUArchState *env, target_ulong= addr,
                    =               TCGMemOpIdx oi, uintptr_t = retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 2, true, fal= se,
+    return load_helper(env, addr, oi, retaddr, MO_BEUW,= false,
                    =     full_be_lduw_mmu);
 }
 
@@ -1420,7 +1418,7 @@ tcg_target_ulong helper_be_lduw_mmu(CPUArchS= tate *env, target_ulong addr,
 static uint64_t full_le_ldul_mmu(CPUArchState *env, target_ulong= addr,
                    =               TCGMemOpIdx oi, uintptr_t = retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 4, false, fa= lse,
+    return load_helper(env, addr, oi, retaddr, MO_LEUL,= false,
                    =     full_le_ldul_mmu);
 }
 
@@ -1433,7 +1431,7 @@ tcg_target_ulong helper_le_ldul_mmu(CPUArchS= tate *env, target_ulong addr,
 static uint64_t full_be_ldul_mmu(CPUArchState *env, target_ulong= addr,
                    =               TCGMemOpIdx oi, uintptr_t = retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 4, true, fal= se,
+    return load_helper(env, addr, oi, retaddr, MO_BEUL,= false,
                    =     full_be_ldul_mmu);
 }
 
@@ -1446,14 +1444,14 @@ tcg_target_ulong helper_be_ldul_mmu(CPUArc= hState *env, target_ulong addr,
 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,=
                    =         TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 8, false, fa= lse,
+    return load_helper(env, addr, oi, retaddr, MO_LEQ, = false,
                    =     helper_le_ldq_mmu);
 }
 
 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,=
                    =         TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 8, true, fal= se,
+    return load_helper(env, addr, oi, retaddr, MO_BEQ, = false,
                    =     helper_be_ldq_mmu);
 }
 
@@ -1499,7 +1497,7 @@ tcg_target_ulong helper_be_ldsl_mmu(CPUArchS= tate *env, target_ulong addr,
 
 static inline void __attribute__((always_inline))
 store_helper(CPUArchState *env, target_ulong addr, uint64_t val,=
-             TCGMemOpIdx oi, uintptr_t = retaddr, size_t size, bool big_endian)
+             TCGMemOpIdx oi, uintpt= r_t retaddr, MemOp op)
 {
     uintptr_t mmu_idx =3D get_mmuidx(oi);
     uintptr_t index =3D tlb_index(env, mmu_idx, addr);=
@@ -1508,6 +1506,7 @@ store_helper(CPUArchState *env, target_ulong= addr, uint64_t val,
     const size_t tlb_off =3D offsetof(CPUTLBEntry, add= r_write);
     unsigned a_bits =3D get_alignment_bits(get_memop(o= i));
     void *haddr;
+    size_t size =3D memop_size(op);
 
     /* Handle CPU specific unaligned behaviour */
     if (addr & ((1 << a_bits) - 1)) {
@@ -1553,9 +1552,10 @@ store_helper(CPUArchState *env, target_ulon= g addr, uint64_t val,
             }
         }
 
+        /* FIXME: io_writex ignores MO_BSWAP.=  */
         io_writex(env, &env_tlb(env)->= ;d[mmu_idx].iotlb[index], mmu_idx,
-                  handle= _bswap(val, size, big_endian),
-                  addr, = retaddr, size);
+                  ha= ndle_bswap(val, op),
+                  ad= dr, retaddr, op);
         return;
     }
 
@@ -1591,7 +1591,7 @@ store_helper(CPUArchState *env, target_ulong= addr, uint64_t val,
          */
         for (i =3D 0; i < size; ++= ;i) {
             uint8_t val8;
-            if (big_endian) {
+            if (memop_big_endian(op= )) {
                 /* Big-e= ndian extract.  */
                 val8 =3D= val >> (((size - 1) * 8) - (i * 8));
             } else {
@@ -1605,30 +1605,27 @@ store_helper(CPUArchState *env, target_ulo= ng addr, uint64_t val,
 
  do_aligned_access:
     haddr =3D (void *)((uintptr_t)addr + entry->= ;addend);
-    switch (size) {
-    case 1:
+    switch (op) {
+    case MO_8:
         stb_p(haddr, val);
         break;
-    case 2:
-        if (big_endian) {
-            stw_be_p(haddr, val);
-        } else {
-            stw_le_p(haddr, val);
-        }
+    case MO_BEUW:
+        stw_be_p(haddr, val);
         break;
-    case 4:
-        if (big_endian) {
-            stl_be_p(haddr, val);
-        } else {
-            stl_le_p(haddr, val);
-        }
+    case MO_LEUW:
+        stw_le_p(haddr, val);
         break;
-    case 8:
-        if (big_endian) {
-            stq_be_p(haddr, val);
-        } else {
-            stq_le_p(haddr, val);
-        }
+    case MO_BEUL:
+        stl_be_p(haddr, val);
+        break;
+    case MO_LEUL:
+        stl_le_p(haddr, val);
+        break;
+    case MO_BEQ:
+        stq_be_p(haddr, val);
+        break;
+    case MO_LEQ:
+        stq_le_p(haddr, val);
         break;
     default:
         g_assert_not_reached();
@@ -1639,43 +1636,43 @@ store_helper(CPUArchState *env, target_ulo= ng addr, uint64_t val,
 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, ui= nt8_t val,
                    =      TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 1, false);
+    store_helper(env, addr, val, oi, retaddr, MO_8);
 }
 
 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uin= t16_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 2, false);
+    store_helper(env, addr, val, oi, retaddr, MO_LEUW);=
 }
 
 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uin= t16_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 2, true);
+    store_helper(env, addr, val, oi, retaddr, MO_BEUW);=
 }
 
 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uin= t32_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 4, false);
+    store_helper(env, addr, val, oi, retaddr, MO_LEUL);=
 }
 
 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uin= t32_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 4, true);
+    store_helper(env, addr, val, oi, retaddr, MO_BEUL);=
 }
 
 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uin= t64_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 8, false);
+    store_helper(env, addr, val, oi, retaddr, MO_LEQ);<= /div>
 }
 
 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uin= t64_t val,
                    =     TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    store_helper(env, addr, val, oi, retaddr, 8, true);
+    store_helper(env, addr, val, oi, retaddr, MO_BEQ);<= /div>
 }
 
 /* First set of helpers allows passing in of OI and RETADDR. &nb= sp;This makes
@@ -1740,8 +1737,7 @@ void helper_be_stq_mmu(CPUArchState *env, ta= rget_ulong addr, uint64_t val,
 static uint64_t full_ldub_cmmu(CPUArchState *env, target_ulong a= ddr,
                    =             TCGMemOpIdx oi, uintptr_t retaddr= )
 {
-    return load_helper(env, addr, oi, retaddr, 1, false, tr= ue,
-                    = ;   full_ldub_cmmu);
+    return load_helper(env, addr, oi, retaddr, MO_8, tr= ue, full_ldub_cmmu);
 }
 
 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr= ,
@@ -1753,7 +1749,7 @@ uint8_t helper_ret_ldb_cmmu(CPUArchState *en= v, target_ulong addr,
 static uint64_t full_le_lduw_cmmu(CPUArchState *env, target_ulon= g addr,
                    =                TCGMemOpIdx oi, uint= ptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 2, false, tr= ue,
+    return load_helper(env, addr, oi, retaddr, MO_LEUW,= true,
                    =     full_le_lduw_cmmu);
 }
 
@@ -1766,7 +1762,7 @@ uint16_t helper_le_ldw_cmmu(CPUArchState *en= v, target_ulong addr,
 static uint64_t full_be_lduw_cmmu(CPUArchState *env, target_ulon= g addr,
                    =                TCGMemOpIdx oi, uint= ptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 2, true, tru= e,
+    return load_helper(env, addr, oi, retaddr, MO_BEUW,= true,
                    =     full_be_lduw_cmmu);
 }
 
@@ -1779,7 +1775,7 @@ uint16_t helper_be_ldw_cmmu(CPUArchState *en= v, target_ulong addr,
 static uint64_t full_le_ldul_cmmu(CPUArchState *env, target_ulon= g addr,
                    =                TCGMemOpIdx oi, uint= ptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 4, false, tr= ue,
+    return load_helper(env, addr, oi, retaddr, MO_LEUL,= true,
                    =     full_le_ldul_cmmu);
 }
 
@@ -1792,7 +1788,7 @@ uint32_t helper_le_ldl_cmmu(CPUArchState *en= v, target_ulong addr,
 static uint64_t full_be_ldul_cmmu(CPUArchState *env, target_ulon= g addr,
                    =                TCGMemOpIdx oi, uint= ptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 4, true, tru= e,
+    return load_helper(env, addr, oi, retaddr, MO_BEUL,= true,
                    =     full_be_ldul_cmmu);
 }
 
@@ -1805,13 +1801,13 @@ uint32_t helper_be_ldl_cmmu(CPUArchState *= env, target_ulong addr,
 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr= ,
                    =          TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 8, false, tr= ue,
+    return load_helper(env, addr, oi, retaddr, MO_LEQ, = true,
                    =     helper_le_ldq_cmmu);
 }
 
 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr= ,
                    =          TCGMemOpIdx oi, uintptr_t retaddr)
 {
-    return load_helper(env, addr, oi, retaddr, 8, true, tru= e,
+    return load_helper(env, addr, oi, retaddr, MO_BEQ, = true,
                    =     helper_be_ldq_cmmu);
 }
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 47a5500..e6e03d9 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -129,4 +129,10 @@ static inline MemOp size_memop(unsigned size)=
 #endif
 }
 
+/* Big endianness from MemOp.  */
+static inline bool memop_big_endian(MemOp op)
+{
+    return (op & MO_BSWAP) =3D=3D MO_BE;
+}
+
 #endif
diff --git a/memory.c b/memory.c
index 11db6ec..264c624 100644
--- a/memory.c
+++ b/memory.c
@@ -343,15 +343,6 @@ static void flatview_simplify(FlatView *view)=
     }
 }
 
-static bool memory_region_big_endian(MemoryRegion *mr)
-{
-#ifdef TARGET_WORDS_BIGENDIAN
-    return mr->ops->endianness !=3D MO_LE;
-#else
-    return mr->ops->endianness =3D=3D MO_BE;
-#endif
-}
-
 static bool memory_region_wrong_endianness(MemoryRegion *mr)
 {
 #ifdef TARGET_WORDS_BIGENDIAN
@@ -564,7 +555,7 @@ static MemTxResult access_with_adjusted_size(h= waddr addr,
     /* FIXME: support unaligned access? */
     access_size =3D MAX(MIN(size, access_size_max), ac= cess_size_min);
     access_mask =3D MAKE_64BIT_MASK(0, access_size * 8= );
-    if (memory_region_big_endian(mr)) {
+    if (memop_big_endian(mr->ops->endianness)) {<= /div>
         for (i =3D 0; i < size; i += =3D access_size) {
             r |=3D access_fn(mr, a= ddr + i, value, access_size,
                    =      (size - access_size - i) * 8, access_mask, attrs);
-- 
1.8.3.1

​


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boundary="===============8070800635558149836==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============8070800635558149836== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516684008162776btcom_" --_000_156516684008162776btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Now that MemOp has been pushed down into the memory API, and callers are encoding endianness, we can collapse byte swaps along the I/O path into the accelerator and target independent adjust_endianness. Collapsing byte swaps along the I/O path enables additional endian inversion logic, e.g. SPARC64 Invert Endian TTE bit, with redundant byte swaps cancelling out. Suggested-by: Richard Henderson Signed-off-by: Tony Nguyen --- accel/tcg/cputlb.c | 42 +++------------------------------ hw/virtio/virtio-pci.c | 10 ++++---- memory.c | 33 ++++++++++---------------- memory_ldst.inc.c | 64 ----------------------------------------------= ---- 4 files changed, 19 insertions(+), 130 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 86d85cc..473b8e6 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1200,38 +1200,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, ta= rget_ulong addr, cpu_loop_exit_atomic(env_cpu(env), retaddr); } -#ifdef TARGET_WORDS_BIGENDIAN -#define NEED_BE_BSWAP 0 -#define NEED_LE_BSWAP 1 -#else -#define NEED_BE_BSWAP 1 -#define NEED_LE_BSWAP 0 -#endif - -/* - * Byte Swap Helper - * - * This should all dead code away depending on the build host and - * access type. - */ - -static inline uint64_t handle_bswap(uint64_t val, MemOp op) -{ - if ((memop_big_endian(op) && NEED_BE_BSWAP) || - (!memop_big_endian(op) && NEED_LE_BSWAP)) { - switch (op & MO_SIZE) { - case MO_8: return val; - case MO_16: return bswap16(val); - case MO_32: return bswap32(val); - case MO_64: return bswap64(val); - default: - g_assert_not_reached(); - } - } else { - return val; - } -} - /* * Load Helpers * @@ -1306,10 +1274,8 @@ load_helper(CPUArchState *env, target_ulong addr, TC= GMemOpIdx oi, } } - /* FIXME: io_readx ignores MO_BSWAP. */ - res =3D io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], - mmu_idx, addr, retaddr, access_type, op); - return handle_bswap(res, op); + return io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index], + mmu_idx, addr, retaddr, access_type, op); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -1552,10 +1518,8 @@ store_helper(CPUArchState *env, target_ulong addr, u= int64_t val, } } - /* FIXME: io_writex ignores MO_BSWAP. */ io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx, - handle_bswap(val, op), - addr, retaddr, op); + val, addr, retaddr, op); return; } diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 70eb161..f3fe6ca 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -542,16 +542,15 @@ void virtio_address_space_write(VirtIOPCIProxy *proxy= , hwaddr addr, val =3D pci_get_byte(buf); break; case 2: - val =3D cpu_to_le16(pci_get_word(buf)); + val =3D pci_get_word(buf); break; case 4: - val =3D cpu_to_le32(pci_get_long(buf)); + val =3D pci_get_long(buf); break; default: /* As length is under guest control, handle illegal values. */ return; } - /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ memory_region_dispatch_write(mr, addr, val, size_memop(len), MEMTXATTRS_UNSPECIFIED); } @@ -576,7 +575,6 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwaddr= addr, /* Make sure caller aligned buf properly */ assert(!(((uintptr_t)buf) & (len - 1))); - /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ memory_region_dispatch_read(mr, addr, &val, size_memop(len), MEMTXATTRS_UNSPECIFIED); switch (len) { @@ -584,10 +582,10 @@ virtio_address_space_read(VirtIOPCIProxy *proxy, hwad= dr addr, pci_set_byte(buf, val); break; case 2: - pci_set_word(buf, le16_to_cpu(val)); + pci_set_word(buf, val); break; case 4: - pci_set_long(buf, le32_to_cpu(val)); + pci_set_long(buf, val); break; default: /* As length is under guest control, handle illegal values. */ diff --git a/memory.c b/memory.c index 264c624..9d3c3a6 100644 --- a/memory.c +++ b/memory.c @@ -343,32 +343,23 @@ static void flatview_simplify(FlatView *view) } } -static bool memory_region_wrong_endianness(MemoryRegion *mr) +static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op) { -#ifdef TARGET_WORDS_BIGENDIAN - return mr->ops->endianness =3D=3D MO_LE; -#else - return mr->ops->endianness =3D=3D MO_BE; -#endif -} - -static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned s= ize) -{ - if (memory_region_wrong_endianness(mr)) { - switch (size) { - case 1: + if ((op & MO_BSWAP) !=3D mr->ops->endianness) { + switch (op & MO_SIZE) { + case MO_8: break; - case 2: + case MO_16: *data =3D bswap16(*data); break; - case 4: + case MO_32: *data =3D bswap32(*data); break; - case 8: + case MO_64: *data =3D bswap64(*data); break; default: - abort(); + g_assert_not_reached(); } } } @@ -1446,7 +1437,7 @@ MemTxResult memory_region_dispatch_read(MemoryRegion = *mr, } r =3D memory_region_dispatch_read1(mr, addr, pval, size, attrs); - adjust_endianness(mr, pval, size); + adjust_endianness(mr, pval, op); return r; } @@ -1489,7 +1480,7 @@ MemTxResult memory_region_dispatch_write(MemoryRegion= *mr, return MEMTX_DECODE_ERROR; } - adjust_endianness(mr, &data, size); + adjust_endianness(mr, &data, op); if ((!kvm_eventfds_enabled()) && memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)= ) { @@ -2335,7 +2326,7 @@ void memory_region_add_eventfd(MemoryRegion *mr, } if (size) { - adjust_endianness(mr, &mrfd.data, size); + adjust_endianness(mr, &mrfd.data, size_memop(size)); } memory_region_transaction_begin(); for (i =3D 0; i < mr->ioeventfd_nb; ++i) { @@ -2370,7 +2361,7 @@ void memory_region_del_eventfd(MemoryRegion *mr, unsigned i; if (size) { - adjust_endianness(mr, &mrfd.data, size); + adjust_endianness(mr, &mrfd.data, size_memop(size)); } memory_region_transaction_begin(); for (i =3D 0; i < mr->ioeventfd_nb; ++i) { diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index ff28b30..33868f7 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -37,17 +37,7 @@ static inline uint32_t glue(address_space_ldl_internal, = SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ r =3D memory_region_dispatch_read(mr, addr1, &val, MO_32 | endian,= attrs); -#if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D MO_LE) { - val =3D bswap32(val); - } -#else - if (endian =3D=3D MO_BE) { - val =3D bswap32(val); - } -#endif } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -113,17 +103,7 @@ static inline uint64_t glue(address_space_ldq_internal= , SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ r =3D memory_region_dispatch_read(mr, addr1, &val, MO_64 | endian,= attrs); -#if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D MO_LE) { - val =3D bswap64(val); - } -#else - if (endian =3D=3D MO_BE) { - val =3D bswap64(val); - } -#endif } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -223,17 +203,7 @@ static inline uint32_t glue(address_space_lduw_interna= l, SUFFIX)(ARG1_DECL, release_lock |=3D prepare_mmio_access(mr); /* I/O case */ - /* FIXME: memory_region_dispatch_read ignores MO_BSWAP. */ r =3D memory_region_dispatch_read(mr, addr1, &val, MO_16 | endian,= attrs); -#if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D MO_LE) { - val =3D bswap16(val); - } -#else - if (endian =3D=3D MO_BE) { - val =3D bswap16(val); - } -#endif } else { /* RAM case */ ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -299,7 +269,6 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL= , mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | MO_TE, = attrs); } else { ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); @@ -336,17 +305,6 @@ static inline void glue(address_space_stl_internal, SU= FFIX)(ARG1_DECL, mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 4 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - -#if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D MO_LE) { - val =3D bswap32(val); - } -#else - if (endian =3D=3D MO_BE) { - val =3D bswap32(val); - } -#endif - /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ r =3D memory_region_dispatch_write(mr, addr1, val, MO_32 | endian,= attrs); } else { /* RAM case */ @@ -442,17 +400,6 @@ static inline void glue(address_space_stw_internal, SU= FFIX)(ARG1_DECL, mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 2 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - -#if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D MO_LE) { - val =3D bswap16(val); - } -#else - if (endian =3D=3D MO_BE) { - val =3D bswap16(val); - } -#endif - /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ r =3D memory_region_dispatch_write(mr, addr1, val, MO_16 | endian,= attrs); } else { /* RAM case */ @@ -516,17 +463,6 @@ static void glue(address_space_stq_internal, SUFFIX)(A= RG1_DECL, mr =3D TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 8 || !memory_access_is_direct(mr, true)) { release_lock |=3D prepare_mmio_access(mr); - -#if defined(TARGET_WORDS_BIGENDIAN) - if (endian =3D=3D MO_LE) { - val =3D bswap64(val); - } -#else - if (endian =3D=3D MO_BE) { - val =3D bswap64(val); - } -#endif - /* FIXME: memory_region_dispatch_write ignores MO_BSWAP. */ r =3D memory_region_dispatch_write(mr, addr1, val, MO_64 | endian,= attrs); } else { /* RAM case */ -- 1.8.3.1 ? --_000_156516684008162776btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Now that MemOp has been pushed down i= nto the memory API, and
callers are encoding endianness, we can collapse byte swaps
along the I/O path into the accelerator and target independent
adjust_endianness.

Collapsing byte swaps along the I/O path enables additional endian
inversion logic, e.g. SPARC64 Invert Endian TTE bit, with redundant
byte swaps cancelling out.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
---
 accel/tcg/cputlb.c     | 42 +++-----------= -------------------
 hw/virtio/virtio-pci.c | 10 ++++----
 memory.c               | 33 &= #43;+++++++++----------------
 memory_ldst.inc.c      | 64 ---------------------= -----------------------------
 4 files changed, 19 insertions(+), 130 deletions(-)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 86d85cc..473b8e6 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1200,38 +1200,6 @@ static void *atomic_mmu_lookup(CPUArchState= *env, target_ulong addr,
     cpu_loop_exit_atomic(env_cpu(env), retaddr);
 }
 
-#ifdef TARGET_WORDS_BIGENDIAN
-#define NEED_BE_BSWAP 0
-#define NEED_LE_BSWAP 1
-#else
-#define NEED_BE_BSWAP 1
-#define NEED_LE_BSWAP 0
-#endif
-
-/*
- * Byte Swap Helper
- *
- * This should all dead code away depending on the build host and
- * access type.
- */
-
-static inline uint64_t handle_bswap(uint64_t val, MemOp op)
-{
-    if ((memop_big_endian(op) && NEED_BE_BSWAP) ||<= /div>
-        (!memop_big_endian(op) && NEED_LE= _BSWAP)) {
-        switch (op & MO_SIZE) {
-        case MO_8: return val;
-        case MO_16: return bswap16(val);
-        case MO_32: return bswap32(val);
-        case MO_64: return bswap64(val);
-        default:
-            g_assert_not_reached();
-        }
-    } else {
-        return val;
-    }
-}
-
 /*
  * Load Helpers
  *
@@ -1306,10 +1274,8 @@ load_helper(CPUArchState *env, target_ulong= addr, TCGMemOpIdx oi,
             }
         }
 
-        /* FIXME: io_readx ignores MO_BSWAP. &nbs= p;*/
-        res =3D io_readx(env, &env_tlb(env)-&= gt;d[mmu_idx].iotlb[index],
-                    = ;   mmu_idx, addr, retaddr, access_type, op);
-        return handle_bswap(res, op);
+        return io_readx(env, &env_tlb(env= )->d[mmu_idx].iotlb[index],
+                   &= nbsp;    mmu_idx, addr, retaddr, access_type, op);
     }
 
     /* Handle slow unaligned access (it spans two page= s or IO).  */
@@ -1552,10 +1518,8 @@ store_helper(CPUArchState *env, target_ulon= g addr, uint64_t val,
             }
         }
 
-        /* FIXME: io_writex ignores MO_BSWAP. &nb= sp;*/
         io_writex(env, &env_tlb(env)->= ;d[mmu_idx].iotlb[index], mmu_idx,
-                  handle= _bswap(val, op),
-                  addr, = retaddr, op);
+                  va= l, addr, retaddr, op);
         return;
     }
 
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 70eb161..f3fe6ca 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -542,16 +542,15 @@ void virtio_address_space_write(VirtIOPCIPro= xy *proxy, hwaddr addr,
         val =3D pci_get_byte(buf);
         break;
     case 2:
-        val =3D cpu_to_le16(pci_get_word(buf));
+        val =3D pci_get_word(buf);
         break;
     case 4:
-        val =3D cpu_to_le32(pci_get_long(buf));
+        val =3D pci_get_long(buf);
         break;
     default:
         /* As length is under guest control,= handle illegal values. */
         return;
     }
-    /* FIXME: memory_region_dispatch_write ignores MO_BSWAP= .  */
     memory_region_dispatch_write(mr, addr, val, size_m= emop(len),
                    =               MEMTXATTRS_UNSPECIFIED);
 }
@@ -576,7 +575,6 @@ virtio_address_space_read(VirtIOPCIProxy *prox= y, hwaddr addr,
     /* Make sure caller aligned buf properly */
     assert(!(((uintptr_t)buf) & (len - 1)));
 
-    /* FIXME: memory_region_dispatch_read ignores MO_BSWAP.=  */
     memory_region_dispatch_read(mr, addr, &val, si= ze_memop(len),
                    =              MEMTXATTRS_UNSPECIFIED);
     switch (len) {
@@ -584,10 +582,10 @@ virtio_address_space_read(VirtIOPCIProxy *pr= oxy, hwaddr addr,
         pci_set_byte(buf, val);
         break;
     case 2:
-        pci_set_word(buf, le16_to_cpu(val));
+        pci_set_word(buf, val);
         break;
     case 4:
-        pci_set_long(buf, le32_to_cpu(val));
+        pci_set_long(buf, val);
         break;
     default:
         /* As length is under guest control,= handle illegal values. */
diff --git a/memory.c b/memory.c
index 264c624..9d3c3a6 100644
--- a/memory.c
+++ b/memory.c
@@ -343,32 +343,23 @@ static void flatview_simplify(FlatView *view= )
     }
 }
 
-static bool memory_region_wrong_endianness(MemoryRegion *mr)
+static void adjust_endianness(MemoryRegion *mr, uint64_t *data, M= emOp op)
 {
-#ifdef TARGET_WORDS_BIGENDIAN
-    return mr->ops->endianness =3D=3D MO_LE;
-#else
-    return mr->ops->endianness =3D=3D MO_BE;
-#endif
-}
-
-static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsig= ned size)
-{
-    if (memory_region_wrong_endianness(mr)) {
-        switch (size) {
-        case 1:
+    if ((op & MO_BSWAP) !=3D mr->ops->endiann= ess) {
+        switch (op & MO_SIZE) {
+        case MO_8:
             break;
-        case 2:
+        case MO_16:
             *data =3D bswap16(*dat= a);
             break;
-        case 4:
+        case MO_32:
             *data =3D bswap32(*dat= a);
             break;
-        case 8:
+        case MO_64:
             *data =3D bswap64(*dat= a);
             break;
         default:
-            abort();
+            g_assert_not_reached();=
         }
     }
 }
@@ -1446,7 +1437,7 @@ MemTxResult memory_region_dispatch_read(Memo= ryRegion *mr,
     }
 
     r =3D memory_region_dispatch_read1(mr, addr, pval,= size, attrs);
-    adjust_endianness(mr, pval, size);
+    adjust_endianness(mr, pval, op);
     return r;
 }
 
@@ -1489,7 +1480,7 @@ MemTxResult memory_region_dispatch_write(Mem= oryRegion *mr,
         return MEMTX_DECODE_ERROR;
     }
 
-    adjust_endianness(mr, &data, size);
+    adjust_endianness(mr, &data, op);
 
     if ((!kvm_eventfds_enabled()) &&
         memory_region_dispatch_write_eventfd= s(mr, addr, data, size, attrs)) {
@@ -2335,7 +2326,7 @@ void memory_region_add_eventfd(MemoryRegion = *mr,
     }
 
     if (size) {
-        adjust_endianness(mr, &mrfd.data, siz= e);
+        adjust_endianness(mr, &mrfd.data,= size_memop(size));
     }
     memory_region_transaction_begin();
     for (i =3D 0; i < mr->ioeventfd_nb; += 3;i) {
@@ -2370,7 +2361,7 @@ void memory_region_del_eventfd(MemoryRegion = *mr,
     unsigned i;
 
     if (size) {
-        adjust_endianness(mr, &mrfd.data, siz= e);
+        adjust_endianness(mr, &mrfd.data,= size_memop(size));
     }
     memory_region_transaction_begin();
     for (i =3D 0; i < mr->ioeventfd_nb; += 3;i) {
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index ff28b30..33868f7 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -37,17 +37,7 @@ static inline uint32_t glue(address_space_ldl_i= nternal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        /* FIXME: memory_region_dispatch_read ign= ores MO_BSWAP.  */
         r =3D memory_region_dispatch_read(mr= , addr1, &val, MO_32 | endian, attrs);
-#if defined(TARGET_WORDS_BIGENDIAN)
-        if (endian =3D=3D MO_LE) {
-            val =3D bswap32(val);
-        }
-#else
-        if (endian =3D=3D MO_BE) {
-            val =3D bswap32(val);
-        }
-#endif
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -113,17 +103,7 @@ static inline uint64_t glue(address_space_ldq= _internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        /* FIXME: memory_region_dispatch_read ign= ores MO_BSWAP.  */
         r =3D memory_region_dispatch_read(mr= , addr1, &val, MO_64 | endian, attrs);
-#if defined(TARGET_WORDS_BIGENDIAN)
-        if (endian =3D=3D MO_LE) {
-            val =3D bswap64(val);
-        }
-#else
-        if (endian =3D=3D MO_BE) {
-            val =3D bswap64(val);
-        }
-#endif
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -223,17 +203,7 @@ static inline uint32_t glue(address_space_ldu= w_internal, SUFFIX)(ARG1_DECL,
         release_lock |=3D prepare_mmio_acces= s(mr);
 
         /* I/O case */
-        /* FIXME: memory_region_dispatch_read ign= ores MO_BSWAP.  */
         r =3D memory_region_dispatch_read(mr= , addr1, &val, MO_16 | endian, attrs);
-#if defined(TARGET_WORDS_BIGENDIAN)
-        if (endian =3D=3D MO_LE) {
-            val =3D bswap16(val);
-        }
-#else
-        if (endian =3D=3D MO_BE) {
-            val =3D bswap16(val);
-        }
-#endif
     } else {
         /* RAM case */
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -299,7 +269,6 @@ void glue(address_space_stl_notdirty, SUFFIX)(= ARG1_DECL,
     mr =3D TRANSLATE(addr, &addr1, &l, true, a= ttrs);
     if (l < 4 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
-
         r =3D memory_region_dispatch_write(m= r, addr1, val, MO_32 | MO_TE, attrs);
     } else {
         ptr =3D qemu_map_ram_ptr(mr->ram_= block, addr1);
@@ -336,17 +305,6 @@ static inline void glue(address_space_stl_int= ernal, SUFFIX)(ARG1_DECL,
     mr =3D TRANSLATE(addr, &addr1, &l, true, a= ttrs);
     if (l < 4 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
-
-#if defined(TARGET_WORDS_BIGENDIAN)
-        if (endian =3D=3D MO_LE) {
-            val =3D bswap32(val);
-        }
-#else
-        if (endian =3D=3D MO_BE) {
-            val =3D bswap32(val);
-        }
-#endif
-        /* FIXME: memory_region_dispatch_write ig= nores MO_BSWAP.  */
         r =3D memory_region_dispatch_write(m= r, addr1, val, MO_32 | endian, attrs);
     } else {
         /* RAM case */
@@ -442,17 +400,6 @@ static inline void glue(address_space_stw_int= ernal, SUFFIX)(ARG1_DECL,
     mr =3D TRANSLATE(addr, &addr1, &l, true, a= ttrs);
     if (l < 2 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
-
-#if defined(TARGET_WORDS_BIGENDIAN)
-        if (endian =3D=3D MO_LE) {
-            val =3D bswap16(val);
-        }
-#else
-        if (endian =3D=3D MO_BE) {
-            val =3D bswap16(val);
-        }
-#endif
-        /* FIXME: memory_region_dispatch_write ig= nores MO_BSWAP.  */
         r =3D memory_region_dispatch_write(m= r, addr1, val, MO_16 | endian, attrs);
     } else {
         /* RAM case */
@@ -516,17 +463,6 @@ static void glue(address_space_stq_internal, = SUFFIX)(ARG1_DECL,
     mr =3D TRANSLATE(addr, &addr1, &l, true, a= ttrs);
     if (l < 8 || !memory_access_is_direct(mr, true)= ) {
         release_lock |=3D prepare_mmio_acces= s(mr);
-
-#if defined(TARGET_WORDS_BIGENDIAN)
-        if (endian =3D=3D MO_LE) {
-            val =3D bswap64(val);
-        }
-#else
-        if (endian =3D=3D MO_BE) {
-            val =3D bswap64(val);
-        }
-#endif
-        /* FIXME: memory_region_dispatch_write ig= nores MO_BSWAP.  */
         r =3D memory_region_dispatch_write(m= r, addr1, val, MO_64 | endian, attrs);
     } else {
         /* RAM case */
-- 
1.8.3.1

​


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boundary="===============4354362297589187622==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============4354362297589187622== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516686024278427btcom_" --_000_156516686024278427btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable The fast path is taken when TLB_FLAGS_MASK is all zero. TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path, there are no other side effects. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 536ea58..e496f99 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS - 3)) /* Set if TLB entry must have MMU lookup repeated for every access */ #define TLB_RECHECK (1 << (TARGET_PAGE_BITS - 4)) +/* Set if TLB entry must take the slow path. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS - 5)) /* Use this mask to check interception with an alignment mask * in a TCG backend. */ -#define TLB_FLAGS_MASK (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_RECHECK) +#define TLB_FLAGS_MASK \ + (TLB_INVALID_MASK \ + | TLB_NOTDIRTY \ + | TLB_MMIO \ + | TLB_RECHECK \ + | TLB_FORCE_SLOW) /** * tlb_hit_page: return true if page aligned @addr is a hit against the -- 1.8.3.1 ? --_000_156516686024278427btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

The fast path is taken when TLB_FLAGS= _MASK is all zero.

TLB_FORCE_SLOW is simply a TLB_FLAGS_MASK bit to force the slow path,<= /div>
there are no other side effects.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-all.h | 10 +++++++&= #43;--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 536ea58..e496f99 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -331,12 +331,18 @@ CPUArchState *cpu_copy(CPUArchState *env);
 #define TLB_MMIO            (1 <= ;< (TARGET_PAGE_BITS - 3))
 /* Set if TLB entry must have MMU lookup repeated for every acce= ss */
 #define TLB_RECHECK         (1 << (TAR= GET_PAGE_BITS - 4))
+/* Set if TLB entry must take the slow path.  */
+#define TLB_FORCE_SLOW      (1 << (TARGET_PA= GE_BITS - 5))
 
 /* Use this mask to check interception with an alignment mask
  * in a TCG backend.
  */
-#define TLB_FLAGS_MASK  (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_M= MIO \
-                    = ;     | TLB_RECHECK)
+#define TLB_FLAGS_MASK \
+    (TLB_INVALID_MASK  \
+     | TLB_NOTDIRTY    \
+     | TLB_MMIO        \
+     | TLB_RECHECK     \
+     | TLB_FORCE_SLOW)
 
 /**
  * tlb_hit_page: return true if page aligned @addr is a hit agai= nst the
-- 
1.8.3.1

​

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Wed, 7 Aug 2019 09:34:41 +0100 X-Inumbo-ID: 35e05970-b8ee-11e9-8980-bc764e045a96 From: To: Thread-Topic: [Qemu-devel] [PATCH v6 24/26] cputlb: Byte swap memory transaction attribute Thread-Index: AQHVTPr0XHOobhwzF02y9V3sLlC8dA== Date: Wed, 7 Aug 2019 08:34:40 +0000 Message-ID: <1565166880633.15851@bt.com> References: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> In-Reply-To: <45ec4924e0b34a3d9124e2db06af75b4@tpw09926dag18e.domain1.systemhost.net> Accept-Language: en-AU, en-GB, en-US Content-Language: en-AU X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.187.101.44] MIME-Version: 1.0 Subject: [Xen-devel] [Qemu-devel] [PATCH v6 24/26] cputlb: Byte swap memory transaction attribute X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, cohuck@redhat.com, sagark@eecs.berkeley.edu, david@redhat.com, jasowang@redhat.com, palmer@sifive.com, mark.cave-ayland@ilande.co.uk, i.mitsyanko@gmail.com, keith.busch@intel.com, jcmvbkbc@gmail.com, frederic.konrad@adacore.com, dmitry.fleytman@gmail.com, kraxel@redhat.com, edgar.iglesias@gmail.com, gxt@mprc.pku.edu.cn, pburton@wavecomp.com, xiaoguangrong.eric@gmail.com, peter.chubb@nicta.com.au, philmd@redhat.com, robh@kernel.org, hare@suse.com, sstabellini@kernel.org, berto@igalia.com, chouteau@adacore.com, qemu-block@nongnu.org, arikalo@wavecomp.com, jslaby@suse.cz, deller@gmx.de, mst@redhat.com, magnus.damm@gmail.com, jcd@tribudubois.net, pasic@linux.ibm.com, borntraeger@de.ibm.com, mreitz@redhat.com, hpoussin@reactos.org, joel@jms.id.au, anthony.perard@citrix.com, xen-devel@lists.xenproject.org, david@gibson.dropbear.id.au, lersek@redhat.com, green@moxielogic.com, atar4qemu@gmail.com, antonynpavlov@gmail.com, marex@denx.de, jiri@resnulli.us, ehabkost@redhat.com, minyard@acm.org, qemu-s390x@nongnu.org, sw@weilnetz.de, alistair@alistair23.me, yuval.shaia@oracle.com, b.galvani@gmail.com, eric.auger@redhat.com, alex.williamson@redhat.com, qemu-arm@nongnu.org, jan.kiszka@web.de, clg@kaod.org, stefanha@redhat.com, marcandre.lureau@redhat.com, shorne@gmail.com, jsnow@redhat.com, rth@twiddle.net, kwolf@redhat.com, qemu-riscv@nongnu.org, proljc@gmail.com, pbonzini@redhat.com, andrew@aj.id.au, kbastian@mail.uni-paderborn.de, crwulff@gmail.com, laurent@vivier.eu, Andrew.Baumann@microsoft.com, sundeep.lkml@gmail.com, andrew.smirnov@gmail.com, michael@walle.cc, paul.durrant@citrix.com, qemu-ppc@nongnu.org, huth@tuxfamily.org, amarkovic@wavecomp.com, imammedo@redhat.com, aurelien@aurel32.net, stefanb@linux.ibm.com Content-Type: multipart/mixed; boundary="===============1829762541040913918==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============1829762541040913918== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516688063315851btcom_" --_000_156516688063315851btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Notice new attribute, byte swap, and force the transaction through the memory slow path. Required by architectures that can invert endianness of memory transaction, e.g. SPARC64 has the Invert Endian TTE bit. Suggested-by: Richard Henderson Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- accel/tcg/cputlb.c | 11 +++++++++++ include/exec/memattrs.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 473b8e6..f6f4dd5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulon= g vaddr, */ address |=3D TLB_RECHECK; } + if (attrs.byte_swap) { + address |=3D TLB_FORCE_SLOW; + } if (!memory_region_is_ram(section->mr) && !memory_region_is_romd(section->mr)) { /* IO memory case */ @@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; @@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry= *iotlbentry, bool locked =3D false; MemTxResult r; + if (iotlbentry->attrs.byte_swap) { + op ^=3D MO_BSWAP; + } + section =3D iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs)= ; mr =3D section->mr; mr_offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index d4a3477..95f2d20 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -37,6 +37,8 @@ typedef struct MemTxAttrs { unsigned int user:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; + /* Invert endianness for this page */ + unsigned int byte_swap:1; /* * The following are target-specific page-table bits. These are not * related to actual memory transactions at all. However, this struct= ure -- 1.8.3.1 ? --_000_156516688063315851btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Notice new attribute, byte swap, and = force the transaction through the
memory slow path.

Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 accel/tcg/cputlb.c      | 11 ++++= +++++++
 include/exec/memattrs.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 473b8e6..f6f4dd5 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -738,6 +738,9 @@ void tlb_set_page_with_attrs(CPUState *cpu, ta= rget_ulong vaddr,
          */
         address |=3D TLB_RECHECK;
     }
+    if (attrs.byte_swap) {
+        address |=3D TLB_FORCE_SLOW;
+    }
     if (!memory_region_is_ram(section->mr) &&am= p;
         !memory_region_is_romd(section->m= r)) {
         /* IO memory case */
@@ -891,6 +894,10 @@ static uint64_t io_readx(CPUArchState *env, C= PUIOTLBEntry *iotlbentry,
     bool locked =3D false;
     MemTxResult r;
 
+    if (iotlbentry->attrs.byte_swap) {
+        op ^=3D MO_BSWAP;
+    }
+
     section =3D iotlb_to_section(cpu, iotlbentry->a= ddr, iotlbentry->attrs);
     mr =3D section->mr;
     mr_offset =3D (iotlbentry->addr & TARGET_PA= GE_MASK) + addr;
@@ -933,6 +940,10 @@ static void io_writex(CPUArchState *env, CPUI= OTLBEntry *iotlbentry,
     bool locked =3D false;
     MemTxResult r;
 
+    if (iotlbentry->attrs.byte_swap) {
+        op ^=3D MO_BSWAP;
+    }
+
     section =3D iotlb_to_section(cpu, iotlbentry->a= ddr, iotlbentry->attrs);
     mr =3D section->mr;
     mr_offset =3D (iotlbentry->addr & TARGET_PA= GE_MASK) + addr;
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index d4a3477..95f2d20 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -37,6 +37,8 @@ typedef struct MemTxAttrs {
     unsigned int user:1;
     /* Requester ID (for MSI for example) */
     unsigned int requester_id:16;
+    /* Invert endianness for this page */
+    unsigned int byte_swap:1;
     /*
      * The following are target-specific page-table bi= ts.  These are not
      * related to actual memory transactions at all. &= nbsp;However, this structure
-- 
1.8.3.1

​

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boundary="===============0258353548311112398==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============0258353548311112398== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516691175116655btcom_" --_000_156516691175116655btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Append MemTxAttrs to interfaces so we can pass along up coming Invert Endian TTE bit on SPARC64. Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- target/sparc/mmu_helper.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index cbd1e91..826e14b 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -88,7 +88,7 @@ static const int perm_table[2][8] =3D { }; static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, + int *prot, int *access_index, MemTxAttrs *= attrs, target_ulong address, int rw, int mmu_idx, target_ulong *page_size) { @@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, target_ulong vaddr; target_ulong page_size; int error_code =3D 0, prot, access_index; + MemTxAttrs attrs =3D {}; /* * TODO: If we ever need tlb_vaddr_to_host for this target, @@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, assert(!probe); address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index, + error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, address, access_type, mmu_idx, &page_size); vaddr =3D address; @@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *t= lb, return 0; } -static int get_physical_address_data(CPUSPARCState *env, - hwaddr *physical, int *prot, +static int get_physical_address_data(CPUSPARCState *env, hwaddr *physical, + int *prot, MemTxAttrs *attrs, target_ulong address, int rw, int mmu= _idx) { CPUState *cs =3D env_cpu(env); @@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCState *env= , return 1; } -static int get_physical_address_code(CPUSPARCState *env, - hwaddr *physical, int *prot, +static int get_physical_address_code(CPUSPARCState *env, hwaddr *physical, + int *prot, MemTxAttrs *attrs, target_ulong address, int mmu_idx) { CPUState *cs =3D env_cpu(env); @@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCState *env= , } static int get_physical_address(CPUSPARCState *env, hwaddr *physical, - int *prot, int *access_index, + int *prot, int *access_index, MemTxAttrs *= attrs, target_ulong address, int rw, int mmu_idx, target_ulong *page_size) { @@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCState *env, h= waddr *physical, } if (rw =3D=3D 2) { - return get_physical_address_code(env, physical, prot, address, + return get_physical_address_code(env, physical, prot, attrs, addre= ss, mmu_idx); } else { - return get_physical_address_data(env, physical, prot, address, rw, - mmu_idx); + return get_physical_address_data(env, physical, prot, attrs, addre= ss, + rw, mmu_idx); } } @@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, target_ulong vaddr; hwaddr paddr; target_ulong page_size; + MemTxAttrs attrs =3D {}; int error_code =3D 0, prot, access_index; address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &paddr, &prot, &access_index, + error_code =3D get_physical_address(env, &paddr, &prot, &access_index,= &attrs, address, access_type, mmu_idx, &page_size); if (likely(error_code =3D=3D 0)) { @@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, + page_size); return true; } if (probe) { @@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env,= hwaddr *phys, { target_ulong page_size; int prot, access_index; + MemTxAttrs attrs =3D {}; - return get_physical_address(env, phys, &prot, &access_index, addr, rw, - mmu_idx, &page_size); + return get_physical_address(env, phys, &prot, &access_index, &attrs, a= ddr, + rw, mmu_idx, &page_size); } #if defined(TARGET_SPARC64) -- 1.8.3.1 ? --_000_156516691175116655btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

Append MemTxAttrs to interfaces so we= can pass along up coming Invert
Endian TTE bit on SPARC64.

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/mmu_helper.c | 32 ++++++= 3;+++++++++++--------------
 1 file changed, 18 insertions(+), 14 deletions(-)

diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index cbd1e91..826e14b 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -88,7 +88,7 @@ static const int perm_table[2][8] =3D {
 };
 
 static int get_physical_address(CPUSPARCState *env, hwaddr *phys= ical,
-                    = ;            int *prot, int *access_index,
+                   &= nbsp;            int *prot, int *access_index= , MemTxAttrs *attrs,
                    =              target_ulong address, int r= w, int mmu_idx,
                    =              target_ulong *page_size)
 {
@@ -219,6 +219,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
     target_ulong vaddr;
     target_ulong page_size;
     int error_code =3D 0, prot, access_index;
+    MemTxAttrs attrs =3D {};
 
     /*
      * TODO: If we ever need tlb_vaddr_to_host for thi= s target,
@@ -229,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
     assert(!probe);
 
     address &=3D TARGET_PAGE_MASK;
-    error_code =3D get_physical_address(env, &paddr, &a= mp;prot, &access_index,
+    error_code =3D get_physical_address(env, &paddr= , &prot, &access_index, &attrs,
                    =                    addres= s, access_type,
                    =                    mmu_id= x, &page_size);
     vaddr =3D address;
@@ -490,8 +491,8 @@ static inline int ultrasparc_tag_match(SparcTL= BEntry *tlb,
     return 0;
 }
 
-static int get_physical_address_data(CPUSPARCState *env,
-                    = ;                 hwaddr *physical,= int *prot,
+static int get_physical_address_data(CPUSPARCState *env, hwaddr *= physical,
+                   &= nbsp;                 int *prot, Me= mTxAttrs *attrs,
                    =                   target_ulong= address, int rw, int mmu_idx)
 {
     CPUState *cs =3D env_cpu(env);
@@ -608,8 +609,8 @@ static int get_physical_address_data(CPUSPARCS= tate *env,
     return 1;
 }
 
-static int get_physical_address_code(CPUSPARCState *env,
-                    = ;                 hwaddr *physical,= int *prot,
+static int get_physical_address_code(CPUSPARCState *env, hwaddr *= physical,
+                   &= nbsp;                 int *prot, Me= mTxAttrs *attrs,
                    =                   target_ulong= address, int mmu_idx)
 {
     CPUState *cs =3D env_cpu(env);
@@ -686,7 +687,7 @@ static int get_physical_address_code(CPUSPARCS= tate *env,
 }
 
 static int get_physical_address(CPUSPARCState *env, hwaddr *phys= ical,
-                    = ;            int *prot, int *access_index,
+                   &= nbsp;            int *prot, int *access_index= , MemTxAttrs *attrs,
                    =              target_ulong address, int r= w, int mmu_idx,
                    =              target_ulong *page_size)
 {
@@ -716,11 +717,11 @@ static int get_physical_address(CPUSPARCStat= e *env, hwaddr *physical,
     }
 
     if (rw =3D=3D 2) {
-        return get_physical_address_code(env, phy= sical, prot, address,
+        return get_physical_address_code(env,= physical, prot, attrs, address,
                    =                      = ; mmu_idx);
     } else {
-        return get_physical_address_data(env, phy= sical, prot, address, rw,
-                    = ;                     mmu= _idx);
+        return get_physical_address_data(env,= physical, prot, attrs, address,
+                   &= nbsp;                    = rw, mmu_idx);
     }
 }
 
@@ -734,10 +735,11 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr = address, int size,
     target_ulong vaddr;
     hwaddr paddr;
     target_ulong page_size;
+    MemTxAttrs attrs =3D {};
     int error_code =3D 0, prot, access_index;
 
     address &=3D TARGET_PAGE_MASK;
-    error_code =3D get_physical_address(env, &paddr, &a= mp;prot, &access_index,
+    error_code =3D get_physical_address(env, &paddr= , &prot, &access_index, &attrs,
                    =                    addres= s, access_type,
                    =                    mmu_id= x, &page_size);
     if (likely(error_code =3D=3D 0)) {
@@ -747,7 +749,8 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr ad= dress, int size,
                    =                 env->dmmu.mmu_pr= imary_context,
                    =                 env->dmmu.mmu_se= condary_context);
 
-        tlb_set_page(cs, vaddr, paddr, prot, mmu_= idx, page_size);
+        tlb_set_page_with_attrs(cs, vaddr, pa= ddr, attrs, prot, mmu_idx,
+                   &= nbsp;            page_size);
         return true;
     }
     if (probe) {
@@ -849,9 +852,10 @@ static int cpu_sparc_get_phys_page(CPUSPARCSt= ate *env, hwaddr *phys,
 {
     target_ulong page_size;
     int prot, access_index;
+    MemTxAttrs attrs =3D {};
 
-    return get_physical_address(env, phys, &prot, &= access_index, addr, rw,
-                    = ;            mmu_idx, &page_size);
+    return get_physical_address(env, phys, &prot, &= amp;access_index, &attrs, addr,
+                   &= nbsp;            rw, mmu_idx, &page_size)= ;
 }
 
 #if defined(TARGET_SPARC64)
-- 
1.8.3.1

​

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boundary="===============6650112555685555634==" Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" --===============6650112555685555634== Content-Language: en-AU Content-Type: multipart/alternative; boundary="_000_156516694118641868btcom_" --_000_156516694118641868btcom_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable This bit configures endianness of PCI MMIO devices. It is used by Solaris and OpenBSD sunhme drivers. Tested working on OpenBSD. Unfortunately Solaris 10 had a unrelated keyboard issue blocking testing... another inch towards Solaris 10 on SPARC64 =3D) Signed-off-by: Tony Nguyen Reviewed-by: Richard Henderson --- target/sparc/cpu.h | 2 ++ target/sparc/mmu_helper.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 1406f0b..c6bafa8 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -275,6 +275,7 @@ enum { #define TTE_VALID_BIT (1ULL << 63) #define TTE_NFO_BIT (1ULL << 60) +#define TTE_IE_BIT (1ULL << 59) #define TTE_USED_BIT (1ULL << 41) #define TTE_LOCKED_BIT (1ULL << 6) #define TTE_SIDEEFFECT_BIT (1ULL << 3) @@ -291,6 +292,7 @@ enum { #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) +#define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 826e14b..77dc86a 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -537,6 +537,10 @@ static int get_physical_address_data(CPUSPARCState *en= v, hwaddr *physical, if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical= )) { int do_fault =3D 0; + if (TTE_IS_IE(env->dtlb[i].tte)) { + attrs->byte_swap =3D true; + } + /* access ok? */ /* multiple bits in SFSR.FT may be set on TT_DFAULT */ if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) { @@ -792,7 +796,7 @@ void dump_mmu(CPUSPARCState *env) } if (TTE_IS_VALID(env->dtlb[i].tte)) { qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx" - ", %s, %s, %s, %s, ctx %" PRId64 " %s\n", + ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n= ", i, env->dtlb[i].tag & (uint64_t)~0x1fffULL, TTE_PA(env->dtlb[i].tte), @@ -801,6 +805,8 @@ void dump_mmu(CPUSPARCState *env) TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", TTE_IS_LOCKED(env->dtlb[i].tte) ? "locked" : "unlocked", + TTE_IS_IE(env->dtlb[i].tte) ? + "yes" : "no", env->dtlb[i].tag & (uint64_t)0x1fffULL, TTE_IS_GLOBAL(env->dtlb[i].tte) ? "global" : "local"); -- 1.8.3.1 ? --_000_156516694118641868btcom_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

This bit configures endianness of PCI= MMIO devices. It is used by
Solaris and OpenBSD sunhme drivers.

Tested working on OpenBSD.

Unfortunately Solaris 10 had a unrelated keyboard issue blocking
testing... another inch towards Solaris 10 on SPARC64 =3D)

Signed-off-by: Tony Nguyen <tony.nguyen@bt.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/cpu.h        | 2 ++
 target/sparc/mmu_helper.c | 8 +++++++= ;-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 1406f0b..c6bafa8 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -275,6 +275,7 @@ enum {
 
 #define TTE_VALID_BIT       (1ULL << 63)
 #define TTE_NFO_BIT         (1ULL << 6= 0)
+#define TTE_IE_BIT          (1ULL <&l= t; 59)
 #define TTE_USED_BIT        (1ULL << 4= 1)
 #define TTE_LOCKED_BIT      (1ULL <<  = 6)
 #define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
@@ -291,6 +292,7 @@ enum {
 
 #define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 #define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)<= /div>
+#define TTE_IS_IE(tte)      ((tte) & TTE_IE_BI= T)
 #define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)=
 #define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)<= /div>
diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 826e14b..77dc86a 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -537,6 +537,10 @@ static int get_physical_address_data(CPUSPARC= State *env, hwaddr *physical,
         if (ultrasparc_tag_match(&env-&g= t;dtlb[i], address, context, physical)) {
             int do_fault =3D 0;
 
+            if (TTE_IS_IE(env->d= tlb[i].tte)) {
+                attrs->= ;byte_swap =3D true;
+            }
+
             /* access ok? */
             /* multiple bits in SF= SR.FT may be set on TT_DFAULT */
             if (TTE_IS_PRIV(env-&g= t;dtlb[i].tte) && is_user) {
@@ -792,7 +796,7 @@ void dump_mmu(CPUSPARCState *env)
             }
             if (TTE_IS_VALID(env-&= gt;dtlb[i].tte)) {
                 qemu_pri= ntf("[%02u] VA: %" PRIx64 ", PA: %llx"
-                    = ;        ", %s, %s, %s, %s, ctx %" PRId64 &qu= ot; %s\n",
+                   &= nbsp;        ", %s, %s, %s, %s, ie %s, ctx %"= PRId64 " %s\n",
                    =          i,
                    =          env->dtlb[i].tag & (uint64_t)~0x1f= ffULL,
                    =          TTE_PA(env->dtlb[i].tte),
@@ -801,6 +805,8 @@ void dump_mmu(CPUSPARCState *env)
                    =          TTE_IS_W_OK(env->dtlb[i].tte) ? "= RW" : "RO",
                    =          TTE_IS_LOCKED(env->dtlb[i].tte) ?
                    =          "locked" : "unlocked"= ,
+                   &= nbsp;        TTE_IS_IE(env->dtlb[i].tte) ?
+                   &= nbsp;        "yes" : "no",
                    =          env->dtlb[i].tag & (uint64_t)0x1ff= fULL,
                    =          TTE_IS_GLOBAL(env->dtlb[i].tte) ?
                    =          "global" : "local");<= /div>
-- 
1.8.3.1

​


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