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([45.12.25.238]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9d6e5c52b3sm66307566b.30.2026.04.10.02.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 02:38:31 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775813912; x=1776418712; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=QxciCGjMhtZXe5VYflJrqx8ULRUS5CvVj0n9IlAzSp4=; b=ULUbGzNK1GuUtNDVcEKfTMcadO0ClK1dg7qC+6QTM3zE3rQTRDj5LTCLqUFAl1cv/+ OwloOfhhfX+I36tGvwK8ALJoyKzUR45vK+NWBlaLtTg1G86AktzsVLZDiYBegWuFYCmj DwIwr7GZ0O41V0kaEsVm278tP0mW6wjS2MSTD21ktQar8R0fJqSvDGUCySSYBR/3Hbug u7rsICuhmbfR3GxPq0/EOk8uH1XyZbniBGkjXoQ2RKTVdAv1olSyPeLjcMzHYJOVr9Wj qFi6LmuwmfGNPO651PF65ogyUyj78fY9hLAFPJfUwhHG5cvbSFcJFKrMyIdsfFecI1N0 oKgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775813912; x=1776418712; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=QxciCGjMhtZXe5VYflJrqx8ULRUS5CvVj0n9IlAzSp4=; b=RmZdA7Drzt7ZnMDzpIitS9hvghzdBI2WcVByeg4Ku6peyeoW+p6HxUSk+lupIbVxTn +sizTPTJBNpe0HQGvigdb9CZN82qODRT/taC2Wmm0J7BMO08MTgA+MYOVYhbsRojC2FL Dr8fTyebmg7Nd4CqsOKhYU4J6WxoiilDvmd5CzIL6qPOu5krcRJaasMX7uHx9EBwqqQG HAw/I7unLvF/qS3qyrt4Dan5z/E3tk53LwAXxkiaekWiZhkW/izeO22LCE39gUlVgIux n1yp3q2Vy7GJjdhIgBeI+HFSvnqoHAJt/Jsukxk73z16RjvZaL0BJPNpyaBjGSlLuUz9 c4wQ== X-Gm-Message-State: AOJu0YyStTvJ1xjFKR4dFv25KpHuXcnVx5UK404qaVOlaBZohj+mFCiv o1RVeAkIick4UE8wl5umbFVhDFRr5nmJmrPCTLCPjhLl2o3DAru5vMbw+OCW9SWn X-Gm-Gg: AeBDiesbzbwOcchTy/KT9ddRZg7de1sa5JOjj1vSPIzZQAdH/qfB0imz/nLam6YhQna 9E4nJGHBO+J0bJFK92uMs8P8mNWDaxAvyo2z2WqF7UJOq9GDhgIM5jF3CssCcblkKqvJGXWzEIb tsms6R+VYE+N5i5cJ3Wzf1DCjv8I5k3j5XUn/I3dJUXamVOhX7TCNNWms8jT6MINrXR7H07ZZW+ 8NWC7GGCrvWdHxdQZscSFOx7mXPzr8aIWTAo4E/4H6ba0orp9aQT4QRbEAf7/0KUWke72xECzWI CWS6lPFiL9j1sWhYzwNLvIVffNKvyqAOpPGIpeh6MomCf2VlN3lRLR4R0l833vZb0dTmca/XA7/ fGU/rCvwyLRvgW8JyEBDQgOOc8N7wx2oRjW7cJi5m6KP7/msCzMDgv0ccti2b0oDPjDMDkYh1UB VWJ0lK5XtMv8+HPLdjRtwu/+4vXJ4= X-Received: by 2002:a17:907:a392:b0:b96:eee1:bb66 with SMTP id a640c23a62f3a-b9d7267ad9dmr146723166b.10.1775813911606; Fri, 10 Apr 2026 02:38:31 -0700 (PDT) From: Mykola Kvach To: xen-devel@lists.xenproject.org Cc: Mykola Kvach , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH] xen/arm: gic-v2: disable interrupt bypass on CPU shutdown Date: Fri, 10 Apr 2026 12:36:15 +0300 Message-ID: <459cf46204e86ed3a2ffd79ae649b1a2051f5204.1775812563.git.mykola_kvach@epam.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1775813912-BCF5B0B1-DB3B44AB/0/0 X-purgate-type: clean X-purgate-size: 3034 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1775813940652154100 Content-Type: text/plain; charset="utf-8" From: Mykola Kvach The GICv2 CPU shutdown path currently writes 0 to GICC_CTLR. Per IHI0048B.b section 2.3.1, clearing IRQBypDisGrp{0,1} and FIQBypDisGrp{0,1} selects bypass rather than deasserted interrupt outputs when the CPU interface stops driving them. Tables 2-2 and 2-3 show that a zeroed GICC_CTLR can fall back to the legacy IRQ/FIQ inputs instead of fully disabling the interface. Fix this by reading GICC_CTLR, setting the bypass-disable bits, and clearing both group-enable bits before writing the value back. Keep the existing GICC_CTL_ENABLE definition for the init path and use a separate mask for the shutdown-side group-enable handling. Section 2.3.2 also states that wakeup event signals remain available even when both GIC interrupt signaling and interrupt bypass are disabled, so disabling bypass does not break the power-management use case, i.e. suspend modes. Fixes: 5e40a1b4351e ("arm: SMP CPU shutdown") Signed-off-by: Mykola Kvach --- xen/arch/arm/gic-v2.c | 7 ++++++- xen/arch/arm/include/asm/gic.h | 21 +++++++++++++++++++-- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index b23e72a3d0..22aa25bad0 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -408,7 +408,12 @@ static void gicv2_cpu_init(void) =20 static void gicv2_cpu_disable(void) { - writel_gicc(0x0, GICC_CTLR); + uint32_t ctlr =3D readl_gicc(GICC_CTLR); + + ctlr |=3D GICC_CTL_BYP_DIS_MASK; + ctlr &=3D ~GICC_CTL_ENABLE_GRP_MASK; + + writel_gicc(ctlr, GICC_CTLR); } =20 static void gicv2_hyp_init(void) diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h index 8e713aa477..da285adb83 100644 --- a/xen/arch/arm/include/asm/gic.h +++ b/xen/arch/arm/include/asm/gic.h @@ -102,8 +102,25 @@ #define GICD_TYPE_SEC 0x400 #define GICD_TYPER_DVIS (1U << 18) =20 -#define GICC_CTL_ENABLE 0x1 -#define GICC_CTL_EOI (0x1 << 9) +/* + * Keep the legacy name for bit[0]. In the Non-secure view of a GICv2 with + * Security Extensions this is the Group 1 enable bit; otherwise it is the + * Group 0. + */ +#define GICC_CTL_ENABLE (0x1 << 0) +/* Bit[1] is the second group-enable bit when separate group enables exist= . */ +#define GICC_CTL_ENABLE_GRP1 (0x1 << 1) +#define GICC_CTL_FIQBypDisGrp0 (0x1 << 5) +#define GICC_CTL_IRQBypDisGrp0 (0x1 << 6) +#define GICC_CTL_FIQBypDisGrp1 (0x1 << 7) +#define GICC_CTL_IRQBypDisGrp1 (0x1 << 8) +#define GICC_CTL_EOI (0x1 << 9) + +/* Shutdown clears both possible group-enable bits, regardless of layout. = */ +#define GICC_CTL_ENABLE_GRP_MASK (GICC_CTL_ENABLE | GICC_CTL_ENABLE_GRP1) +#define GICC_CTL_BYP_DIS_MASK \ + (GICC_CTL_FIQBypDisGrp0 | GICC_CTL_IRQBypDisGrp0 | \ + GICC_CTL_FIQBypDisGrp1 | GICC_CTL_IRQBypDisGrp1) =20 #define GICC_IA_IRQ 0x03ff #define GICC_IA_CPU_MASK 0x1c00 --=20 2.43.0