From nobody Thu Sep 19 16:08:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 172224363690169.50211931206002; Mon, 29 Jul 2024 02:00:36 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.766470.1176967 (Exim 4.92) (envelope-from ) id 1sYMEv-0000t3-Q2; Mon, 29 Jul 2024 09:00:21 +0000 Received: by outflank-mailman (output) from mailman id 766470.1176967; Mon, 29 Jul 2024 09:00:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sYMEv-0000q0-Jq; Mon, 29 Jul 2024 09:00:21 +0000 Received: by outflank-mailman (input) for mailman id 766470; Mon, 29 Jul 2024 09:00:20 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1sYMEu-0000M4-6g for xen-devel@lists.xenproject.org; Mon, 29 Jul 2024 09:00:20 +0000 Received: from support.bugseng.com (mail.bugseng.com [162.55.131.47]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id f9e8979b-4d88-11ef-8776-851b0ebba9a2; Mon, 29 Jul 2024 11:00:17 +0200 (CEST) Received: from truciolo.homenet.telecomitalia.it (host-87-20-207-105.retail.telecomitalia.it [87.20.207.105]) by support.bugseng.com (Postfix) with ESMTPSA id 302264EE075A; Mon, 29 Jul 2024 11:00:17 +0200 (CEST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f9e8979b-4d88-11ef-8776-851b0ebba9a2 From: Federico Serafini To: xen-devel@lists.xenproject.org Cc: consulting@bugseng.com, Federico Serafini , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [XEN PATCH v5 2/8] x86/vpmu: address violations of MISRA C Rule 16.3 Date: Mon, 29 Jul 2024 11:00:03 +0200 Message-Id: <4130e1f7f7c32cff1d3c8887febe0ed3793f11c1.1722239813.git.federico.serafini@bugseng.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZM-MESSAGEID: 1722243638507116600 Content-Type: text/plain; charset="utf-8" Add missing break statements to address violations of MISRA C Rule 16.3: "An unconditional `break' statement shall terminate every switch-clause". No functional change. Signed-off-by: Federico Serafini Reviewed-by: Stefano Stabellini Reviewed-by: Jan Beulich --- xen/arch/x86/cpu/vpmu.c | 3 +++ xen/arch/x86/cpu/vpmu_intel.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c index a7bc0cd1fc..b2ba999412 100644 --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -663,6 +663,8 @@ long do_xenpmu_op( =20 if ( pmu_params.version.maj !=3D XENPMU_VER_MAJ ) return -EINVAL; + + break; } =20 switch ( op ) @@ -776,6 +778,7 @@ long do_xenpmu_op( =20 default: ret =3D -EINVAL; + break; } =20 return ret; diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index cd414165df..26dd3a9358 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -666,6 +666,7 @@ static int cf_check core2_vpmu_do_wrmsr(unsigned int ms= r, uint64_t msr_content) =20 xen_pmu_cntr_pair[tmp].control =3D msr_content; } + break; } =20 if ( type !=3D MSR_TYPE_GLOBAL ) @@ -713,6 +714,7 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int ms= r, uint64_t *msr_content) break; default: rdmsrl(msr, *msr_content); + break; } } else if ( msr =3D=3D MSR_IA32_MISC_ENABLE ) --=20 2.34.1