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charset="utf-8" This follows Linux commit de09cdd09fa1 ("intel_idle: stop exposing platform acronyms in sysfs"), but their main justifications (sysfs exposure and similarity with acpi-idle) don't apply to us. The field is only used in a single printk() right now, but having the platform tags there isn't useful either. Requested-by: Roger Pau Monn=C3=A9 Signed-off-by: Jan Beulich --- v2: New. --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -134,25 +134,25 @@ static const struct cpuidle_state { */ static const struct cpuidle_state nehalem_cstates[] =3D { { - .name =3D "C1-NHM", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 3, .target_residency =3D 6, }, { - .name =3D "C1E-NHM", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-NHM", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 20, .target_residency =3D 80, }, { - .name =3D "C6-NHM", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 200, .target_residency =3D 800, @@ -162,31 +162,31 @@ static const struct cpuidle_state nehale =20 static const struct cpuidle_state snb_cstates[] =3D { { - .name =3D "C1-SNB", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-SNB", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-SNB", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 80, .target_residency =3D 211, }, { - .name =3D "C6-SNB", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 104, .target_residency =3D 345, }, { - .name =3D "C7-SNB", + .name =3D "C7", .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 109, .target_residency =3D 345, @@ -196,31 +196,31 @@ static const struct cpuidle_state snb_cs =20 static const struct cpuidle_state byt_cstates[] =3D { { - .name =3D "C1-BYT", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C6N-BYT", + .name =3D "C6N", .flags =3D MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 300, .target_residency =3D 275, }, { - .name =3D "C6S-BYT", + .name =3D "C6S", .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 500, .target_residency =3D 560, }, { - .name =3D "C7-BYT", + .name =3D "C7", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 1200, .target_residency =3D 4000, }, { - .name =3D "C7S-BYT", + .name =3D "C7S", .flags =3D MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 10000, .target_residency =3D 20000, @@ -230,31 +230,31 @@ static const struct cpuidle_state byt_cs =20 static const struct cpuidle_state cht_cstates[] =3D { { - .name =3D "C1-CHT", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C6N-CHT", + .name =3D "C6N", .flags =3D MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 80, .target_residency =3D 275, }, { - .name =3D "C6S-CHT", + .name =3D "C6S", .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 200, .target_residency =3D 560, }, { - .name =3D "C7-CHT", + .name =3D "C7", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 1200, .target_residency =3D 4000, }, { - .name =3D "C7S-CHT", + .name =3D "C7S", .flags =3D MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 10000, .target_residency =3D 20000, @@ -264,31 +264,31 @@ static const struct cpuidle_state cht_cs =20 static const struct cpuidle_state ivb_cstates[] =3D { { - .name =3D "C1-IVB", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-IVB", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-IVB", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 59, .target_residency =3D 156, }, { - .name =3D "C6-IVB", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 80, .target_residency =3D 300, }, { - .name =3D "C7-IVB", + .name =3D "C7", .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 87, .target_residency =3D 300, @@ -298,25 +298,25 @@ static const struct cpuidle_state ivb_cs =20 static const struct cpuidle_state ivt_cstates[] =3D { { - .name =3D "C1-IVT", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-IVT", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 80, }, { - .name =3D "C3-IVT", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 59, .target_residency =3D 156, }, { - .name =3D "C6-IVT", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 82, .target_residency =3D 300, @@ -326,25 +326,25 @@ static const struct cpuidle_state ivt_cs =20 static const struct cpuidle_state ivt_cstates_4s[] =3D { { - .name =3D "C1-IVT-4S", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-IVT-4S", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 250, }, { - .name =3D "C3-IVT-4S", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 59, .target_residency =3D 300, }, { - .name =3D "C6-IVT-4S", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 84, .target_residency =3D 400, @@ -354,25 +354,25 @@ static const struct cpuidle_state ivt_cs =20 static const struct cpuidle_state ivt_cstates_8s[] =3D { { - .name =3D "C1-IVT-8S", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-IVT-8S", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 500, }, { - .name =3D "C3-IVT-8S", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 59, .target_residency =3D 600, }, { - .name =3D "C6-IVT-8S", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 88, .target_residency =3D 700, @@ -382,49 +382,49 @@ static const struct cpuidle_state ivt_cs =20 static const struct cpuidle_state hsw_cstates[] =3D { { - .name =3D "C1-HSW", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-HSW", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-HSW", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 33, .target_residency =3D 100, }, { - .name =3D "C6-HSW", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 133, .target_residency =3D 400, }, { - .name =3D "C7s-HSW", + .name =3D "C7s", .flags =3D MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 166, .target_residency =3D 500, }, { - .name =3D "C8-HSW", + .name =3D "C8", .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 300, .target_residency =3D 900, }, { - .name =3D "C9-HSW", + .name =3D "C9", .flags =3D MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 600, .target_residency =3D 1800, }, { - .name =3D "C10-HSW", + .name =3D "C10", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 2600, .target_residency =3D 7700, @@ -434,49 +434,49 @@ static const struct cpuidle_state hsw_cs =20 static const struct cpuidle_state bdw_cstates[] =3D { { - .name =3D "C1-BDW", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-BDW", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-BDW", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 40, .target_residency =3D 100, }, { - .name =3D "C6-BDW", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 133, .target_residency =3D 400, }, { - .name =3D "C7s-BDW", + .name =3D "C7s", .flags =3D MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 166, .target_residency =3D 500, }, { - .name =3D "C8-BDW", + .name =3D "C8", .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 300, .target_residency =3D 900, }, { - .name =3D "C9-BDW", + .name =3D "C9", .flags =3D MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 600, .target_residency =3D 1800, }, { - .name =3D "C10-BDW", + .name =3D "C10", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 2600, .target_residency =3D 7700, @@ -486,49 +486,49 @@ static const struct cpuidle_state bdw_cs =20 static struct cpuidle_state __read_mostly skl_cstates[] =3D { { - .name =3D "C1-SKL", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-SKL", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C3-SKL", + .name =3D "C3", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 70, .target_residency =3D 100, }, { - .name =3D "C6-SKL", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 85, .target_residency =3D 200, }, { - .name =3D "C7s-SKL", + .name =3D "C7s", .flags =3D MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 124, .target_residency =3D 800, }, { - .name =3D "C8-SKL", + .name =3D "C8", .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 200, .target_residency =3D 800, }, { - .name =3D "C9-SKL", + .name =3D "C9", .flags =3D MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 480, .target_residency =3D 5000, }, { - .name =3D "C10-SKL", + .name =3D "C10", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 890, .target_residency =3D 5000, @@ -538,19 +538,19 @@ static struct cpuidle_state __read_mostl =20 static struct cpuidle_state __read_mostly skx_cstates[] =3D { { - .name =3D "C1-SKX", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-SKX", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C6-SKX", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 133, .target_residency =3D 600, @@ -560,19 +560,19 @@ static struct cpuidle_state __read_mostl =20 static const struct cpuidle_state icx_cstates[] =3D { { - .name =3D "C1-ICX", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 1, }, { - .name =3D "C1E-ICX", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 4, .target_residency =3D 4, }, { - .name =3D "C6-ICX", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 170, .target_residency =3D 600, @@ -582,25 +582,25 @@ static const struct cpuidle_state icx_cs =20 static const struct cpuidle_state atom_cstates[] =3D { { - .name =3D "C1E-ATM", + .name =3D "C1E", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C2-ATM", + .name =3D "C2", .flags =3D MWAIT2flg(0x10), .exit_latency =3D 20, .target_residency =3D 80, }, { - .name =3D "C4-ATM", + .name =3D "C4", .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 100, .target_residency =3D 400, }, { - .name =3D "C6-ATM", + .name =3D "C6", .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 140, .target_residency =3D 560, @@ -610,31 +610,31 @@ static const struct cpuidle_state atom_c =20 static const struct cpuidle_state tangier_cstates[] =3D { { - .name =3D "C1-TNG", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 4, }, { - .name =3D "C4-TNG", + .name =3D "C4", .flags =3D MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 100, .target_residency =3D 400, }, { - .name =3D "C6-TNG", + .name =3D "C6", .flags =3D MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 140, .target_residency =3D 560, }, { - .name =3D "C7-TNG", + .name =3D "C7", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 1200, .target_residency =3D 4000, }, { - .name =3D "C9-TNG", + .name =3D "C9", .flags =3D MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 10000, .target_residency =3D 20000, @@ -644,13 +644,13 @@ static const struct cpuidle_state tangie =20 static const struct cpuidle_state avn_cstates[] =3D { { - .name =3D "C1-AVN", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C6-AVN", + .name =3D "C6", .flags =3D MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 15, .target_residency =3D 45, @@ -660,13 +660,13 @@ static const struct cpuidle_state avn_cs =20 static const struct cpuidle_state knl_cstates[] =3D { { - .name =3D "C1-KNL", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 1, .target_residency =3D 2, }, { - .name =3D "C6-KNL", + .name =3D "C6", .flags =3D MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 120, .target_residency =3D 500, @@ -676,43 +676,43 @@ static const struct cpuidle_state knl_cs =20 static struct cpuidle_state __read_mostly bxt_cstates[] =3D { { - .name =3D "C1-BXT", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-BXT", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C6-BXT", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 133, .target_residency =3D 133, }, { - .name =3D "C7s-BXT", + .name =3D "C7s", .flags =3D MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 155, .target_residency =3D 155, }, { - .name =3D "C8-BXT", + .name =3D "C8", .flags =3D MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 1000, .target_residency =3D 1000, }, { - .name =3D "C9-BXT", + .name =3D "C9", .flags =3D MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 2000, .target_residency =3D 2000, }, { - .name =3D "C10-BXT", + .name =3D "C10", .flags =3D MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 10000, .target_residency =3D 10000, @@ -722,19 +722,19 @@ static struct cpuidle_state __read_mostl =20 static const struct cpuidle_state dnv_cstates[] =3D { { - .name =3D "C1-DNV", + .name =3D "C1", .flags =3D MWAIT2flg(0x00), .exit_latency =3D 2, .target_residency =3D 2, }, { - .name =3D "C1E-DNV", + .name =3D "C1E", .flags =3D MWAIT2flg(0x01), .exit_latency =3D 10, .target_residency =3D 20, }, { - .name =3D "C6-DNV", + .name =3D "C6", .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, .exit_latency =3D 50, .target_residency =3D 500,