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mx.microsoft.com 1; spf=pass smtp.mailfrom=suse.com; dmarc=pass action=none header.from=suse.com; dkim=pass header.d=suse.com; arc=none Authentication-Results: xen.org; dkim=none (message not signed) header.d=none;xen.org; dmarc=none action=none header.from=suse.com; Subject: [PATCH v2 11/18] AMD/IOMMU: return old PTE from {set,clear}_iommu_pte_present() From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , Paul Durrant References: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Message-ID: <33819694-2787-4bd6-1830-6b4eb81cb4a1@suse.com> Date: Fri, 24 Sep 2021 11:51:40 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 In-Reply-To: <957f067b-9fe1-2350-4266-51982f09d3a9@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: FR0P281CA0089.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:1e::11) To VI1PR04MB5600.eurprd04.prod.outlook.com (2603:10a6:803:e7::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 38bf7131-378d-40b3-c1d6-08d97f40e937 X-MS-TrafficTypeDiagnostic: VI1PR0401MB2446: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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charset="utf-8" In order to free intermediate page tables when replacing smaller mappings by a single larger one callers will need to know the full PTE. Flush indicators can be derived from this in the callers (and outside the locked regions). First split set_iommu_pte_present() from set_iommu_ptes_present(): Only the former needs to return the old PTE, while the latter (like also set_iommu_pde_present()) doesn't even need to return flush indicators. Then change return types/values and callers accordingly. Signed-off-by: Jan Beulich --- a/xen/drivers/passthrough/amd/iommu_map.c +++ b/xen/drivers/passthrough/amd/iommu_map.c @@ -31,30 +31,28 @@ static unsigned int pfn_to_pde_idx(unsig return idx; } =20 -static unsigned int clear_iommu_pte_present(unsigned long l1_mfn, - unsigned long dfn) +static union amd_iommu_pte clear_iommu_pte_present(unsigned long l1_mfn, + unsigned long dfn) { - union amd_iommu_pte *table, *pte; - unsigned int flush_flags; + union amd_iommu_pte *table, *pte, old; =20 table =3D map_domain_page(_mfn(l1_mfn)); pte =3D &table[pfn_to_pde_idx(dfn, 1)]; + old =3D *pte; =20 - flush_flags =3D pte->pr ? IOMMU_FLUSHF_modified : 0; write_atomic(&pte->raw, 0); =20 unmap_domain_page(table); =20 - return flush_flags; + return old; } =20 -static unsigned int set_iommu_pde_present(union amd_iommu_pte *pte, - unsigned long next_mfn, - unsigned int next_level, bool iw, - bool ir) +static void set_iommu_pde_present(union amd_iommu_pte *pte, + unsigned long next_mfn, + unsigned int next_level, + bool iw, bool ir) { - union amd_iommu_pte new =3D {}, old; - unsigned int flush_flags =3D IOMMU_FLUSHF_added; + union amd_iommu_pte new =3D {}; =20 /* * FC bit should be enabled in PTE, this helps to solve potential @@ -68,28 +66,42 @@ static unsigned int set_iommu_pde_presen new.next_level =3D next_level; new.pr =3D true; =20 - old.raw =3D read_atomic(&pte->raw); - old.ign0 =3D 0; - old.ign1 =3D 0; - old.ign2 =3D 0; + write_atomic(&pte->raw, new.raw); +} =20 - if ( old.pr && old.raw !=3D new.raw ) - flush_flags |=3D IOMMU_FLUSHF_modified; +static union amd_iommu_pte set_iommu_pte_present(unsigned long pt_mfn, + unsigned long dfn, + unsigned long next_mfn, + unsigned int level, + bool iw, bool ir) +{ + union amd_iommu_pte *table, *pde, old; =20 - write_atomic(&pte->raw, new.raw); + table =3D map_domain_page(_mfn(pt_mfn)); + pde =3D &table[pfn_to_pde_idx(dfn, level)]; + + old =3D *pde; + if ( !old.pr || old.next_level || + old.mfn !=3D next_mfn || + old.iw !=3D iw || old.ir !=3D ir ) + set_iommu_pde_present(pde, next_mfn, 0, iw, ir); + else + old.pr =3D false; /* signal "no change" to the caller */ =20 - return flush_flags; + unmap_domain_page(table); + + return old; } =20 -static unsigned int set_iommu_ptes_present(unsigned long pt_mfn, - unsigned long dfn, - unsigned long next_mfn, - unsigned int nr_ptes, - unsigned int pde_level, - bool iw, bool ir) +static void set_iommu_ptes_present(unsigned long pt_mfn, + unsigned long dfn, + unsigned long next_mfn, + unsigned int nr_ptes, + unsigned int pde_level, + bool iw, bool ir) { union amd_iommu_pte *table, *pde; - unsigned int page_sz, flush_flags =3D 0; + unsigned int page_sz; =20 table =3D map_domain_page(_mfn(pt_mfn)); pde =3D &table[pfn_to_pde_idx(dfn, pde_level)]; @@ -98,20 +110,18 @@ static unsigned int set_iommu_ptes_prese if ( (void *)(pde + nr_ptes) > (void *)table + PAGE_SIZE ) { ASSERT_UNREACHABLE(); - return 0; + return; } =20 while ( nr_ptes-- ) { - flush_flags |=3D set_iommu_pde_present(pde, next_mfn, 0, iw, ir); + set_iommu_pde_present(pde, next_mfn, 0, iw, ir); =20 ++pde; next_mfn +=3D page_sz; } =20 unmap_domain_page(table); - - return flush_flags; } =20 void amd_iommu_set_root_page_table(struct amd_iommu_dte *dte, @@ -284,6 +294,7 @@ int amd_iommu_map_page(struct domain *d, struct domain_iommu *hd =3D dom_iommu(d); int rc; unsigned long pt_mfn =3D 0; + union amd_iommu_pte old; =20 spin_lock(&hd->arch.mapping_lock); =20 @@ -320,12 +331,16 @@ int amd_iommu_map_page(struct domain *d, } =20 /* Install 4k mapping */ - *flush_flags |=3D set_iommu_ptes_present(pt_mfn, dfn_x(dfn), mfn_x(mfn= ), - 1, 1, (flags & IOMMUF_writable), - (flags & IOMMUF_readable)); + old =3D set_iommu_pte_present(pt_mfn, dfn_x(dfn), mfn_x(mfn), 1, + (flags & IOMMUF_writable), + (flags & IOMMUF_readable)); =20 spin_unlock(&hd->arch.mapping_lock); =20 + *flush_flags |=3D IOMMU_FLUSHF_added; + if ( old.pr ) + *flush_flags |=3D IOMMU_FLUSHF_modified; + return 0; } =20 @@ -334,6 +349,7 @@ int amd_iommu_unmap_page(struct domain * { unsigned long pt_mfn =3D 0; struct domain_iommu *hd =3D dom_iommu(d); + union amd_iommu_pte old =3D {}; =20 spin_lock(&hd->arch.mapping_lock); =20 @@ -355,11 +371,14 @@ int amd_iommu_unmap_page(struct domain * if ( pt_mfn ) { /* Mark PTE as 'page not present'. */ - *flush_flags |=3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn)); + old =3D clear_iommu_pte_present(pt_mfn, dfn_x(dfn)); } =20 spin_unlock(&hd->arch.mapping_lock); =20 + if ( old.pr ) + *flush_flags |=3D IOMMU_FLUSHF_modified; + return 0; } =20