From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619102645; cv=none; d=zohomail.com; s=zohoarc; b=iuA90JPI8Tg7VKeUHAOmxZf71HrT7h+VgfvfIe1TwFXRRFxK5hjFZc7QvaUyWkdBiO7MIXmN/KM5phMloiXjuh59EB2yjiuLk+hxC2b9m+ZNo547kfGpm6rExFsYHuannNOM+pFNAffyzyJQZfP72GDtlfw9hdfFmZ5ucwYwoLs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619102645; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sK0bwnN4IIuy+T0mgb6iypNUm85GbsitJEBd7v7Q3KI=; b=OJsPfXtkCADVZnxLUwwYWPa2mp71U4e7vmo6oFa9+9gu/nDBLTju3mxPHoYdpYebzB7n3eKEQyl73PaOd5coQuB1xK6/5uiMDty1t+h5UjFJ2mtg57zF6I6yN/wGMmttJNyzQZIjP91EVXc/Nal3qT7QJ2MS8Bg8paSIgllxL9k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=quarantine dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619102645039927.5725609153875; Thu, 22 Apr 2021 07:44:05 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.115458.220284 (Exim 4.92) (envelope-from ) id 1lZaYQ-00033S-LP; Thu, 22 Apr 2021 14:43:42 +0000 Received: by outflank-mailman (output) from mailman id 115458.220284; Thu, 22 Apr 2021 14:43:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZaYQ-00033L-H5; Thu, 22 Apr 2021 14:43:42 +0000 Received: by outflank-mailman (input) for mailman id 115458; Thu, 22 Apr 2021 14:43:40 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZaYO-00033G-JL for xen-devel@lists.xenproject.org; Thu, 22 Apr 2021 14:43:40 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 3f659f9b-de90-46f0-85a3-8b334f5be43d; Thu, 22 Apr 2021 14:43:39 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id D9CF6B16A; Thu, 22 Apr 2021 14:43:38 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3f659f9b-de90-46f0-85a3-8b334f5be43d X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102619; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sK0bwnN4IIuy+T0mgb6iypNUm85GbsitJEBd7v7Q3KI=; b=o9pqOblZqdpgj7gD9r17P1btYe4RR3hzFi2+eos+LI10hFnUEDKdPQ0Kt5sFdDIY3L9qH4 rJNOXTKm+7XZjhO4jdHxd9j5VuYRXoaJ8lC1T/4NkRk3vUGHUUua9BaKluQyo/S7yV0wZJ dgaFsoENPoq5YutGXA7kUvtDj+4e0k4= Subject: [PATCH v3 01/22] mm: introduce xvmalloc() et al and use for grant table allocations From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Ian Jackson , Julien Grall , Stefano Stabellini , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <69778de6-3b94-64d1-99d9-1a0fcfa503fd@suse.com> Date: Thu, 22 Apr 2021 16:43:39 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" All of the array allocations in grant_table_init() can exceed a page's worth of memory, which xmalloc()-based interfaces aren't really suitable for after boot. We also don't need any of these allocations to be physically contiguous.. Introduce interfaces dynamically switching between xmalloc() et al and vmalloc() et al, based on requested size, and use them instead. All the wrappers in the new header get cloned mostly verbatim from xmalloc.h, with the sole adjustment to switch unsigned long to size_t for sizes and to unsigned int for alignments. Signed-off-by: Jan Beulich --- v2: Actually edit a copy-and-pasted comment in xvmalloc.h which was meant to be edited from the beginning. --- I'm unconvinced of the mentioning of "physically contiguous" in the comment at the top of the new header: I don't think xmalloc() provides such a guarantee. Any use assuming so would look (latently) broken to me. --- a/xen/common/grant_table.c +++ b/xen/common/grant_table.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include @@ -1749,8 +1749,8 @@ gnttab_populate_status_frames(struct dom =20 if ( gt->status =3D=3D ZERO_BLOCK_PTR ) { - gt->status =3D xzalloc_array(grant_status_t *, - grant_to_status_frames(gt->max_grant_fr= ames)); + gt->status =3D xvzalloc_array(grant_status_t *, + grant_to_status_frames(gt->max_grant_f= rames)); if ( !gt->status ) { gt->status =3D ZERO_BLOCK_PTR; @@ -1780,7 +1780,7 @@ status_alloc_failed: } if ( !nr_status_frames(gt) ) { - xfree(gt->status); + xvfree(gt->status); gt->status =3D ZERO_BLOCK_PTR; } return -ENOMEM; @@ -1852,7 +1852,7 @@ gnttab_unpopulate_status_frames(struct d gt->nr_status_frames =3D 0; for ( i =3D 0; i < n; i++ ) free_xenheap_page(gt->status[i]); - xfree(gt->status); + xvfree(gt->status); gt->status =3D ZERO_BLOCK_PTR; =20 return 0; @@ -1966,21 +1966,22 @@ int grant_table_init(struct domain *d, i d->grant_table =3D gt; =20 /* Active grant table. */ - gt->active =3D xzalloc_array(struct active_grant_entry *, - max_nr_active_grant_frames(gt)); + gt->active =3D xvzalloc_array(struct active_grant_entry *, + max_nr_active_grant_frames(gt)); if ( gt->active =3D=3D NULL ) goto out; =20 /* Tracking of mapped foreign frames table */ if ( gt->max_maptrack_frames ) { - gt->maptrack =3D vzalloc(gt->max_maptrack_frames * sizeof(*gt->map= track)); + gt->maptrack =3D xvzalloc_array(struct grant_mapping *, + gt->max_maptrack_frames); if ( gt->maptrack =3D=3D NULL ) goto out; } =20 /* Shared grant table. */ - gt->shared_raw =3D xzalloc_array(void *, gt->max_grant_frames); + gt->shared_raw =3D xvzalloc_array(void *, gt->max_grant_frames); if ( gt->shared_raw =3D=3D NULL ) goto out; =20 @@ -3868,19 +3869,19 @@ grant_table_destroy( =20 for ( i =3D 0; i < nr_grant_frames(t); i++ ) free_xenheap_page(t->shared_raw[i]); - xfree(t->shared_raw); + xvfree(t->shared_raw); =20 for ( i =3D 0; i < nr_maptrack_frames(t); i++ ) free_xenheap_page(t->maptrack[i]); - vfree(t->maptrack); + xvfree(t->maptrack); =20 for ( i =3D 0; i < nr_active_grant_frames(t); i++ ) free_xenheap_page(t->active[i]); - xfree(t->active); + xvfree(t->active); =20 for ( i =3D 0; i < nr_status_frames(t); i++ ) free_xenheap_page(t->status[i]); - xfree(t->status); + xvfree(t->status); =20 xfree(t); d->grant_table =3D NULL; --- a/xen/common/vmap.c +++ b/xen/common/vmap.c @@ -7,6 +7,7 @@ #include #include #include +#include #include =20 static DEFINE_SPINLOCK(vm_lock); @@ -301,11 +302,29 @@ void *vzalloc(size_t size) return p; } =20 -void vfree(void *va) +static void _vfree(const void *va, unsigned int pages, enum vmap_region ty= pe) { - unsigned int i, pages; + unsigned int i; struct page_info *pg; PAGE_LIST_HEAD(pg_list); + + ASSERT(pages); + + for ( i =3D 0; i < pages; i++ ) + { + pg =3D vmap_to_page(va + i * PAGE_SIZE); + ASSERT(pg); + page_list_add(pg, &pg_list); + } + vunmap(va); + + while ( (pg =3D page_list_remove_head(&pg_list)) !=3D NULL ) + free_domheap_page(pg); +} + +void vfree(void *va) +{ + unsigned int pages; enum vmap_region type =3D VMAP_DEFAULT; =20 if ( !va ) @@ -317,18 +336,71 @@ void vfree(void *va) type =3D VMAP_XEN; pages =3D vm_size(va, type); } - ASSERT(pages); =20 - for ( i =3D 0; i < pages; i++ ) + _vfree(va, pages, type); +} + +void xvfree(void *va) +{ + unsigned int pages =3D vm_size(va, VMAP_DEFAULT); + + if ( pages ) + _vfree(va, pages, VMAP_DEFAULT); + else + xfree(va); +} + +void *_xvmalloc(size_t size, unsigned int align) +{ + ASSERT(align <=3D PAGE_SIZE); + return size <=3D PAGE_SIZE ? _xmalloc(size, align) : vmalloc(size); +} + +void *_xvzalloc(size_t size, unsigned int align) +{ + ASSERT(align <=3D PAGE_SIZE); + return size <=3D PAGE_SIZE ? _xzalloc(size, align) : vzalloc(size); +} + +void *_xvrealloc(void *va, size_t size, unsigned int align) +{ + size_t pages =3D vm_size(va, VMAP_DEFAULT); + void *ptr; + + ASSERT(align <=3D PAGE_SIZE); + + if ( !pages ) { - struct page_info *page =3D vmap_to_page(va + i * PAGE_SIZE); + if ( size <=3D PAGE_SIZE ) + return _xrealloc(va, size, align); =20 - ASSERT(page); - page_list_add(page, &pg_list); + ptr =3D vmalloc(size); + if ( ptr && va && va !=3D ZERO_BLOCK_PTR ) + { + /* + * xmalloc-based allocations up to PAGE_SIZE don't cross page + * boundaries. Therefore, without needing to know the exact + * prior allocation size, simply copy the entire tail of the + * page containing the earlier allocation. + */ + memcpy(ptr, va, PAGE_SIZE - PAGE_OFFSET(va)); + xfree(va); + } + } + else if ( pages =3D=3D PFN_UP(size) ) + ptr =3D va; + else + { + ptr =3D _xvmalloc(size, align); + if ( ptr ) + { + memcpy(ptr, va, min(size, pages << PAGE_SHIFT)); + vfree(va); + } + else if ( pages > PFN_UP(size) ) + ptr =3D va; } - vunmap(va); =20 - while ( (pg =3D page_list_remove_head(&pg_list)) !=3D NULL ) - free_domheap_page(pg); + return ptr; } #endif --- /dev/null +++ b/xen/include/xen/xvmalloc.h @@ -0,0 +1,73 @@ + +#ifndef __XVMALLOC_H__ +#define __XVMALLOC_H__ + +#include +#include + +/* + * Xen malloc/free-style interface for allocations possibly exceeding a pa= ge's + * worth of memory, as long as there's no need to have physically contiguo= us + * memory allocated. These should be used in preference to xmalloc() et al + * whenever the size is not known to be constrained to at most a single pa= ge. + */ + +/* Allocate space for typed object. */ +#define xvmalloc(_type) ((_type *)_xvmalloc(sizeof(_type), __alignof__(_ty= pe))) +#define xvzalloc(_type) ((_type *)_xvzalloc(sizeof(_type), __alignof__(_ty= pe))) + +/* Allocate space for array of typed objects. */ +#define xvmalloc_array(_type, _num) \ + ((_type *)_xvmalloc_array(sizeof(_type), __alignof__(_type), _num)) +#define xvzalloc_array(_type, _num) \ + ((_type *)_xvzalloc_array(sizeof(_type), __alignof__(_type), _num)) + +/* Allocate space for a structure with a flexible array of typed objects. = */ +#define xvzalloc_flex_struct(type, field, nr) \ + ((type *)_xvzalloc(offsetof(type, field[nr]), __alignof__(type))) + +#define xvmalloc_flex_struct(type, field, nr) \ + ((type *)_xvmalloc(offsetof(type, field[nr]), __alignof__(type))) + +/* Re-allocate space for a structure with a flexible array of typed object= s. */ +#define xvrealloc_flex_struct(ptr, field, nr) \ + ((typeof(ptr))_xvrealloc(ptr, offsetof(typeof(*(ptr)), field[nr]), \ + __alignof__(typeof(*(ptr))))) + +/* Allocate untyped storage. */ +#define xvmalloc_bytes(_bytes) _xvmalloc(_bytes, SMP_CACHE_BYTES) +#define xvzalloc_bytes(_bytes) _xvzalloc(_bytes, SMP_CACHE_BYTES) + +/* Free any of the above. */ +extern void xvfree(void *); + +/* Free an allocation, and zero the pointer to it. */ +#define XVFREE(p) do { \ + xvfree(p); \ + (p) =3D NULL; \ +} while ( false ) + +/* Underlying functions */ +extern void *_xvmalloc(size_t size, unsigned int align); +extern void *_xvzalloc(size_t size, unsigned int align); +extern void *_xvrealloc(void *ptr, size_t size, unsigned int align); + +static inline void *_xvmalloc_array( + size_t size, unsigned int align, unsigned long num) +{ + /* Check for overflow. */ + if ( size && num > UINT_MAX / size ) + return NULL; + return _xvmalloc(size * num, align); +} + +static inline void *_xvzalloc_array( + size_t size, unsigned int align, unsigned long num) +{ + /* Check for overflow. */ + if ( size && num > UINT_MAX / size ) + return NULL; + return _xvzalloc(size * num, align); +} + +#endif /* __XVMALLOC_H__ */ From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 22 Apr 2021 14:44:37 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 22b32c30-555e-4039-b98a-5e5c24665c90; Thu, 22 Apr 2021 14:44:36 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 28625B16A; Thu, 22 Apr 2021 14:44:36 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 22b32c30-555e-4039-b98a-5e5c24665c90 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102676; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CX7ycSIbHLxk9/beplw9uWXkdYfiG5DPYy83G5AM4JE=; b=rcA4yehWdnrNhng0HkIHI17UjFEXc9hI6PbENa4vqnKqE19m4FAG505qY7Ew/dLNlHe4U7 QkXQ9lUHaPKlMkgQNillDAcGZpSVslNfoJ4a8iq/d0RVENOHruxQw3LSTAmfKWCUCweDXk ooZFonzxWH73Oce3Z+oJqmFsXL9nlzY= Subject: [PATCH v3 02/22] x86/xstate: use xvzalloc() for save area allocation From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <1fec148f-a5b2-5102-a790-e908d6f040c9@suse.com> Date: Thu, 22 Apr 2021 16:44:36 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" This is in preparation for the area size exceeding a page's worth of space, as will happen with AMX as well as Architectural LBR. Signed-off-by: Jan Beulich Acked-by: Roger Pau Monn=C3=A9 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -522,7 +523,7 @@ int xstate_alloc_save_area(struct vcpu * =20 /* XSAVE/XRSTOR requires the save area be 64-byte-boundary aligned. */ BUILD_BUG_ON(__alignof(*save_area) < 64); - save_area =3D _xzalloc(size, __alignof(*save_area)); + save_area =3D _xvzalloc(size, __alignof(*save_area)); if ( save_area =3D=3D NULL ) return -ENOMEM; =20 @@ -543,8 +544,7 @@ int xstate_alloc_save_area(struct vcpu * =20 void xstate_free_save_area(struct vcpu *v) { - xfree(v->arch.xsave_area); - v->arch.xsave_area =3D NULL; + XVFREE(v->arch.xsave_area); } =20 static unsigned int _xstate_ctxt_size(u64 xcr0) From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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Thu, 22 Apr 2021 14:45:01 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 0e593b11-5b2c-4bc5-a34e-d21a9a229790; Thu, 22 Apr 2021 14:44:59 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 2C482AEC6; Thu, 22 Apr 2021 14:44:59 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 0e593b11-5b2c-4bc5-a34e-d21a9a229790 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102699; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7ruxsuA3j7K0oTuxQf62nTzbV9rQVNflxNyw+J58l9k=; b=De0JFItAh1GKFcSs4EuD/iOOaLQqmaMnkfKA8T5SWN2R6wQ3MVIvrN+puw6y8zCOtUTKBv IOA+5veSaZokCXXxQBsBARtXm/Rsb29+LvDSSrXDRK8d3MJ/ysCS+ZAWcg/rMG85n8Oehs VO8g9qH5HgopHADpdSHSBVX3I4pHCpc= Subject: [PATCH v3 03/22] x86/xstate: re-size save area when CPUID policy changes From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Ian Jackson , Julien Grall , Stefano Stabellini , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <8ba8f016-0aed-277b-bbea-80022d057791@suse.com> Date: Thu, 22 Apr 2021 16:44:59 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" vCPU-s get maximum size areas allocated initially. Hidden (and in particular default-off) features may allow for a smaller size area to suffice. Suggested-by: Andrew Cooper Signed-off-by: Jan Beulich --- v2: Use 1ul instead of 1ull. Re-base. --- This could be further shrunk if we used XSAVEC / if we really used XSAVES, as then we don't need to also cover the holes. But since we currently use neither of the two in reality, this would require more work than just adding the alternative size calculation here. Seeing that both vcpu_init_fpu() and cpuid_policy_updated() get called from arch_vcpu_create(), I'm not sure we really need this two-stage approach - the slightly longer period of time during which v->arch.xsave_area would remain NULL doesn't look all that problematic. But since xstate_alloc_save_area() gets called for idle vCPU-s, it has to stay anyway in some form, so the extra code churn may not be worth it. Instead of cpuid_policy_xcr0_max(), cpuid_policy_xstates() may be the interface to use here. But it remains to be determined whether the xcr0_accum field is meant to be inclusive of XSS (in which case it would better be renamed) or exclusive. Right now there's no difference as we don't support any XSS-controlled features. --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -281,7 +281,21 @@ void update_guest_memory_policy(struct v } } =20 -void domain_cpu_policy_changed(struct domain *d) +/* + * Called during vcpu construction, and each time the toolstack changes the + * CPUID configuration for the domain. + */ +static int __must_check cpuid_policy_updated(struct vcpu *v) +{ + int rc =3D xstate_update_save_area(v); + + if ( !rc && is_hvm_vcpu(v) ) + hvm_cpuid_policy_changed(v); + + return rc; +} + +int domain_cpu_policy_changed(struct domain *d) { const struct cpuid_policy *p =3D d->arch.cpuid; struct vcpu *v; @@ -439,13 +453,18 @@ void domain_cpu_policy_changed(struct do =20 for_each_vcpu ( d, v ) { - cpuid_policy_updated(v); + int rc =3D cpuid_policy_updated(v); + + if ( rc ) + return rc; =20 /* If PMU version is zero then the guest doesn't have VPMU */ if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && p->basic.pmu_version =3D=3D 0 ) vpmu_destroy(v); } + + return 0; } =20 #ifndef CONFIG_BIGMEM @@ -584,7 +603,7 @@ int arch_vcpu_create(struct vcpu *v) { vpmu_initialise(v); =20 - cpuid_policy_updated(v); + rc =3D cpuid_policy_updated(v); } =20 return rc; @@ -859,11 +878,11 @@ int arch_domain_create(struct domain *d, */ d->arch.x87_fip_width =3D cpu_has_fpu_sel ? 0 : 8; =20 - domain_cpu_policy_changed(d); - d->arch.msr_relaxed =3D config->arch.misc_flags & XEN_X86_MSR_RELAXED; =20 - return 0; + rc =3D domain_cpu_policy_changed(d); + if ( !rc ) + return 0; =20 fail: d->is_dying =3D DOMDYING_dead; @@ -2471,16 +2490,6 @@ int domain_relinquish_resources(struct d return 0; } =20 -/* - * Called during vcpu construction, and each time the toolstack changes the - * CPUID configuration for the domain. - */ -void cpuid_policy_updated(struct vcpu *v) -{ - if ( is_hvm_vcpu(v) ) - hvm_cpuid_policy_changed(v); -} - void arch_dump_domain_info(struct domain *d) { paging_dump_domain_info(d); --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -89,7 +89,7 @@ static int update_domain_cpu_policy(stru recalculate_cpuid_policy(d); =20 /* Recalculate relevant dom/vcpu state now the policy has changed. */ - domain_cpu_policy_changed(d); + ret =3D domain_cpu_policy_changed(d); =20 out: /* Free whichever cpuid/msr structs are not installed in struct domain= . */ --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -542,6 +542,41 @@ int xstate_alloc_save_area(struct vcpu * return 0; } =20 +int xstate_update_save_area(struct vcpu *v) +{ + unsigned int i, size, old; + struct xsave_struct *save_area; + uint64_t xcr0_max =3D cpuid_policy_xcr0_max(v->domain->arch.cpuid); + + ASSERT(!is_idle_vcpu(v)); + + if ( !cpu_has_xsave ) + return 0; + + if ( v->arch.xcr0_accum & ~xcr0_max ) + return -EBUSY; + + for ( size =3D old =3D XSTATE_AREA_MIN_SIZE, i =3D 2; i < xstate_featu= res; ++i ) + { + if ( xcr0_max & (1ul << i) ) + size =3D max(size, xstate_offsets[i] + xstate_sizes[i]); + if ( v->arch.xcr0_accum & (1ul << i) ) + old =3D max(old, xstate_offsets[i] + xstate_sizes[i]); + } + + save_area =3D _xvrealloc(v->arch.xsave_area, size, __alignof(*save_are= a)); + if ( !save_area ) + return -ENOMEM; + + ASSERT(old <=3D size); + memset((void *)save_area + old, 0, size - old); + + v->arch.xsave_area =3D save_area; + v->arch.fpu_ctxt =3D &v->arch.xsave_area->fpu_sse; + + return 0; +} + void xstate_free_save_area(struct vcpu *v) { XVFREE(v->arch.xsave_area); --- a/xen/include/asm-x86/domain.h +++ b/xen/include/asm-x86/domain.h @@ -78,8 +78,6 @@ void toggle_guest_mode(struct vcpu *); /* x86/64: toggle guest page tables between kernel and user modes. */ void toggle_guest_pt(struct vcpu *); =20 -void cpuid_policy_updated(struct vcpu *v); - /* * Initialise a hypercall-transfer page. The given pointer must be mapped * in Xen virtual address space (accesses are not validated or checked). @@ -670,7 +668,7 @@ struct guest_memory_policy void update_guest_memory_policy(struct vcpu *v, struct guest_memory_policy *policy); =20 -void domain_cpu_policy_changed(struct domain *d); +int __must_check domain_cpu_policy_changed(struct domain *d); =20 bool update_runstate_area(struct vcpu *); bool update_secondary_system_time(struct vcpu *, --- a/xen/include/asm-x86/xstate.h +++ b/xen/include/asm-x86/xstate.h @@ -106,6 +106,7 @@ void compress_xsave_states(struct vcpu * /* extended state init and cleanup functions */ void xstate_free_save_area(struct vcpu *v); int xstate_alloc_save_area(struct vcpu *v); +int xstate_update_save_area(struct vcpu *v); void xstate_init(struct cpuinfo_x86 *c); unsigned int xstate_ctxt_size(u64 xcr0); =20 From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 22 Apr 2021 14:45:32 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id c82a5c0c-1aac-421f-a9af-49f2287862ba; Thu, 22 Apr 2021 14:45:27 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id D1D60ABB1; Thu, 22 Apr 2021 14:45:26 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c82a5c0c-1aac-421f-a9af-49f2287862ba X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102726; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YTf7yEdgV9RjTpaGYCRR3T6Rl7rw+jl6IuRZaeG5MhQ=; b=ZqMrAy6T00gH0krJlMdW+ccEdJmDHv/RsnxZcJ81EiVvSOcb+Tf2dkAlYMMw9kV+6wptDS M5WZQXUeoYdWyjl1HF+VY2uQZw3CQfE1DgT+l5OSNK0YoV9WcPsEtikz+T3U/p8Px90m15 DEv4cUS3wmphTfpNm78PzmKYvCyAecg= Subject: [PATCH v3 04/22] x86/xstate: re-use valid_xcr0() for boot-time checks From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <77b149c5-e7b8-6335-dd86-745c6cc69a06@suse.com> Date: Thu, 22 Apr 2021 16:45:27 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" Instead of (just partially) open-coding it, re-use the function after suitably moving it up. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -609,6 +609,34 @@ unsigned int xstate_ctxt_size(u64 xcr0) return _xstate_ctxt_size(xcr0); } =20 +static bool valid_xcr0(uint64_t xcr0) +{ + /* FP must be unconditionally set. */ + if ( !(xcr0 & X86_XCR0_FP) ) + return false; + + /* YMM depends on SSE. */ + if ( (xcr0 & X86_XCR0_YMM) && !(xcr0 & X86_XCR0_SSE) ) + return false; + + if ( xcr0 & (X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM) ) + { + /* OPMASK, ZMM, and HI_ZMM require YMM. */ + if ( !(xcr0 & X86_XCR0_YMM) ) + return false; + + /* OPMASK, ZMM, and HI_ZMM must be the same. */ + if ( ~xcr0 & (X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM) ) + return false; + } + + /* BNDREGS and BNDCSR must be the same. */ + if ( !(xcr0 & X86_XCR0_BNDREGS) !=3D !(xcr0 & X86_XCR0_BNDCSR) ) + return false; + + return true; +} + /* Collect the information of processor's extended state */ void xstate_init(struct cpuinfo_x86 *c) { @@ -644,10 +672,9 @@ void xstate_init(struct cpuinfo_x86 *c) } =20 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); - - BUG_ON((eax & XSTATE_FP_SSE) !=3D XSTATE_FP_SSE); - BUG_ON((eax & X86_XCR0_YMM) && !(eax & X86_XCR0_SSE)); feature_mask =3D (((u64)edx << 32) | eax) & XCNTXT_MASK; + BUG_ON(!valid_xcr0(feature_mask)); + BUG_ON(!(feature_mask & X86_XCR0_SSE)); =20 /* * Set CR4_OSXSAVE and run "cpuid" to get xsave_cntxt_size. @@ -677,31 +704,6 @@ void xstate_init(struct cpuinfo_x86 *c) BUG(); } =20 -static bool valid_xcr0(u64 xcr0) -{ - /* FP must be unconditionally set. */ - if ( !(xcr0 & X86_XCR0_FP) ) - return false; - - /* YMM depends on SSE. */ - if ( (xcr0 & X86_XCR0_YMM) && !(xcr0 & X86_XCR0_SSE) ) - return false; - - if ( xcr0 & (X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM) ) - { - /* OPMASK, ZMM, and HI_ZMM require YMM. */ - if ( !(xcr0 & X86_XCR0_YMM) ) - return false; - - /* OPMASK, ZMM, and HI_ZMM must be the same. */ - if ( ~xcr0 & (X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM) ) - return false; - } - - /* BNDREGS and BNDCSR must be the same. */ - return !(xcr0 & X86_XCR0_BNDREGS) =3D=3D !(xcr0 & X86_XCR0_BNDCSR); -} - int validate_xstate(const struct domain *d, uint64_t xcr0, uint64_t xcr0_a= ccum, const struct xsave_hdr *hdr) { From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619102789; cv=none; d=zohomail.com; s=zohoarc; b=dACp24+og7UW48BSyfuRIe5NhRnUg6jrKtJzJ29WfwKoIBaDaEuNSFYXLtwNe4Ln794siUZaT5yO0aATsVOP3cifVE7pjpStujHpazGi09LBwB2Tlp7cjL+9fQo7X1PhIlmtm47gBrEi0l8g4yBaWHFs+Al/mutt0Yjc+FGnVZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102765; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=An8uS4tiRtP4/sbgEQt0pyfRbcGoO31aNLmWWP5xbQA=; b=RHpqN6AfeNvotXMtggLmtrwRJFzTm9kPYOHay69KJMOu7snitOqnhn3sDLMno1eEAcV2q2 /3d4bT4qMFzioUQyGUN1CqMPEPgYf4jhHymhMeqlQxwNj6TXfQf51I+ZPCTxg8oodVJNOP /AavWkJfhkERLV2Laihp0RZq0UV/4rQ= Subject: [PATCH v3 05/22] x86/xstate: drop xstate_offsets[] and xstate_sizes[] From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <434705ef-1c34-581d-b956-2322b4413232@suse.com> Date: Thu, 22 Apr 2021 16:45:58 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" They're redundant with respective fields from the raw CPUID policy; no need to keep two copies of the same data. This also breaks recalculate_xstate()'s dependency on xstate_init(), allowing host CPUID policy calculation to be moved together with that of the raw one (which a subsequent change will require anyway). Signed-off-by: Jan Beulich --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -498,6 +498,8 @@ void identify_cpu(struct cpuinfo_x86 *c) } =20 /* Now the feature flags better reflect actual CPU features! */ + if (c =3D=3D &boot_cpu_data) + init_host_cpuid(); =20 xstate_init(c); =20 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -170,32 +170,32 @@ static void recalculate_xstate(struct cp { xstates |=3D X86_XCR0_YMM; xstate_size =3D max(xstate_size, - xstate_offsets[X86_XCR0_YMM_POS] + - xstate_sizes[X86_XCR0_YMM_POS]); + xstate_offset(X86_XCR0_YMM_POS) + + xstate_size(X86_XCR0_YMM_POS)); } =20 if ( p->feat.mpx ) { xstates |=3D X86_XCR0_BNDREGS | X86_XCR0_BNDCSR; xstate_size =3D max(xstate_size, - xstate_offsets[X86_XCR0_BNDCSR_POS] + - xstate_sizes[X86_XCR0_BNDCSR_POS]); + xstate_offset(X86_XCR0_BNDCSR_POS) + + xstate_size(X86_XCR0_BNDCSR_POS)); } =20 if ( p->feat.avx512f ) { xstates |=3D X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM; xstate_size =3D max(xstate_size, - xstate_offsets[X86_XCR0_HI_ZMM_POS] + - xstate_sizes[X86_XCR0_HI_ZMM_POS]); + xstate_offset(X86_XCR0_HI_ZMM_POS) + + xstate_size(X86_XCR0_HI_ZMM_POS)); } =20 if ( p->feat.pku ) { xstates |=3D X86_XCR0_PKRU; xstate_size =3D max(xstate_size, - xstate_offsets[X86_XCR0_PKRU_POS] + - xstate_sizes[X86_XCR0_PKRU_POS]); + xstate_offset(X86_XCR0_PKRU_POS) + + xstate_size(X86_XCR0_PKRU_POS)); } =20 p->xstate.max_size =3D xstate_size; @@ -218,8 +218,8 @@ static void recalculate_xstate(struct cp if ( !(xstates & curr_xstate) ) continue; =20 - p->xstate.comp[i].size =3D xstate_sizes[i]; - p->xstate.comp[i].offset =3D xstate_offsets[i]; + p->xstate.comp[i].size =3D xstate_size(i); + p->xstate.comp[i].offset =3D xstate_offset(i); p->xstate.comp[i].xss =3D curr_xstate & XSTATE_XSAVES_ONLY; p->xstate.comp[i].align =3D curr_xstate & xstate_align; } @@ -531,10 +531,16 @@ static void __init calculate_hvm_def_pol x86_cpuid_policy_shrink_max_leaves(p); } =20 -void __init init_guest_cpuid(void) +void __init init_host_cpuid(void) { calculate_raw_policy(); calculate_host_policy(); +} + +void __init init_guest_cpuid(void) +{ + /* Do this a 2nd time to account for setup_{clear,force}_cpu_cap() use= s. */ + calculate_host_policy(); =20 if ( IS_ENABLED(CONFIG_PV) ) { --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -26,8 +27,6 @@ static u32 __read_mostly xsave_cntxt_siz /* A 64-bit bitmask of the XSAVE/XRSTOR features supported by processor. */ u64 __read_mostly xfeature_mask; =20 -unsigned int *__read_mostly xstate_offsets; -unsigned int *__read_mostly xstate_sizes; u64 __read_mostly xstate_align; static unsigned int __read_mostly xstate_features; =20 @@ -93,34 +92,19 @@ static int setup_xstate_features(bool bs unsigned int leaf, eax, ebx, ecx, edx; =20 if ( bsp ) - { xstate_features =3D flsl(xfeature_mask); - xstate_offsets =3D xzalloc_array(unsigned int, xstate_features); - if ( !xstate_offsets ) - return -ENOMEM; - - xstate_sizes =3D xzalloc_array(unsigned int, xstate_features); - if ( !xstate_sizes ) - return -ENOMEM; - } =20 for ( leaf =3D 2; leaf < xstate_features; leaf++ ) { - if ( bsp ) - { - cpuid_count(XSTATE_CPUID, leaf, &xstate_sizes[leaf], - &xstate_offsets[leaf], &ecx, &edx); - if ( ecx & XSTATE_ALIGN64 ) - __set_bit(leaf, &xstate_align); - } + cpuid_count(XSTATE_CPUID, leaf, &eax, + &ebx, &ecx, &edx); + BUG_ON(eax !=3D xstate_size(leaf)); + BUG_ON(ebx !=3D xstate_offset(leaf)); + + if ( bsp && (ecx & XSTATE_ALIGN64) ) + __set_bit(leaf, &xstate_align); else - { - cpuid_count(XSTATE_CPUID, leaf, &eax, - &ebx, &ecx, &edx); - BUG_ON(eax !=3D xstate_sizes[leaf]); - BUG_ON(ebx !=3D xstate_offsets[leaf]); BUG_ON(!(ecx & XSTATE_ALIGN64) !=3D !test_bit(leaf, &xstate_al= ign)); - } } =20 return 0; @@ -150,7 +134,7 @@ static void setup_xstate_comp(uint16_t * if ( test_bit(i, &xstate_align) ) offset =3D ROUNDUP(offset, 64); comp_offsets[i] =3D offset; - offset +=3D xstate_sizes[i]; + offset +=3D xstate_size(i); } } ASSERT(offset <=3D xsave_cntxt_size); @@ -213,10 +197,10 @@ void expand_xsave_states(struct vcpu *v, * comp_offsets[] information, something is very broken. */ BUG_ON(!comp_offsets[index]); - BUG_ON((xstate_offsets[index] + xstate_sizes[index]) > size); + BUG_ON((xstate_offset(index) + xstate_size(index)) > size); =20 - memcpy(dest + xstate_offsets[index], src + comp_offsets[index], - xstate_sizes[index]); + memcpy(dest + xstate_offset(index), src + comp_offsets[index], + xstate_size(index)); =20 valid &=3D ~feature; } @@ -279,10 +263,10 @@ void compress_xsave_states(struct vcpu * * comp_offset[] information, something is very broken. */ BUG_ON(!comp_offsets[index]); - BUG_ON((xstate_offsets[index] + xstate_sizes[index]) > size); + BUG_ON((xstate_offset(index) + xstate_size(index)) > size); =20 - memcpy(dest + comp_offsets[index], src + xstate_offsets[index], - xstate_sizes[index]); + memcpy(dest + comp_offsets[index], src + xstate_offset(index), + xstate_size(index)); =20 valid &=3D ~feature; } @@ -516,8 +500,8 @@ int xstate_alloc_save_area(struct vcpu * unsigned int i; =20 for ( size =3D 0, i =3D 2; i < xstate_features; ++i ) - if ( size < xstate_sizes[i] ) - size =3D xstate_sizes[i]; + if ( size < xstate_size(i) ) + size =3D xstate_size(i); size +=3D XSTATE_AREA_MIN_SIZE; } =20 @@ -559,9 +543,9 @@ int xstate_update_save_area(struct vcpu for ( size =3D old =3D XSTATE_AREA_MIN_SIZE, i =3D 2; i < xstate_featu= res; ++i ) { if ( xcr0_max & (1ul << i) ) - size =3D max(size, xstate_offsets[i] + xstate_sizes[i]); + size =3D max(size, xstate_offset(i) + xstate_size(i)); if ( v->arch.xcr0_accum & (1ul << i) ) - old =3D max(old, xstate_offsets[i] + xstate_sizes[i]); + old =3D max(old, xstate_offset(i) + xstate_size(i)); } =20 save_area =3D _xvrealloc(v->arch.xsave_area, size, __alignof(*save_are= a)); @@ -819,7 +803,7 @@ uint64_t read_bndcfgu(void) : "=3Dm" (*xstate) : "a" (X86_XCR0_BNDCSR), "d" (0), "D" (xstate) ); =20 - bndcsr =3D (void *)xstate + xstate_offsets[X86_XCR0_BNDCSR_POS]; + bndcsr =3D (void *)xstate + xstate_offset(X86_XCR0_BNDCSR_POS); } =20 if ( cr0 & X86_CR0_TS ) --- a/xen/include/asm-x86/cpuid.h +++ b/xen/include/asm-x86/cpuid.h @@ -16,6 +16,7 @@ extern const uint32_t known_features[FSCAPINTS]; extern const uint32_t special_features[FSCAPINTS]; =20 +void init_host_cpuid(void); void init_guest_cpuid(void); =20 /* --- a/xen/include/asm-x86/xstate.h +++ b/xen/include/asm-x86/xstate.h @@ -44,8 +44,9 @@ extern uint32_t mxcsr_mask; =20 extern u64 xfeature_mask; extern u64 xstate_align; -extern unsigned int *xstate_offsets; -extern unsigned int *xstate_sizes; + +#define xstate_offset(n) (raw_cpuid_policy.xstate.comp[n].offset) +#define xstate_size(n) (raw_cpuid_policy.xstate.comp[n].size) =20 /* extended state save area */ struct __attribute__((aligned (64))) xsave_struct From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619102835; cv=none; d=zohomail.com; s=zohoarc; b=af9R0cWetwh5FcR69LQ5yZbiFfP98HA8U6Kgmy31PTboYvSrN9B6Veg4IM/s76hoaCoFvlJTWL78K58+W4sGjB5EJEswJmbxQijZjniMGp+xvOahi6jwXzf9K9A9pVl7DPQhLXWCNlujQ0LLlXklBe4aXY20BYvJipHvhoOBmyc= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102812; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=So2JgmrzhvB3sGCo9ejN1SRRrQtA5dudILEINyAz1T8=; b=YwDOqv4vy7B5IwVbyljw7TzZZEkZx+1jgHX8IhteJF5muTMLF8x3iSCFydCNY3pDzr991i BnnIGkf0TMMC/EIJukqT6PJLbWIskJWp/oCxMYmwTcF9IOQFO5KELXbpHvP2JdyC2cEevy Ku7iVdtwRwrtNm0Q0lIOTGJFP5Rkn7U= Subject: [PATCH v3 06/22] x86/xstate: replace xsave_cntxt_size and drop XCNTXT_MASK From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: Date: Thu, 22 Apr 2021 16:46:47 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" XCNTXT_MASK is effectively embedded in recalculate_xstate(), and xsave_cntxt_size was redundant with the host CPUID policy's xstate.max_size field. Use the host CPUID policy as input (requiring it to be calculated earlier), thus allowing e.g. "cpuid=3Dno-avx512f" to also result in avoiding allocation of space for ZMM and mask register state. Also drop a stale part of an adjacent comment. Signed-off-by: Jan Beulich --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -20,9 +20,10 @@ /* * Maximum size (in byte) of the XSAVE/XRSTOR save area required by all * the supported and enabled features on the processor, including the - * XSAVE.HEADER. We only enable XCNTXT_MASK that we have known. + * XSAVE.HEADER. We only enable cpuid_policy_xcr0_max(&host_cpuid_policy). + * Note that this identifier should not be usable as an lvalue. */ -static u32 __read_mostly xsave_cntxt_size; +#define xsave_cntxt_size (host_cpuid_policy.xstate.max_size | 0) =20 /* A 64-bit bitmask of the XSAVE/XRSTOR features supported by processor. */ u64 __read_mostly xfeature_mask; @@ -575,8 +576,23 @@ static unsigned int _xstate_ctxt_size(u6 ASSERT(ok); cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); ASSERT(ebx <=3D ecx); - ok =3D set_xcr0(act_xcr0); - ASSERT(ok); + + /* + * When called the very first time from xstate_init(), act_xcr0 (as re= ad + * from per-CPU data) is still zero. xstate_init() wants this function= to + * leave xfeature_mask in place, so avoid restoration in this case (wh= ich + * would fail anyway). + */ + if ( act_xcr0 ) + { + ok =3D set_xcr0(act_xcr0); + ASSERT(ok); + } + else + { + BUG_ON(!ok); + ASSERT(xcr0 =3D=3D xfeature_mask); + } =20 return ebx; } @@ -648,42 +664,35 @@ void xstate_init(struct cpuinfo_x86 *c) return; =20 if ( (bsp && !use_xsave) || - boot_cpu_data.cpuid_level < XSTATE_CPUID ) + c->cpuid_level < XSTATE_CPUID ) { BUG_ON(!bsp); setup_clear_cpu_cap(X86_FEATURE_XSAVE); return; } =20 - cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); - feature_mask =3D (((u64)edx << 32) | eax) & XCNTXT_MASK; - BUG_ON(!valid_xcr0(feature_mask)); - BUG_ON(!(feature_mask & X86_XCR0_SSE)); - - /* - * Set CR4_OSXSAVE and run "cpuid" to get xsave_cntxt_size. - */ - set_in_cr4(X86_CR4_OSXSAVE); - if ( !set_xcr0(feature_mask) ) - BUG(); - if ( bsp ) { + feature_mask =3D cpuid_policy_xcr0_max(&host_cpuid_policy); + BUG_ON(!valid_xcr0(feature_mask)); + BUG_ON(!(feature_mask & X86_XCR0_SSE)); + xfeature_mask =3D feature_mask; - /* - * xsave_cntxt_size is the max size required by enabled features. - * We know FP/SSE and YMM about eax, and nothing about edx at pres= ent. - */ - xsave_cntxt_size =3D _xstate_ctxt_size(feature_mask); + /* xsave_cntxt_size is the max size required by enabled features. = */ printk("xstate: size: %#x and states: %#"PRIx64"\n", - xsave_cntxt_size, xfeature_mask); - } - else - { - BUG_ON(xfeature_mask !=3D feature_mask); - BUG_ON(xsave_cntxt_size !=3D _xstate_ctxt_size(feature_mask)); + xsave_cntxt_size, feature_mask); + + set_in_cr4(X86_CR4_OSXSAVE); } =20 + cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); + feature_mask =3D (((uint64_t)edx << 32) | eax) & xfeature_mask; + BUG_ON(xfeature_mask !=3D feature_mask); + + /* This has the side effect of set_xcr0(feature_mask). */ + if ( xsave_cntxt_size !=3D _xstate_ctxt_size(feature_mask) ) + BUG(); + if ( setup_xstate_features(bsp) && bsp ) BUG(); } --- a/xen/include/asm-x86/xstate.h +++ b/xen/include/asm-x86/xstate.h @@ -30,9 +30,6 @@ extern uint32_t mxcsr_mask; #define XSTATE_AREA_MIN_SIZE (FXSAVE_SIZE + XSAVE_HDR_SIZE) =20 #define XSTATE_FP_SSE (X86_XCR0_FP | X86_XCR0_SSE) -#define XCNTXT_MASK (X86_XCR0_FP | X86_XCR0_SSE | X86_XCR0_YMM | \ - X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM |= \ - XSTATE_NONLAZY) =20 #define XSTATE_ALL (~(1ULL << 63)) #define XSTATE_NONLAZY (X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | X86_XCR0_PKRU) From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 22 Apr 2021 14:47:24 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 659f57e8-ec80-4d3c-9fdf-8d577b13b234; Thu, 22 Apr 2021 14:47:23 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 2C276ABB1; Thu, 22 Apr 2021 14:47:23 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 659f57e8-ec80-4d3c-9fdf-8d577b13b234 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102843; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2vhMDJVGPLut9dUUvDo0ADaCfxiPqS6gGUbBUs/N0kg=; b=Lmgbr5OOk6rjy1YhZnMk1M8RsWc6m6E30tvi1IoNRWef79uUGW2MN3udMUMN1AB/ZjPEf9 p1pMSw9hguRx5vH7rV1qYSKLC6xxFjz5Z5xtVdW4IbXJkwLpgLh1PJTQ8N4Ev6VXpKuLsW x+fuYOTJsLuRm3zRXxvrzfvey3lbITo= Subject: [PATCH v3 07/22] x86/xstate: avoid accounting for unsupported components From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: Date: Thu, 22 Apr 2021 16:47:23 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" There's no point in including unsupported components in the size calculations of xstate_{alloc,update}_save_area(). Signed-off-by: Jan Beulich --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -501,8 +501,12 @@ int xstate_alloc_save_area(struct vcpu * unsigned int i; =20 for ( size =3D 0, i =3D 2; i < xstate_features; ++i ) + { + if ( !(xfeature_mask & (1ul << i)) ) + continue; if ( size < xstate_size(i) ) size =3D xstate_size(i); + } size +=3D XSTATE_AREA_MIN_SIZE; } =20 @@ -543,6 +547,8 @@ int xstate_update_save_area(struct vcpu =20 for ( size =3D old =3D XSTATE_AREA_MIN_SIZE, i =3D 2; i < xstate_featu= res; ++i ) { + if ( !(xfeature_mask & (1ul << i)) ) + continue; if ( xcr0_max & (1ul << i) ) size =3D max(size, xstate_offset(i) + xstate_size(i)); if ( v->arch.xcr0_accum & (1ul << i) ) From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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Thu, 22 Apr 2021 14:47:57 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 2cdad257-e8fd-48ac-ba7e-1fd13a13e949; Thu, 22 Apr 2021 14:47:57 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 5AF7EABB1; Thu, 22 Apr 2021 14:47:56 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 2cdad257-e8fd-48ac-ba7e-1fd13a13e949 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102876; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nApfhe7Gh5uQXawoQVwfWvBSVmPP6Sx/Cf+XRmmjUl4=; b=W9ESb8eYYHSfy/yk1kr3FdK4zhsiAhvXNdt8NdmouJ61k5NRpjUDcsbFMe+fG1s3XXWzO/ W9srfNoKpat258g/Vveia7Uh9Nm0Ymr6HSv00+dmKwAoKJ3dOw2AwQKOaL/7Wg5aCB/38s Ou8XnXbWBzDL9LD1swsAZUn5g9xDlgs= Subject: [PATCH v3 08/22] x86: use xvmalloc() for extended context buffer allocations From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <5a860979-e95f-4c29-18c0-4543d8df6547@suse.com> Date: Thu, 22 Apr 2021 16:47:56 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" This is in preparation for the buffer sizes exceeding a page's worth of space, as will happen with AMX as well as Architectural LBR. Signed-off-by: Jan Beulich --- v2: New. --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -380,7 +381,7 @@ long arch_do_domctl( goto sethvmcontext_out; =20 ret =3D -ENOMEM; - if ( (c.data =3D xmalloc_bytes(c.size)) =3D=3D NULL ) + if ( (c.data =3D xvmalloc_bytes(c.size)) =3D=3D NULL ) goto sethvmcontext_out; =20 ret =3D -EFAULT; @@ -392,7 +393,7 @@ long arch_do_domctl( domain_unpause(d); =20 sethvmcontext_out: - xfree(c.data); + xvfree(c.data); break; } =20 @@ -422,7 +423,7 @@ long arch_do_domctl( =20 /* Allocate our own marshalling buffer */ ret =3D -ENOMEM; - if ( (c.data =3D xmalloc_bytes(c.size)) =3D=3D NULL ) + if ( (c.data =3D xvmalloc_bytes(c.size)) =3D=3D NULL ) goto gethvmcontext_out; =20 domain_pause(d); @@ -435,7 +436,7 @@ long arch_do_domctl( =20 gethvmcontext_out: copyback =3D true; - xfree(c.data); + xvfree(c.data); break; } =20 @@ -953,7 +954,7 @@ long arch_do_domctl( if ( !ret && size > PV_XSAVE_HDR_SIZE ) { unsigned int xsave_size =3D size - PV_XSAVE_HDR_SIZE; - void *xsave_area =3D xmalloc_bytes(xsave_size); + void *xsave_area =3D xvmalloc_bytes(xsave_size); =20 if ( !xsave_area ) { @@ -967,7 +968,7 @@ long arch_do_domctl( if ( copy_to_guest_offset(evc->buffer, offset, xsave_area, xsave_size) ) ret =3D -EFAULT; - xfree(xsave_area); + xvfree(xsave_area); } =20 vcpu_unpause(v); @@ -987,7 +988,7 @@ long arch_do_domctl( evc->size > PV_XSAVE_SIZE(xfeature_mask) ) goto vcpuextstate_out; =20 - receive_buf =3D xmalloc_bytes(evc->size); + receive_buf =3D xvmalloc_bytes(evc->size); if ( !receive_buf ) { ret =3D -ENOMEM; @@ -997,7 +998,7 @@ long arch_do_domctl( offset, evc->size) ) { ret =3D -EFAULT; - xfree(receive_buf); + xvfree(receive_buf); goto vcpuextstate_out; } =20 @@ -1015,7 +1016,7 @@ long arch_do_domctl( ret =3D 0; if ( ret ) { - xfree(receive_buf); + xvfree(receive_buf); goto vcpuextstate_out; } =20 @@ -1043,7 +1044,7 @@ long arch_do_domctl( vcpu_unpause(v); } =20 - xfree(receive_buf); + xvfree(receive_buf); } =20 #undef PV_XSAVE_HDR_SIZE --- a/xen/arch/x86/hvm/save.c +++ b/xen/arch/x86/hvm/save.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 #include =20 @@ -154,7 +155,7 @@ int hvm_save_one(struct domain *d, unsig else v =3D d->vcpu[instance]; ctxt.size =3D hvm_sr_handlers[typecode].size; - ctxt.data =3D xmalloc_bytes(ctxt.size); + ctxt.data =3D xvmalloc_bytes(ctxt.size); if ( !ctxt.data ) return -ENOMEM; =20 @@ -200,7 +201,7 @@ int hvm_save_one(struct domain *d, unsig else domain_unpause(d); =20 - xfree(ctxt.data); + xvfree(ctxt.data); return rv; } =20 From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619102968; cv=none; d=zohomail.com; s=zohoarc; b=OeaNURUYewbV1o3W1Us5OSDgr+l8ozOyUMS/9efAa7x8gxvRE9268xVLOGY92oCGaTOyRyYNcg7iIJlVyRUjQB83AYIPpLamIMcxjx+rHv2ey11gwrUqpEQIXOPtR0t9c+UMo5aLOQjnUzjKoKc3uj7jXfZt9/8FCRwigmVSnas= ARC-Message-Signature: i=1; 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Thu, 22 Apr 2021 14:49:01 +0000 Received: by outflank-mailman (output) from mailman id 115499.220380; Thu, 22 Apr 2021 14:49:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZadZ-00047c-8F; Thu, 22 Apr 2021 14:49:01 +0000 Received: by outflank-mailman (input) for mailman id 115499; Thu, 22 Apr 2021 14:48:59 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZadX-00047W-C6 for xen-devel@lists.xenproject.org; Thu, 22 Apr 2021 14:48:59 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id bfa7b65c-c3e7-45be-9a66-a31a63cbdbdf; Thu, 22 Apr 2021 14:48:58 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 76379B16E; Thu, 22 Apr 2021 14:48:57 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: bfa7b65c-c3e7-45be-9a66-a31a63cbdbdf X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619102937; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=whV4digUq1DW2nHxtRw8sF8wf/NZv487D6zdQFusjPM=; b=X3NfmOp8L/htldif072mA7Zp7Wbak0BirqDpv3UbwamSUvZZgtip5n9ZlgHQ2+d3wk7Z3l 7gZSTZjr/rseWEB0XbxmiVq5CzORG3pgw3wHoLK3EYj7Obt+K+arkMbD1ZFWkIPEyRvPcC d88IsqLLC3Cbe4ptTbwFm5ihPmVxFYA= Subject: [PATCH v3 09/22] x86/xstate: enable AMX components From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Ian Jackson , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= , Anthony Perard References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <0dbeab9e-087d-c7f5-3d79-f507e8ddeb0d@suse.com> Date: Thu, 22 Apr 2021 16:48:57 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" These being controlled by XCR0, enabling support is relatively straightforward. Note however that there won't be any use of them until their dependent ISA extension CPUID flags get exposed, not the least due to recalculate_xstate() handling the dependencies in kind of a reverse manner. Signed-off-by: Jan Beulich --- v3: Add new states to XSTATE_NONLAZY. v2: New. --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -221,6 +221,9 @@ int libxl_cpuid_parse_config(libxl_cpuid {"md-clear", 0x00000007, 0, CPUID_REG_EDX, 10, 1}, {"serialize", 0x00000007, 0, CPUID_REG_EDX, 14, 1}, {"cet-ibt", 0x00000007, 0, CPUID_REG_EDX, 20, 1}, + {"amx-bf16", 0x00000007, 0, CPUID_REG_EDX, 22, 1}, + {"amx-tile", 0x00000007, 0, CPUID_REG_EDX, 24, 1}, + {"amx-int8", 0x00000007, 0, CPUID_REG_EDX, 25, 1}, {"ibrsb", 0x00000007, 0, CPUID_REG_EDX, 26, 1}, {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1}, {"l1d-flush", 0x00000007, 0, CPUID_REG_EDX, 28, 1}, --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -168,7 +168,8 @@ static const char *const str_7d0[32] =3D =20 [18] =3D "pconfig", [20] =3D "cet-ibt", - + [22] =3D "amx-bf16", + [24] =3D "amx-tile", [25] =3D "amx-int8", [26] =3D "ibrsb", [27] =3D "stibp", [28] =3D "l1d-flush", [29] =3D "arch-caps", [30] =3D "core-caps", [31] =3D "ssbd", --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -198,6 +198,14 @@ static void recalculate_xstate(struct cp xstate_size(X86_XCR0_PKRU_POS)); } =20 + if ( p->feat.amx_tile ) + { + xstates |=3D X86_XCR0_TILECFG | X86_XCR0_TILEDATA; + xstate_size =3D max(xstate_size, + xstate_offset(X86_XCR0_TILEDATA_POS) + + xstate_size(X86_XCR0_TILEDATA_POS)); + } + p->xstate.max_size =3D xstate_size; p->xstate.xcr0_low =3D xstates & ~XSTATE_XSAVES_ONLY; p->xstate.xcr0_high =3D (xstates & ~XSTATE_XSAVES_ONLY) >> 32; --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -640,6 +640,10 @@ static bool valid_xcr0(uint64_t xcr0) if ( !(xcr0 & X86_XCR0_BNDREGS) !=3D !(xcr0 & X86_XCR0_BNDCSR) ) return false; =20 + /* TILECFG and TILEDATA must be the same. */ + if ( !(xcr0 & X86_XCR0_TILECFG) !=3D !(xcr0 & X86_XCR0_TILEDATA) ) + return false; + return true; } =20 --- a/xen/include/asm-x86/x86-defns.h +++ b/xen/include/asm-x86/x86-defns.h @@ -96,6 +96,10 @@ #define X86_XCR0_HI_ZMM (1ULL << X86_XCR0_HI_ZMM_POS) #define X86_XCR0_PKRU_POS 9 #define X86_XCR0_PKRU (1ULL << X86_XCR0_PKRU_POS) +#define X86_XCR0_TILECFG_POS 17 +#define X86_XCR0_TILECFG (1ULL << X86_XCR0_TILECFG_POS) +#define X86_XCR0_TILEDATA_POS 18 +#define X86_XCR0_TILEDATA (1ULL << X86_XCR0_TILEDATA_POS) #define X86_XCR0_LWP_POS 62 #define X86_XCR0_LWP (1ULL << X86_XCR0_LWP_POS) =20 --- a/xen/include/asm-x86/xstate.h +++ b/xen/include/asm-x86/xstate.h @@ -32,7 +32,8 @@ extern uint32_t mxcsr_mask; #define XSTATE_FP_SSE (X86_XCR0_FP | X86_XCR0_SSE) =20 #define XSTATE_ALL (~(1ULL << 63)) -#define XSTATE_NONLAZY (X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | X86_XCR0_PKRU) +#define XSTATE_NONLAZY (X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | X86_XCR0_PKRU= | \ + X86_XCR0_TILECFG | X86_XCR0_TILEDATA) #define XSTATE_LAZY (XSTATE_ALL & ~XSTATE_NONLAZY) #define XSTATE_XSAVES_ONLY 0 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -268,6 +268,9 @@ XEN_CPUFEATURE(MD_CLEAR, 9*32+10) / XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT = */ XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */ XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking= */ +XEN_CPUFEATURE(AMX_BF16, 9*32+22) /* AMX BFloat16 instructions */ +XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX tile architecture */ +XEN_CPUFEATURE(AMX_INT8, 9*32+25) /* AMX 8-bit integer instructions= */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by= Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -222,7 +222,7 @@ def crunch_numbers(state): # instruction groups which are specified to require XSAVE for state # management. XSAVE: [XSAVEOPT, XSAVEC, XGETBV1, XSAVES, - AVX, MPX, PKU, LWP], + AVX, MPX, PKU, AMX_TILE, LWP], =20 # AVX is taken to mean hardware support for 256bit registers (whic= h in # practice depends on the VEX prefix to encode), and the instructi= ons @@ -290,6 +290,11 @@ def crunch_numbers(state): =20 # In principle the TSXLDTRK insns could also be considered indepen= dent. RTM: [TSXLDTRK], + + # AMX-TILE means hardware support for tile registers and general n= on- + # computational instructions. All further AMX features are built = on top + # of AMX-TILE. + AMX_TILE: [AMX_BF16, AMX_INT8], } =20 deep_features =3D tuple(sorted(deps.keys())) From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619103042; cv=none; d=zohomail.com; s=zohoarc; b=ByEjVjd4LwIDcsj+wGmV2tVzdSz/jsz8HoscwrtIulAIC4qXiyYjBZdeduvKvvtrCcpiBGfl6nbph6o4eVFXxr8KiLzK7rNHtzDwNPla1+wk5Xb9VxWPR/88g+8KBSUQawjGsbcO15M0JdsMFWGyiX+yb8nmgoQ/9weNzyd6nSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619103042; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+QdQWxNcKE7APKYxJnP/WcIc9s52TlEnJpEVbzCgqbg=; b=jCKJ/ond0dFp6CRI5zHorLuOwJeYXVpHOF7CqXwskGu+WDw1ZIr33L+hsDRKrYnJTpcdC0IkotlXpT7Si3prNERO3YGhHm3CwoVhyfBLw+HdZdC89SnlDpOHvr4i5jOwS+oDZvvD+mqU07qLPXaPF4NRbTVIxSQWD3Fvy7oZg00= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=quarantine dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619103042356636.5303890838265; Thu, 22 Apr 2021 07:50:42 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.115504.220392 (Exim 4.92) (envelope-from ) id 1lZaek-0004xw-OR; Thu, 22 Apr 2021 14:50:14 +0000 Received: by outflank-mailman (output) from mailman id 115504.220392; Thu, 22 Apr 2021 14:50:14 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZaek-0004xp-KF; Thu, 22 Apr 2021 14:50:14 +0000 Received: by outflank-mailman (input) for mailman id 115504; Thu, 22 Apr 2021 14:50:13 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZaej-0004xj-E9 for xen-devel@lists.xenproject.org; Thu, 22 Apr 2021 14:50:13 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id c9b0d180-a439-4877-9c45-42c6449251d1; Thu, 22 Apr 2021 14:50:12 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id DBFB9B177; Thu, 22 Apr 2021 14:50:11 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c9b0d180-a439-4877-9c45-42c6449251d1 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103012; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+QdQWxNcKE7APKYxJnP/WcIc9s52TlEnJpEVbzCgqbg=; b=e3PtmwVNBCYQunHtm0GS0/Knk0Q82wV/Vg2een4wPBNxR2Xuc8jPezfKm2//rVxqgIm88k EEVMG6y5gJKG6tkSNyGQjb6/b6KqFe3XdYwtL0U0S6Z9j+QflvW/uBqSpxE+fwWfXC1mjE JPCbTjuL8H4Z1M5Mb+slvDTIQZP+7l4= Subject: [PATCH v3 10/22] x86/CPUID: adjust extended leaves out of range clearing From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: Date: Thu, 22 Apr 2021 16:50:12 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) A maximum extended leaf input value with the high half different from 0x8000 should not be considered valid - all leaves should be cleared in this case. Signed-off-by: Jan Beulich Reviewed-by: Roger Pau Monn=C3=A9 --- TBD: Andrew suggested to drop this patch, but that sub-thread still has a loose end. Hence, until I'm convinced otherwise, I've retained this patch here. I don't think it conflicts with any of the subsequent ones. --- v2: Integrate into series. --- a/tools/tests/cpu-policy/test-cpu-policy.c +++ b/tools/tests/cpu-policy/test-cpu-policy.c @@ -519,11 +519,22 @@ static void test_cpuid_out_of_range_clea }, }, { + .name =3D "no extd", + .nr_markers =3D 0, + .p =3D { + /* Clears all markers. */ + .extd.max_leaf =3D 0, + + .extd.vendor_ebx =3D 0xc2, + .extd.raw_fms =3D 0xc2, + }, + }, + { .name =3D "extd", .nr_markers =3D 1, .p =3D { /* Retains marker in leaf 0. Clears others. */ - .extd.max_leaf =3D 0, + .extd.max_leaf =3D 0x80000000, .extd.vendor_ebx =3D 0xc2, =20 .extd.raw_fms =3D 0xc2, --- a/xen/lib/x86/cpuid.c +++ b/xen/lib/x86/cpuid.c @@ -232,7 +232,9 @@ void x86_cpuid_policy_clear_out_of_range ARRAY_SIZE(p->xstate.raw) - 1); } =20 - zero_leaves(p->extd.raw, (p->extd.max_leaf & 0xffff) + 1, + zero_leaves(p->extd.raw, + ((p->extd.max_leaf >> 16) =3D=3D 0x8000 + ? (p->extd.max_leaf & 0xffff) + 1 : 0), ARRAY_SIZE(p->extd.raw) - 1); } =20 From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619103059; cv=none; d=zohomail.com; s=zohoarc; b=flzFYovfqtcNG1YepO2Pmk/ph5p0WFKT/qva060tDx/6WeDTKavICEYbV0oYniPKmrQolDp2YVvyQCkZI8vlfJTNZzKtBwo9obaYeGjZdgUK6UYbJS7EyzFviinSfOpd9nJXKgFRqa3UylYGy53JaSg3H6od630Pa3f/wYRfNwk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619103059; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8opvY7uAAKKl+VTk1uX8v+giIhvZM4yDWQN/O3L3BD0=; b=mj3QJfuzuFlPA6rGe7oJQWGCeWDFe5Zmv55ceWLhQK8Nl+mxEldfnw+7P27F2dtg6pcNzwTLcUcWBGLfhKjo+ucjtLJCx/cUyfY2F80uhNicYJOgXil7ZzbIaEJWm7O0lXV9MCviQE7joTVtS3DqV95CR3VwfHZm/ATl8G/nIY8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=quarantine dis=none) header.from= Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1619103059234882.848458784967; Thu, 22 Apr 2021 07:50:59 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.115508.220403 (Exim 4.92) (envelope-from ) id 1lZafC-00053a-0V; Thu, 22 Apr 2021 14:50:42 +0000 Received: by outflank-mailman (output) from mailman id 115508.220403; Thu, 22 Apr 2021 14:50:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZafB-00053T-Ti; Thu, 22 Apr 2021 14:50:41 +0000 Received: by outflank-mailman (input) for mailman id 115508; Thu, 22 Apr 2021 14:50:41 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZafB-00053M-0t for xen-devel@lists.xenproject.org; Thu, 22 Apr 2021 14:50:41 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id e877c9df-396e-4d3d-babf-7035a0da8ede; Thu, 22 Apr 2021 14:50:40 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 7E701AEC6; Thu, 22 Apr 2021 14:50:39 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e877c9df-396e-4d3d-babf-7035a0da8ede X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103039; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8opvY7uAAKKl+VTk1uX8v+giIhvZM4yDWQN/O3L3BD0=; b=NnH0ao7PeJ7xx6CqWxxfekzBqhEfxincSwKDwUwRX+EzXPGc/ci3yMfQXRf27SrZzLask1 Nx0pBksaUD6dhP4b/MNIVyxFc8FBrjp21p7JjbzXQSsfC/Bw+Zc72pQYvfUbKKzGkYTurk 5jaDGLh9rFgtP9IOq+oqGRx98ECrqq4= Subject: [PATCH v3 11/22] x86/CPUID: move bounding of max_{,sub}leaf fields to library code From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <079ec0a9-fde7-e7a9-40d1-bea50a0c9a0a@suse.com> Date: Thu, 22 Apr 2021 16:50:39 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" Break out this logic from calculate_host_policy() to also use it in the x86 emulator harness, where subsequently we'll want to avoid open-coding AMX maximum palette bounding. Signed-off-by: Jan Beulich --- v2: New. --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -79,6 +79,7 @@ bool emul_test_init(void) unsigned long sp; =20 x86_cpuid_policy_fill_native(&cp); + x86_cpuid_policy_bound_max_leaves(&cp); =20 /* * The emulator doesn't use these instructions, so can always emulate @@ -91,6 +92,8 @@ bool emul_test_init(void) cp.feat.rdpid =3D true; cp.extd.clzero =3D true; =20 + x86_cpuid_policy_shrink_max_leaves(&cp); + if ( cpu_has_xsave ) { unsigned int tmp, ebx; --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -322,12 +322,7 @@ static void __init calculate_host_policy =20 *p =3D raw_cpuid_policy; =20 - p->basic.max_leaf =3D - min_t(uint32_t, p->basic.max_leaf, ARRAY_SIZE(p->basic.raw) - 1); - p->feat.max_subleaf =3D - min_t(uint32_t, p->feat.max_subleaf, ARRAY_SIZE(p->feat.raw) - 1); - p->extd.max_leaf =3D 0x80000000 | min_t(uint32_t, p->extd.max_leaf & 0= xffff, - ARRAY_SIZE(p->extd.raw) - 1); + x86_cpuid_policy_bound_max_leaves(p); =20 cpuid_featureset_to_policy(boot_cpu_data.x86_capability, p); recalculate_xstate(p); --- a/xen/include/xen/lib/x86/cpuid.h +++ b/xen/include/xen/lib/x86/cpuid.h @@ -352,6 +352,12 @@ void x86_cpuid_policy_fill_native(struct void x86_cpuid_policy_clear_out_of_range_leaves(struct cpuid_policy *p); =20 /** + * Bound max leaf/subleaf values according to the capacity of the respecti= ve + * arrays in struct cpuid_policy. + */ +void x86_cpuid_policy_bound_max_leaves(struct cpuid_policy *p); + +/** * Shrink max leaf/subleaf values such that the last respective valid entry * isn't all blank. While permitted by the spec, such extraneous leaves m= ay * provide undue "hints" to guests. --- a/xen/lib/x86/cpuid.c +++ b/xen/lib/x86/cpuid.c @@ -238,6 +238,16 @@ void x86_cpuid_policy_clear_out_of_range ARRAY_SIZE(p->extd.raw) - 1); } =20 +void x86_cpuid_policy_bound_max_leaves(struct cpuid_policy *p) +{ + p->basic.max_leaf =3D + min_t(uint32_t, p->basic.max_leaf, ARRAY_SIZE(p->basic.raw) - 1); + p->feat.max_subleaf =3D + min_t(uint32_t, p->feat.max_subleaf, ARRAY_SIZE(p->feat.raw) - 1); + p->extd.max_leaf =3D 0x80000000 | min_t(uint32_t, p->extd.max_leaf & 0= xffff, + ARRAY_SIZE(p->extd.raw) - 1); +} + void x86_cpuid_policy_shrink_max_leaves(struct cpuid_policy *p) { unsigned int i; From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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Thu, 22 Apr 2021 14:51:21 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id 7ed209c1-2804-4e19-9b3f-e9d820fb28fd; Thu, 22 Apr 2021 14:51:19 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id E59FFABB1; Thu, 22 Apr 2021 14:51:18 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 7ed209c1-2804-4e19-9b3f-e9d820fb28fd X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103079; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t+XcRDhrAUGOG8nc9gmJBAzFifKvbp2kVW+qfBTeKyQ=; b=sMzh/TVrXZEHbTXWsLQa/zcPDFjnUNJJA3n+oQdjCTew3yW/KWDxhXmAvixJ6PVLfsNWSh owkrD2tahxdbLwKBWU6Tp5mYul/SLF+1mhpsbA4MdDC5uAI9GVI2O2VlKzWgJx6E7Kb7LM gBI/hFT250K8OYy+DMa+MS8/3A89xkw= Subject: [PATCH v3 12/22] x86/CPUID: enable AMX leaves From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <45685598-4fa8-7c8e-d1f1-ee550c4c9ab9@suse.com> Date: Thu, 22 Apr 2021 16:51:19 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" This requires bumping the number of basic leaves we support. Apart from this the logic is modeled as closely as possible to that of leaf 7 handling. The checks in x86_cpu_policies_are_compatible() may be more strict than they ultimately need to be, but I'd rather start being on the safe side. Signed-off-by: Jan Beulich --- v2: New. --- It's not clear to me in how far libxl_cpuid.c would want extending: It doesn't look to offer a way to override the maximum subleaf of leaf 7. In fact I can't seem to be able to spot a max extended leaf override mechanism either. --- a/tools/tests/cpu-policy/test-cpu-policy.c +++ b/tools/tests/cpu-policy/test-cpu-policy.c @@ -190,6 +190,40 @@ static void test_cpuid_serialise_success }, .nr_leaves =3D 4 + 0xd + 1 + 1, }, + + /* Leaf 0x1d serialisation stops at max_palette. */ + { + .name =3D "empty leaf 0x1d", + .p =3D { + .basic.max_leaf =3D 0x1d, + }, + .nr_leaves =3D 4 + 0x1d + 1, + }, + { + .name =3D "partial leaf 0x1d", + .p =3D { + .basic.max_leaf =3D 0x1d, + .tile.max_palette =3D 1, + }, + .nr_leaves =3D 4 + 0x1d + 1 + 1, + }, + + /* Leaf 0x1e serialisation stops at 0. */ + { + .name =3D "empty leaf 0x1e", + .p =3D { + .basic.max_leaf =3D 0x1e, + }, + .nr_leaves =3D 4 + 0x1e + 1, + }, + { + .name =3D "partial leaf 0x1e", + .p =3D { + .basic.max_leaf =3D 0x1e, + .tmul.maxk =3D 16, + }, + .nr_leaves =3D 4 + 0x1e + 1, + }, }; =20 printf("Testing CPUID serialise success:\n"); @@ -321,6 +355,14 @@ static void test_cpuid_deserialise_failu .leaf =3D { .leaf =3D 0xd, .subleaf =3D CPUID_GUEST_NR_XSTATE = }, }, { + .name =3D "OoB tile leaf", + .leaf =3D { .leaf =3D 0x1d, .subleaf =3D CPUID_GUEST_NR_PALETT= E }, + }, + { + .name =3D "OoB tmul leaf", + .leaf =3D { .leaf =3D 0x1e, .subleaf =3D CPUID_GUEST_NR_TMUL }, + }, + { .name =3D "OoB extd leaf", .leaf =3D { .leaf =3D 0x80000000 | CPUID_GUEST_NR_EXTD }, }, @@ -432,6 +474,8 @@ static void test_cpuid_out_of_range_clea .topo.raw[0].a =3D 0xc2, .xstate.raw[0].a =3D 0xc2, .xstate.raw[1].a =3D 0xc2, + .tile.raw[0].a =3D 0xc2, + .tmul.raw[0].a =3D 0xc2, }, }, { @@ -447,6 +491,8 @@ static void test_cpuid_out_of_range_clea .topo.raw[0].a =3D 0xc2, .xstate.raw[0].a =3D 0xc2, .xstate.raw[1].a =3D 0xc2, + .tile.raw[0].a =3D 0xc2, + .tmul.raw[0].a =3D 0xc2, }, }, { @@ -461,6 +507,8 @@ static void test_cpuid_out_of_range_clea .topo.raw[0].a =3D 0xc2, .xstate.raw[0].a =3D 0xc2, .xstate.raw[1].a =3D 0xc2, + .tile.raw[0].a =3D 0xc2, + .tmul.raw[0].a =3D 0xc2, }, }, { @@ -474,6 +522,8 @@ static void test_cpuid_out_of_range_clea .topo.raw[1].b =3D 0xc2, .xstate.raw[0].a =3D 0xc2, .xstate.raw[1].a =3D 0xc2, + .tile.raw[0].a =3D 0xc2, + .tmul.raw[0].a =3D 0xc2, }, }, { @@ -488,6 +538,8 @@ static void test_cpuid_out_of_range_clea =20 .xstate.raw[2].b =3D 0xc2, .xstate.raw[3].b =3D 0xc2, + .tile.raw[0].a =3D 0xc2, + .tmul.raw[0].a =3D 0xc2, }, }, { @@ -530,6 +582,34 @@ static void test_cpuid_out_of_range_clea }, }, { + .name =3D "tile no palette", + .nr_markers =3D 0, + .p =3D { + /* First two subleaves invalid as a pair. Others cleared.= */ + .basic.max_leaf =3D 0x1d, + .xstate.xcr0_low =3D XSTATE_FP_SSE, + + .tile.raw[0].a =3D 0xc2, + .tile.raw[1].b =3D 0xc2, + .tmul.raw[0].a =3D 0xc2, + }, + }, + { + .name =3D "tile palette 1", + .nr_markers =3D 1, + .p =3D { + /* First two subleaves valid as a pair. Others cleared. */ + .basic.max_leaf =3D 0x1d, + .feat.amx_tile =3D 1, + .xstate.xcr0_low =3D XSTATE_FP_SSE | X86_XCR0_TILECFG | + X86_XCR0_TILEDATA, + .tile.raw[0].a =3D 1, + .tile.raw[1].b =3D 0xc2, + + .tmul.raw[0].a =3D 0xc2, + }, + }, + { .name =3D "extd", .nr_markers =3D 1, .p =3D { @@ -624,6 +704,24 @@ static void test_cpuid_maximum_leaf_shri }, }, { + .name =3D "tile", + .p =3D { + /* Subleaf 1 only with some valid value. */ + .basic.max_leaf =3D 0x1d, + .tile.raw[0].a =3D 1, + .tile.raw[1].a =3D 1024, + }, + }, + { + .name =3D "tmul", + .p =3D { + /* Subleaf 0 only with some valid values. */ + .basic.max_leaf =3D 0x1e, + .tmul.maxk =3D 16, + .tmul.maxn =3D 16, + }, + }, + { .name =3D "extd", .p =3D { /* Commonly available information only. */ @@ -643,6 +741,7 @@ static void test_cpuid_maximum_leaf_shri =20 p->basic.max_leaf =3D ARRAY_SIZE(p->basic.raw) - 1; p->feat.max_subleaf =3D ARRAY_SIZE(p->feat.raw) - 1; + p->tile.max_palette =3D ARRAY_SIZE(p->tile.raw) - 1; p->extd.max_leaf =3D 0x80000000 | (ARRAY_SIZE(p->extd.raw) - 1); =20 x86_cpuid_policy_shrink_max_leaves(p); @@ -660,6 +759,10 @@ static void test_cpuid_maximum_leaf_shri fail(" Test %s feat fail - expected %#x, got %#x\n", t->name, t->p.feat.max_subleaf, p->feat.max_subleaf); =20 + if ( p->tile.max_palette !=3D t->p.tile.max_palette ) + fail(" Test %s tile fail - expected %#x, got %#x\n", + t->name, t->p.tile.max_palette, p->tile.max_palette); + free(p); } } --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -233,6 +233,29 @@ static void recalculate_xstate(struct cp } } =20 +static void recalculate_tile(struct cpuid_policy *p) +{ + unsigned int i; + + if ( !p->feat.amx_tile ) + { + memset(&p->tile, 0, sizeof(p->tile)); + memset(&p->tmul, 0, sizeof(p->tmul)); + return; + } + + p->tile.raw[0].b =3D p->tile.raw[0].c =3D p->tile.raw[0].d =3D 0; + + for ( i =3D 1; i <=3D p->tile.max_palette; ++i ) + { + p->tile.raw[i].c &=3D 0x0000ffff; + p->tile.raw[i].d =3D 0; + } + + p->tmul.raw[0].a =3D p->tmul.raw[0].c =3D p->tmul.raw[0].d =3D 0; + p->tmul.raw[0].b &=3D 0x00ffffff; +} + /* * Misc adjustments to the policy. Mostly clobbering reserved fields and * duplicating shared fields. Intentionally hidden fields are annotated. @@ -252,6 +275,8 @@ static void recalculate_misc(struct cpui =20 p->basic.raw[0xc] =3D EMPTY_LEAF; =20 + zero_leaves(p->basic.raw, 0xe, 0x1c); + p->extd.e1d &=3D ~CPUID_COMMON_1D_FEATURES; =20 /* Most of Power/RAS hidden from guests. */ @@ -326,6 +351,7 @@ static void __init calculate_host_policy =20 cpuid_featureset_to_policy(boot_cpu_data.x86_capability, p); recalculate_xstate(p); + recalculate_tile(p); recalculate_misc(p); =20 /* When vPMU is disabled, drop it from the host policy. */ @@ -413,6 +439,7 @@ static void __init calculate_pv_max_poli sanitise_featureset(pv_featureset); cpuid_featureset_to_policy(pv_featureset, p); recalculate_xstate(p); + recalculate_tile(p); =20 p->extd.raw[0xa] =3D EMPTY_LEAF; /* No SVM for PV guests. */ =20 @@ -437,6 +464,7 @@ static void __init calculate_pv_def_poli sanitise_featureset(pv_featureset); cpuid_featureset_to_policy(pv_featureset, p); recalculate_xstate(p); + recalculate_tile(p); =20 x86_cpuid_policy_shrink_max_leaves(p); } @@ -504,6 +532,7 @@ static void __init calculate_hvm_max_pol sanitise_featureset(hvm_featureset); cpuid_featureset_to_policy(hvm_featureset, p); recalculate_xstate(p); + recalculate_tile(p); =20 x86_cpuid_policy_shrink_max_leaves(p); } @@ -530,6 +559,7 @@ static void __init calculate_hvm_def_pol sanitise_featureset(hvm_featureset); cpuid_featureset_to_policy(hvm_featureset, p); recalculate_xstate(p); + recalculate_tile(p); =20 x86_cpuid_policy_shrink_max_leaves(p); } @@ -600,6 +630,7 @@ void recalculate_cpuid_policy(struct dom =20 p->basic.max_leaf =3D min(p->basic.max_leaf, max->basic.max_leaf); p->feat.max_subleaf =3D min(p->feat.max_subleaf, max->feat.max_subleaf= ); + p->tile.max_palette =3D min(p->tile.max_palette, max->tile.max_palette= ); p->extd.max_leaf =3D 0x80000000 | min(p->extd.max_leaf & 0xffff, ((p->x86_vendor & (X86_VENDOR_A= MD | X86_VENDOR_H= YGON)) @@ -690,6 +721,7 @@ void recalculate_cpuid_policy(struct dom p->extd.maxlinaddr =3D p->extd.lm ? 48 : 32; =20 recalculate_xstate(p); + recalculate_tile(p); recalculate_misc(p); =20 for ( i =3D 0; i < ARRAY_SIZE(p->cache.raw); ++i ) @@ -812,6 +844,22 @@ void guest_cpuid(const struct vcpu *v, u *res =3D array_access_nospec(p->xstate.raw, subleaf); break; =20 + case 0x1d: + ASSERT(p->tile.max_palette < ARRAY_SIZE(p->tile.raw)); + if ( subleaf > min_t(uint32_t, p->tile.max_palette, + ARRAY_SIZE(p->tile.raw) - 1) ) + return; + + *res =3D array_access_nospec(p->tile.raw, subleaf); + break; + + case 0x1e: + if ( subleaf >=3D ARRAY_SIZE(p->tmul.raw) ) + return; + + *res =3D array_access_nospec(p->tmul.raw, subleaf); + break; + default: *res =3D array_access_nospec(p->basic.raw, leaf); break; @@ -1145,6 +1193,8 @@ static void __init __maybe_unused build_ sizeof(raw_cpuid_policy.feat.raw)); BUILD_BUG_ON(sizeof(raw_cpuid_policy.xstate) !=3D sizeof(raw_cpuid_policy.xstate.raw)); + BUILD_BUG_ON(sizeof(raw_cpuid_policy.tile) !=3D + sizeof(raw_cpuid_policy.tile.raw)); BUILD_BUG_ON(sizeof(raw_cpuid_policy.extd) !=3D sizeof(raw_cpuid_policy.extd.raw)); } --- a/xen/include/xen/lib/x86/cpuid.h +++ b/xen/include/xen/lib/x86/cpuid.h @@ -78,11 +78,13 @@ unsigned int x86_cpuid_lookup_vendor(uin */ const char *x86_cpuid_vendor_to_str(unsigned int vendor); =20 -#define CPUID_GUEST_NR_BASIC (0xdu + 1) +#define CPUID_GUEST_NR_BASIC (0x1eu + 1) #define CPUID_GUEST_NR_CACHE (5u + 1) #define CPUID_GUEST_NR_FEAT (1u + 1) #define CPUID_GUEST_NR_TOPO (1u + 1) #define CPUID_GUEST_NR_XSTATE (62u + 1) +#define CPUID_GUEST_NR_PALETTE (1u + 1) +#define CPUID_GUEST_NR_TMUL (0u + 1) #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1) #define CPUID_GUEST_NR_EXTD_AMD (0x1cu + 1) #define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \ @@ -225,6 +227,35 @@ struct cpuid_policy } comp[CPUID_GUEST_NR_XSTATE]; } xstate; =20 + /* Structured tile information leaf: 0x00000001d[xx] */ + union { + struct cpuid_leaf raw[CPUID_GUEST_NR_PALETTE]; + struct { + /* Subleaf 0. */ + uint32_t max_palette; + uint32_t /* b */:32, /* c */:32, /* d */:32; + }; + + /* Per-palette common state. Valid for i >=3D 1. */ + struct { + uint16_t tot_bytes, bytes_per_tile; + uint16_t bytes_per_row, num_regs; + uint16_t max_rows, :16; + uint32_t /* d */:32; + } palette[CPUID_GUEST_NR_PALETTE]; + } tile; + + /* Structured tmul information leaf: 0x00000001e[xx] */ + union { + struct cpuid_leaf raw[CPUID_GUEST_NR_TMUL]; + struct { + /* Subleaf 0. */ + uint32_t /* a */:32; + uint32_t maxk:8, maxn:16, :8; + uint32_t /* c */:32, /* d */:32; + }; + } tmul; + /* Extended leaves: 0x800000xx */ union { struct cpuid_leaf raw[CPUID_GUEST_NR_EXTD]; --- a/xen/lib/x86/cpuid.c +++ b/xen/lib/x86/cpuid.c @@ -170,6 +170,18 @@ void x86_cpuid_policy_fill_native(struct } } =20 + if ( p->basic.max_leaf >=3D 0x1d ) + { + cpuid_count_leaf(0x1d, 0, &p->tile.raw[0]); + + for ( i =3D 1; i <=3D MIN(p->tile.max_palette, + ARRAY_SIZE(p->tile.raw) - 1); ++i ) + cpuid_count_leaf(0x1d, i, &p->tile.raw[i]); + } + + if ( p->basic.max_leaf >=3D 0x1e ) + cpuid_count_leaf(0x1e, 0, &p->tmul.raw[0]); + /* Extended leaves. */ cpuid_leaf(0x80000000, &p->extd.raw[0]); for ( i =3D 1; i <=3D MIN(p->extd.max_leaf & 0xffffU, @@ -232,6 +244,19 @@ void x86_cpuid_policy_clear_out_of_range ARRAY_SIZE(p->xstate.raw) - 1); } =20 + if ( p->basic.max_leaf < 0x1d || + (cpuid_policy_xstates(p) & + (X86_XCR0_TILECFG | X86_XCR0_TILEDATA)) !=3D + (X86_XCR0_TILECFG | X86_XCR0_TILEDATA) ) + memset(p->tile.raw, 0, sizeof(p->tile.raw)); + else + zero_leaves(p->tile.raw, p->tile.max_palette + 1, + ARRAY_SIZE(p->tile.raw) - 1); + + if ( p->basic.max_leaf < 0x1e || !p->tile.max_palette || + (!p->feat.amx_int8 && !p->feat.amx_bf16) ) + memset(p->tmul.raw, 0, sizeof(p->tmul.raw)); + zero_leaves(p->extd.raw, ((p->extd.max_leaf >> 16) =3D=3D 0x8000 ? (p->extd.max_leaf & 0xffff) + 1 : 0), @@ -244,6 +269,8 @@ void x86_cpuid_policy_bound_max_leaves(s min_t(uint32_t, p->basic.max_leaf, ARRAY_SIZE(p->basic.raw) - 1); p->feat.max_subleaf =3D min_t(uint32_t, p->feat.max_subleaf, ARRAY_SIZE(p->feat.raw) - 1); + p->tile.max_palette =3D + min_t(uint32_t, p->tile.max_palette, ARRAY_SIZE(p->tile.raw) - 1); p->extd.max_leaf =3D 0x80000000 | min_t(uint32_t, p->extd.max_leaf & 0= xffff, ARRAY_SIZE(p->extd.raw) - 1); } @@ -271,6 +298,21 @@ void x86_cpuid_policy_shrink_max_leaves( */ p->basic.raw[0xd] =3D p->xstate.raw[0]; =20 + for ( i =3D p->tile.max_palette; i; --i ) + if ( p->tile.raw[i].a | p->tile.raw[i].b | + p->tile.raw[i].c | p->tile.raw[i].d ) + break; + if ( i ) + p->tile.max_palette =3D i; + else + { + ASSERT(!p->feat.amx_tile); + zero_leaves(p->tile.raw, 0, 0); + } + p->basic.raw[0x1d] =3D p->tile.raw[0]; + + p->basic.raw[0x1e] =3D p->tmul.raw[0]; + for ( i =3D p->basic.max_leaf; i; --i ) if ( p->basic.raw[i].a | p->basic.raw[i].b | p->basic.raw[i].c | p->basic.raw[i].d ) @@ -404,6 +446,19 @@ int x86_cpuid_copy_to_buffer(const struc break; } =20 + case 0x1d: + for ( subleaf =3D 0; + subleaf <=3D MIN(p->tile.max_palette, + ARRAY_SIZE(p->tile.raw) - 1); ++subleaf ) + COPY_LEAF(leaf, subleaf, &p->tile.raw[subleaf]); + break; + + case 0x1e: + for ( subleaf =3D 0; + subleaf <=3D ARRAY_SIZE(p->tmul.raw) - 1; ++subleaf ) + COPY_LEAF(leaf, subleaf, &p->tmul.raw[subleaf]); + break; + default: COPY_LEAF(leaf, XEN_CPUID_NO_SUBLEAF, &p->basic.raw[leaf]); break; @@ -496,6 +551,20 @@ int x86_cpuid_copy_from_buffer(struct cp array_access_nospec(p->xstate.raw, data.subleaf) =3D l; break; =20 + case 0x1d: + if ( data.subleaf >=3D ARRAY_SIZE(p->tile.raw) ) + goto out_of_range; + + array_access_nospec(p->tile.raw, data.subleaf) =3D l; + break; + + case 0x1e: + if ( data.subleaf >=3D ARRAY_SIZE(p->tmul.raw) ) + goto out_of_range; + + array_access_nospec(p->tmul.raw, data.subleaf) =3D l; + break; + default: if ( data.subleaf !=3D XEN_CPUID_NO_SUBLEAF ) goto out_of_range; --- a/xen/lib/x86/policy.c +++ b/xen/lib/x86/policy.c @@ -7,6 +7,7 @@ int x86_cpu_policies_are_compatible(cons struct cpu_policy_errors *err) { struct cpu_policy_errors e =3D INIT_CPU_POLICY_ERRORS; + unsigned int i; int ret =3D -EINVAL; =20 #define NA XEN_CPUID_NO_SUBLEAF @@ -21,6 +22,31 @@ int x86_cpu_policies_are_compatible(cons if ( guest->cpuid->feat.max_subleaf > host->cpuid->feat.max_subleaf ) FAIL_CPUID(7, 0); =20 + if ( (guest->cpuid->feat.amx_tile && !guest->cpuid->tile.max_palette) = || + guest->cpuid->tile.max_palette > host->cpuid->tile.max_palette ) + FAIL_CPUID(0x1d, 0); + + for ( i =3D 1; i <=3D guest->cpuid->tile.max_palette; ++i ) + { + const typeof(guest->cpuid->tile.palette[0]) *gt, *ht; + + gt =3D &guest->cpuid->tile.palette[i]; + ht =3D &host->cpuid->tile.palette[i]; + + if ( gt->tot_bytes !=3D ht->tot_bytes || + gt->bytes_per_tile !=3D ht->bytes_per_tile || + gt->bytes_per_row !=3D ht->bytes_per_row || + !gt->num_regs || gt->num_regs > ht->num_regs || + !gt->max_rows || gt->max_rows > ht->max_rows ) + FAIL_CPUID(0x1d, i); + } + + if ( ((guest->cpuid->feat.amx_int8 || guest->cpuid->feat.amx_bf16) && + (!guest->cpuid->tmul.maxk || !guest->cpuid->tmul.maxn)) || + guest->cpuid->tmul.maxk > host->cpuid->tmul.maxk || + guest->cpuid->tmul.maxn > host->cpuid->tmul.maxn ) + FAIL_CPUID(0x1e, 0); + if ( guest->cpuid->extd.max_leaf > host->cpuid->extd.max_leaf ) FAIL_CPUID(0x80000000, NA); =20 --- a/xen/lib/x86/private.h +++ b/xen/lib/x86/private.h @@ -17,13 +17,17 @@ =20 #else =20 +#include #include #include #include #include #include =20 +#define ASSERT assert + #include +#include #include =20 #include From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619103154; cv=none; d=zohomail.com; s=zohoarc; b=AlwlGTOg1b1cAlyUlp4O7MvSH2syY3w7Clm5iGeueIuLpSKNmDh50YhJRXZI/KSSY7ojPFgDD2PyxSxsCjLC3pCM2Cr1movxU5eUnX05jZk7/uICogLoHaZzAxBc0lB5WpJz3DwHYraLt+pQqAg1hpnGffykbsF925GNI/j94yo= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103133; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2hIV80jisyRvLb5ihKMWW9bM/ay0CiKgh0ql2H5RsPM=; b=tm24H5NP5jna4E6UlW1SBaKovSvPN3k+uf5i/MctxiWNKJim911uRL2h7cp337Ze6RhuKc ciJkhYkM7biBUY0fiQaI8qNXHQ+6bTgUTnUM0y/AZP5bGZkskfa4X0W/PXBDlw9N1+vAqS pgwwY1I5lvgXfsTbF/9LyezIqbm1qIk= Subject: [PATCH v3 13/22] x86: XFD enabling From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Ian Jackson , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= , Anthony Perard References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <6f09bf89-6272-c9c0-1391-2620d6851b67@suse.com> Date: Thu, 22 Apr 2021 16:52:13 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" Just like for XCR0 we generally want to run with the guest settings of the involved MSRs while in Xen. Hence saving/restoring of guest values needs to only happen during context switch. While adding the feature to libxl's table I've noticed the other XSAVE sub-features all don't have entries there. These get added at the same time. Signed-off-by: Jan Beulich --- v3: New. --- I wasn't sure whether we want to have AMX depend on XFD. Purely from a spec pov the two are independent features (without XFD one simply wouldn't have a way to disable it for the purpose of lazy allocation of state saving space). --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -237,6 +237,12 @@ int libxl_cpuid_parse_config(libxl_cpuid {"fsrs", 0x00000007, 1, CPUID_REG_EAX, 11, 1}, {"fsrcs", 0x00000007, 1, CPUID_REG_EAX, 12, 1}, =20 + {"xsaveopt", 0x0000000d, 1, CPUID_REG_EAX, 0, 1}, + {"xsavec", 0x0000000d, 1, CPUID_REG_EAX, 1, 1}, + {"xgetbv1", 0x0000000d, 1, CPUID_REG_EAX, 2, 1}, + {"xsaves", 0x0000000d, 1, CPUID_REG_EAX, 3, 1}, + {"xfd", 0x0000000d, 1, CPUID_REG_EAX, 4, 1}, + {"lahfsahf", 0x80000001, NA, CPUID_REG_ECX, 0, 1}, {"cmplegacy", 0x80000001, NA, CPUID_REG_ECX, 1, 1}, {"svm", 0x80000001, NA, CPUID_REG_ECX, 2, 1}, --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -116,6 +116,7 @@ static const char *const str_Da1[32] =3D { [ 0] =3D "xsaveopt", [ 1] =3D "xsavec", [ 2] =3D "xgetbv1", [ 3] =3D "xsaves", + [ 4] =3D "xfd", }; =20 static const char *const str_7c0[32] =3D --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -230,6 +230,7 @@ static void recalculate_xstate(struct cp p->xstate.comp[i].offset =3D xstate_offset(i); p->xstate.comp[i].xss =3D curr_xstate & XSTATE_XSAVES_ONLY; p->xstate.comp[i].align =3D curr_xstate & xstate_align; + p->xstate.comp[i].xfd =3D curr_xstate & xfd_mask; } } =20 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1837,6 +1837,12 @@ void paravirt_ctxt_switch_to(struct vcpu =20 if ( cpu_has_msr_tsc_aux ) wrmsr_tsc_aux(v->arch.msrs->tsc_aux); + + if ( v->domain->arch.cpuid->xstate.xfd ) + { + wrmsrl(MSR_XFD, v->arch.msrs->xfd); + wrmsrl(MSR_XFD_ERR, v->arch.msrs->xfd_err); + } } =20 /* Update per-VCPU guest runstate shared memory area (if registered). */ --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1101,6 +1101,8 @@ long arch_do_domctl( static const uint32_t msrs_to_send[] =3D { MSR_SPEC_CTRL, MSR_INTEL_MISC_FEATURES_ENABLES, + MSR_XFD, + MSR_XFD_ERR, MSR_TSC_AUX, MSR_AMD64_DR0_ADDRESS_MASK, MSR_AMD64_DR1_ADDRESS_MASK, --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -1178,6 +1178,12 @@ static int construct_vmcs(struct vcpu *v if ( (vmexit_ctl & VM_EXIT_CLEAR_BNDCFGS) && (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) ) vmx_clear_msr_intercept(v, MSR_IA32_BNDCFGS, VMX_MSR_RW); + + if ( d->arch.cpuid->xstate.xfd ) + { + vmx_clear_msr_intercept(v, MSR_XFD, VMX_MSR_RW); + vmx_clear_msr_intercept(v, MSR_XFD_ERR, VMX_MSR_RW); + } } =20 /* I/O access bitmap. */ --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -539,6 +539,12 @@ static void vmx_save_guest_msrs(struct v */ v->arch.hvm.vmx.shadow_gs =3D read_gs_shadow(); =20 + if ( v->domain->arch.cpuid->xstate.xfd ) + { + rdmsrl(MSR_XFD, msrs->xfd); + rdmsrl(MSR_XFD_ERR, msrs->xfd_err); + } + if ( v->arch.hvm.vmx.ipt_active ) { rdmsrl(MSR_RTIT_OUTPUT_MASK, msrs->rtit.output_mask); @@ -558,6 +564,12 @@ static void vmx_restore_guest_msrs(struc if ( cpu_has_msr_tsc_aux ) wrmsr_tsc_aux(msrs->tsc_aux); =20 + if ( v->domain->arch.cpuid->xstate.xfd ) + { + wrmsrl(MSR_XFD, msrs->xfd); + wrmsrl(MSR_XFD_ERR, msrs->xfd_err); + } + if ( v->arch.hvm.vmx.ipt_active ) { wrmsrl(MSR_RTIT_OUTPUT_BASE, page_to_maddr(v->vmtrace.pg)); --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -29,6 +29,7 @@ #include #include #include +#include =20 #include =20 @@ -267,6 +268,18 @@ int guest_rdmsr(struct vcpu *v, uint32_t *val =3D msrs->misc_features_enables.raw; break; =20 + case MSR_XFD: + case MSR_XFD_ERR: + if ( !cp->xstate.xfd ) + goto gp_fault; + if ( v =3D=3D curr && is_hvm_domain(d) ) + rdmsrl(msr, *val); + else if ( msr =3D=3D MSR_XFD ) + *val =3D msrs->xfd; + else + *val =3D msrs->xfd_err; + break; + case MSR_IA32_MCG_CAP ... MSR_IA32_MCG_CTL: /* 0x179 -> 0x17b= */ case MSR_IA32_MCx_CTL2(0) ... MSR_IA32_MCx_CTL2(31): /* 0x280 -> 0x29f= */ case MSR_IA32_MCx_CTL(0) ... MSR_IA32_MCx_MISC(31): /* 0x400 -> 0x47f= */ @@ -523,6 +536,19 @@ int guest_wrmsr(struct vcpu *v, uint32_t break; } =20 + case MSR_XFD: + case MSR_XFD_ERR: + if ( !cp->xstate.xfd || + (val & ~(cpuid_policy_xstates(cp) & xfd_mask)) ) + goto gp_fault; + if ( v =3D=3D curr ) + wrmsrl(msr, val); + if ( msr =3D=3D MSR_XFD ) + msrs->xfd =3D val; + else + msrs->xfd_err =3D val; + break; + case MSR_IA32_MCG_CAP ... MSR_IA32_MCG_CTL: /* 0x179 -> 0x17b= */ case MSR_IA32_MCx_CTL2(0) ... MSR_IA32_MCx_CTL2(31): /* 0x280 -> 0x29f= */ case MSR_IA32_MCx_CTL(0) ... MSR_IA32_MCx_MISC(31): /* 0x400 -> 0x47f= */ --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -29,6 +29,10 @@ u64 __read_mostly xfeature_mask; =20 u64 __read_mostly xstate_align; + +/* Mask of XSAVE/XRSTOR features supporting XFD. */ +uint64_t __read_mostly xfd_mask; + static unsigned int __read_mostly xstate_features; =20 uint32_t __read_mostly mxcsr_mask =3D 0x0000ffbf; @@ -106,6 +110,11 @@ static int setup_xstate_features(bool bs __set_bit(leaf, &xstate_align); else BUG_ON(!(ecx & XSTATE_ALIGN64) !=3D !test_bit(leaf, &xstate_al= ign)); + + if ( bsp && (ecx & XSTATE_XFD) ) + __set_bit(leaf, &xfd_mask); + else + BUG_ON(!(ecx & XSTATE_XFD) !=3D !test_bit(leaf, &xfd_mask)); } =20 return 0; --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -69,6 +69,10 @@ #define MSR_MCU_OPT_CTRL 0x00000123 #define MCU_OPT_CTRL_RNGDS_MITG_DIS (_AC(1, ULL) << 0) =20 +/* Bits within these two MSRs share positions with XCR0. */ +#define MSR_XFD 0x000001c4 +#define MSR_XFD_ERR 0x000001c5 + #define MSR_RTIT_OUTPUT_BASE 0x00000560 #define MSR_RTIT_OUTPUT_MASK 0x00000561 #define MSR_RTIT_CTL 0x00000570 --- a/xen/include/asm-x86/msr.h +++ b/xen/include/asm-x86/msr.h @@ -343,6 +343,12 @@ struct vcpu_msrs uint64_t raw; } xss; =20 + /* 0x000001c4 - MSR_XFD */ + uint64_t xfd; + + /* 0x000001c5 - MSR_XFD_ERR */ + uint64_t xfd_err; + /* * 0xc0000103 - MSR_TSC_AUX * --- a/xen/include/asm-x86/xstate.h +++ b/xen/include/asm-x86/xstate.h @@ -39,9 +39,11 @@ extern uint32_t mxcsr_mask; #define XSTATE_COMPACTION_ENABLED (1ULL << 63) =20 #define XSTATE_ALIGN64 (1U << 1) +#define XSTATE_XFD (1U << 2) =20 extern u64 xfeature_mask; extern u64 xstate_align; +extern uint64_t xfd_mask; =20 #define xstate_offset(n) (raw_cpuid_policy.xstate.comp[n].offset) #define xstate_size(n) (raw_cpuid_policy.xstate.comp[n].size) --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -191,6 +191,7 @@ XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) / XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=3D1 */ XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ +XEN_CPUFEATURE(XFD, 4*32+ 4) /* XFD / XFD_ERR MSRs */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instruction= s */ --- a/xen/include/xen/lib/x86/cpuid.h +++ b/xen/include/xen/lib/x86/cpuid.h @@ -222,7 +222,7 @@ struct cpuid_policy /* Per-component common state. Valid for i >=3D 2. */ struct { uint32_t size, offset; - bool xss:1, align:1; + bool xss:1, align:1, xfd:1; uint32_t _res_d; } comp[CPUID_GUEST_NR_XSTATE]; } xstate; --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -221,7 +221,7 @@ def crunch_numbers(state): # are instructions built on top of base XSAVE, while others are new # instruction groups which are specified to require XSAVE for state # management. - XSAVE: [XSAVEOPT, XSAVEC, XGETBV1, XSAVES, + XSAVE: [XSAVEOPT, XSAVEC, XGETBV1, XSAVES, XFD, AVX, MPX, PKU, AMX_TILE, LWP], =20 # AVX is taken to mean hardware support for 256bit registers (whic= h in From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Thu, 22 Apr 2021 14:53:07 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id c5a7a2ae-3752-4c6a-a4f1-b1c71f1aebc7; Thu, 22 Apr 2021 14:53:06 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id B6228B12C; Thu, 22 Apr 2021 14:53:05 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c5a7a2ae-3752-4c6a-a4f1-b1c71f1aebc7 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103185; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x3YA7TeiA4XEzSJsFpFCqRC4Ay1WG3ZSQOmpYlC59ls=; b=r5Z3tPJLVcwGOEtqjSxBpldVS0yvlI56I7r2/8H4JXvKLeoi/rQQl1S6Hl6RpemlmklXQV GhrToU6siwujuJBRrR970qEXTIO4MBfBoN/Yn43i4doVwpLnNKfU3TxYx3HBn+LUg982VA yVjnK3+O7BTOOh6dx9vzlx9rg79F5mc= Subject: [PATCH v3 14/22] x86emul: introduce X86EMUL_FPU_{tilecfg,tile} From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <3472a5ac-3b59-157f-ba21-997f5e726e4b@suse.com> Date: Thu, 22 Apr 2021 16:53:05 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" These will be used by AMX insns. They're not sensitive to CR0.TS, but instead some are sensitive to XFD. Signed-off-by: Jan Beulich --- v3: Separate X86EMUL_FPU_tilecfg. Use XFD alternative logic instead of checking CR0.TS. v2: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1420,6 +1420,13 @@ static int _get_fpu( return X86EMUL_UNHANDLEABLE; break; =20 + case X86EMUL_FPU_tilecfg: + case X86EMUL_FPU_tile: + ASSERT(mode_64bit()); + if ( !(xcr0 & X86_XCR0_TILECFG) || !(xcr0 & X86_XCR0_TILEDATA) ) + return X86EMUL_UNHANDLEABLE; + break; + default: break; } @@ -1429,6 +1436,7 @@ static int _get_fpu( if ( rc =3D=3D X86EMUL_OKAY ) { unsigned long cr0; + uint64_t xcr0_needed =3D 0; =20 fail_if(type =3D=3D X86EMUL_FPU_fpu && !ops->put_fpu); =20 @@ -1453,15 +1461,45 @@ static int _get_fpu( /* Should be unreachable if VEX decoding is working correctly.= */ ASSERT((cr0 & X86_CR0_PE) && !(ctxt->regs->eflags & X86_EFLAGS= _VM)); } - if ( cr0 & X86_CR0_EM ) + + switch ( type ) + { + default: + if ( cr0 & X86_CR0_EM ) + { + generate_exception_if(type =3D=3D X86EMUL_FPU_fpu, EXC_NM); + generate_exception_if(type =3D=3D X86EMUL_FPU_mmx, EXC_UD); + generate_exception_if(type =3D=3D X86EMUL_FPU_xmm, EXC_UD); + } + generate_exception_if((cr0 & X86_CR0_TS) && + (type !=3D X86EMUL_FPU_wait || + (cr0 & X86_CR0_MP)), + EXC_NM); + break; + + case X86EMUL_FPU_tilecfg: + break; + + case X86EMUL_FPU_tile: + xcr0_needed =3D X86_XCR0_TILEDATA; + break; + } + + if ( xcr0_needed && ctxt->cpuid->xstate.xfd ) { - generate_exception_if(type =3D=3D X86EMUL_FPU_fpu, EXC_NM); - generate_exception_if(type =3D=3D X86EMUL_FPU_mmx, EXC_UD); - generate_exception_if(type =3D=3D X86EMUL_FPU_xmm, EXC_UD); + uint64_t xfd; + + fail_if(!ops->read_msr); + rc =3D ops->read_msr(MSR_XFD, &xfd, ctxt); + if ( rc =3D=3D X86EMUL_OKAY && (xfd & xcr0_needed) ) + { + fail_if(!ops->write_msr); + rc =3D ops->read_msr(MSR_XFD_ERR, &xfd, ctxt); + if ( rc =3D=3D X86EMUL_OKAY ) + rc =3D ops->write_msr(MSR_XFD_ERR, xfd | xcr0_needed, = ctxt); + generate_exception_if(rc =3D=3D X86EMUL_OKAY, EXC_NM); + } } - generate_exception_if((cr0 & X86_CR0_TS) && - (type !=3D X86EMUL_FPU_wait || (cr0 & X86_CR= 0_MP)), - EXC_NM); } =20 done: --- a/xen/arch/x86/x86_emulate/x86_emulate.h +++ b/xen/arch/x86/x86_emulate/x86_emulate.h @@ -172,6 +172,8 @@ enum x86_emulate_fpu_type { X86EMUL_FPU_ymm, /* AVX/XOP instruction set (%ymm0-%ymm7/15) */ X86EMUL_FPU_opmask, /* AVX512 opmask instruction set (%k0-%k7) */ X86EMUL_FPU_zmm, /* AVX512 instruction set (%zmm0-%zmm7/31) */ + X86EMUL_FPU_tilecfg, /* AMX configuration (tilecfg) */ + X86EMUL_FPU_tile, /* AMX instruction set (%tmm0-%tmmN) */ /* This sentinel will never be passed to ->get_fpu(). */ X86EMUL_FPU_none }; From nobody Wed May 8 02:51:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Thu, 22 Apr 2021 14:53:30 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id B094CAEC6; Thu, 22 Apr 2021 14:53:29 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 8ee80abb-0a83-4cae-83a6-abef09b90889 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103209; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6sH9ZStUceyjzleVNMQ/IZlMigDXrBHjCjtxo39B/zw=; b=mmEZ8yopdhasVdP8JPkF1gdcQ9LRt5DkRhQday7xIOXKH/wtWcIza0syOhw0SxQnsY8CCr bT7zuZUJEZnTIgYSasDqiOVscO2FvFjNgJedH/ltWvuqyDAkuumdC1zdxR3eOE1Ld2OeLV qMnEh8eo1RjdUH6oC3m6BcKcBKeUyAQ= Subject: [PATCH v3 15/22] x86emul: support TILERELEASE From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <08ce1e1f-f521-3e7d-3f7c-206e8ba0afa3@suse.com> Date: Thu, 22 Apr 2021 16:53:29 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" This is relatively straightforward, and hence best suited to introduce a few other general pieces. Testing of this will be added once a sensible test can be put together, i.e. when support for other insns is also there. Signed-off-by: Jan Beulich --- v2: New. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1335,6 +1335,7 @@ static const struct vex { { { 0x45 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsrlv{d,q} */ { { 0x46 }, 2, T, R, pfx_66, W0, Ln }, /* vpsravd */ { { 0x47 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsllv{d,q} */ + { { 0x49, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tilerelease */ { { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */ { { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */ { { 0x52 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssd */ --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -247,6 +247,10 @@ int emul_test_get_fpu( break; default: return X86EMUL_UNHANDLEABLE; + + case X86EMUL_FPU_tilecfg: + case X86EMUL_FPU_tile: + return cpu_has_amx_tile ? X86EMUL_OKAY : X86EMUL_UNHANDLEABLE; } return X86EMUL_OKAY; } --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -475,6 +475,7 @@ static const struct ext0f38_table { [0x43] =3D { .simd_size =3D simd_scalar_vexw, .d8s =3D d8s_dq }, [0x44] =3D { .simd_size =3D simd_packed_int, .two_op =3D 1, .d8s =3D d= 8s_vl }, [0x45 ... 0x47] =3D { .simd_size =3D simd_packed_int, .d8s =3D d8s_vl = }, + [0x49] =3D { .simd_size =3D simd_other, .two_op =3D 1 }, [0x4c] =3D { .simd_size =3D simd_packed_fp, .two_op =3D 1, .d8s =3D d8= s_vl }, [0x4d] =3D { .simd_size =3D simd_scalar_vexw, .d8s =3D d8s_dq }, [0x4e] =3D { .simd_size =3D simd_packed_fp, .two_op =3D 1, .d8s =3D d8= s_vl }, @@ -2046,6 +2047,7 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx512_4fmaps() (ctxt->cpuid->feat.avx512_4fmaps) #define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2inters= ect) #define vcpu_has_serialize() (ctxt->cpuid->feat.serialize) +#define vcpu_has_amx_tile() (ctxt->cpuid->feat.amx_tile) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) =20 @@ -9500,6 +9502,24 @@ x86_emulate( generate_exception_if(vex.l, EXC_UD); goto simd_0f_avx; =20 + case X86EMUL_OPC_VEX(0x0f38, 0x49): + generate_exception_if(!mode_64bit() || vex.l || vex.w, EXC_UD); + if ( ea.type =3D=3D OP_REG ) + { + switch ( modrm ) + { + case 0xc0: /* tilerelease */ + host_and_vcpu_must_have(amx_tile); + get_fpu(X86EMUL_FPU_tilecfg); + op_bytes =3D 1; /* fake */ + goto simd_0f_common; + + default: + goto unrecognized_insn; + } + } + goto unimplemented_insn; + case X86EMUL_OPC_VEX_66(0x0f38, 0x50): /* vpdpbusd [xy]mm/mem,[xy]mm,[= xy]mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x51): /* vpdpbusds [xy]mm/mem,[xy]mm,= [xy]mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x52): /* vpdpwssd [xy]mm/mem,[xy]mm,[= xy]mm */ --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -133,6 +133,7 @@ #define cpu_has_avx512_vp2intersect boot_cpu_has(X86_FEATURE_AVX512_VP2INT= ERSECT) #define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) #define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE) +#define cpu_has_amx_tile boot_cpu_has(X86_FEATURE_AMX_TILE) =20 /* CPUID level 0x00000007:1.eax */ #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) From nobody Wed May 8 02:51:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 22 Apr 2021 14:53:59 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 084e26c9-62dc-41a8-91ce-30799c849cb7; Thu, 22 Apr 2021 14:53:58 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 07DEEABB1; Thu, 22 Apr 2021 14:53:58 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 084e26c9-62dc-41a8-91ce-30799c849cb7 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103238; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=M6XR0QmmTejtrJcAjrfXrTJZ6XGbzGG7Zeqjm+UvbQ8=; b=J7MjrzDZ4cpYV3cK4wCeLjdQ2DCVmKFWSgSHkpbntrVMZhF9C90a+gYJR2omoa/xSxDeat UZpwODr0ZWpk+acLQ+NpIoGDxjYIYstBW7nNCpWI5VPsQlQjkZKyZmQqRPWPkfFAneAKju WCDNrj/AlWVV8yz95HFzimwqo8SgS6A= Subject: [PATCH v3 16/22] x86: introduce struct for TILECFG register From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <022f5561-8c90-e5c5-9a9c-1878ef17518c@suse.com> Date: Thu, 22 Apr 2021 16:53:58 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" Introduce a new x86-types.h to hold various architectural type definitions, the TILECFG register layout being the first. Arrange for the insn emulator to include this header. Signed-off-by: Jan Beulich --- v3: New. --- a/tools/fuzz/x86_instruction_emulator/Makefile +++ b/tools/fuzz/x86_instruction_emulator/Makefile @@ -26,7 +26,7 @@ GCOV_FLAGS :=3D --coverage $(CC) -c $(CFLAGS) $(GCOV_FLAGS) $< -o $@ =20 x86.h :=3D $(addprefix $(XEN_ROOT)/tools/include/xen/asm/,\ - x86-vendors.h x86-defns.h msr-index.h) \ + x86-vendors.h x86-types.h x86-defns.h msr-index.h) \ $(addprefix $(XEN_ROOT)/tools/include/xen/lib/x86/, \ cpuid.h cpuid-autogen.h) x86_emulate.h :=3D x86-emulate.h x86_emulate/x86_emulate.h $(x86.h) --- a/tools/tests/x86_emulator/Makefile +++ b/tools/tests/x86_emulator/Makefile @@ -284,7 +284,7 @@ $(call cc-option-add,HOSTCFLAGS-x86_64,H HOSTCFLAGS +=3D $(CFLAGS_xeninclude) -I. $(HOSTCFLAGS-$(XEN_COMPILE_ARCH)) =20 x86.h :=3D $(addprefix $(XEN_ROOT)/tools/include/xen/asm/,\ - x86-vendors.h x86-defns.h msr-index.h) \ + x86-vendors.h x86-types.h x86-defns.h msr-index.h) \ $(addprefix $(XEN_ROOT)/tools/include/xen/lib/x86/, \ cpuid.h cpuid-autogen.h) x86_emulate.h :=3D x86-emulate.h x86_emulate/x86_emulate.h $(x86.h) --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -37,6 +37,7 @@ =20 #include #include +#include #include =20 #include --- a/xen/arch/x86/x86_emulate.c +++ b/xen/arch/x86/x86_emulate.c @@ -17,6 +17,7 @@ #include #include /* cpu_has_amd_erratum() */ #include +#include =20 /* Avoid namespace pollution. */ #undef cmpxchg --- /dev/null +++ b/xen/include/asm-x86/x86-types.h @@ -0,0 +1,14 @@ +#ifndef __XEN_X86_TYPES_H__ +#define __XEN_X86_TYPES_H__ + +/* + * TILECFG register + */ +struct x86_tilecfg { + uint8_t palette, start_row; + uint8_t res[14]; + uint16_t colsb[16]; + uint8_t rows[16]; +}; + +#endif /* __XEN_X86_TYPES_H__ */ From nobody Wed May 8 02:51:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619103285; cv=none; d=zohomail.com; s=zohoarc; b=MqIreURUDLjbgHiZ0/nsp7wHZNrfBhsppS7R9ySGOj2BCx44pkEXM8KGS+rUTVryG03ya38sVC6lMGIBrnXpQmS/LjUPBw3Iivk9l0+9qRdnhwk2Mh4q0F6gkcwJu0HaG6F+RpZaaAzK1V6F6Lx9JMv+GRnUjeWGfWDCFvJInUc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1619103285; 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a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103267; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hH9PSsalwPjUONIbbOKjEItk1Fxab7kog6ux7w948mE=; b=thTtqfwvMmd1dLsc11sQSY7GZ7y6SwDLiyQ3dqx602i/a7p6Q1l1++V40QmVpSgqT4djRa OfrzfMLo7m+S0LQs5LoLbR9JkBQsWSGjBo3/aE+RDcumHOLhYaAM+L+Ty1RxdbshCSHwiZ VH3LpMmRNJ5mHCkm5o8nFY9D2S7qgck= Subject: [PATCH v3 17/22] x86emul: support {LD,ST}TILECFG From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: Date: Thu, 22 Apr 2021 16:54:27 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" While ver 043 of the ISA extensions doc also specifies xcr0_supports_palette() returning false as one of the #GP(0) reasons for LDTILECFG, the earlier #UD / #GP conditions look to make this fully dead. Signed-off-by: Jan Beulich --- v3: Rebase over struct x86_tilecfg introduction. v2: New. --- SDE: -spr --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1335,6 +1335,8 @@ static const struct vex { { { 0x45 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsrlv{d,q} */ { { 0x46 }, 2, T, R, pfx_66, W0, Ln }, /* vpsravd */ { { 0x47 }, 2, T, R, pfx_66, Wn, Ln }, /* vpsllv{d,q} */ + { { 0x49, 0x00 }, 2, F, R, pfx_no, W0, L0 }, /* ldtilecfg */ + { { 0x49, 0x00 }, 2, F, W, pfx_66, W0, L0 }, /* sttilecfg */ { { 0x49, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tilerelease */ { { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */ { { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */ --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -898,6 +898,11 @@ int main(int argc, char **argv) int rc; #ifdef __x86_64__ unsigned int vendor_native; + static const struct x86_tilecfg tilecfg =3D { + .palette =3D 1, + .colsb =3D { 2, 4, 5, 3 }, + .rows =3D { 2, 4, 3, 5 }, + }; #else unsigned int bcdres_native, bcdres_emul; #endif @@ -4463,6 +4468,74 @@ int main(int argc, char **argv) printf("skipped\n"); =20 #ifdef __x86_64__ + printf("%-40s", "Testing tilerelease;sttilecfg 4(%rcx)..."); + if ( stack_exec && cpu_has_amx_tile ) + { + decl_insn(tilerelease); + + asm volatile ( put_insn(tilerelease, + /* tilerelease */ + ".byte 0xC4, 0xE2, 0x78, 0x49, 0xC0;" + /* sttilecfg 4(%0) */ + ".byte 0xC4, 0xE2, 0x79, 0x49, 0x41, 0x04") + :: "c" (NULL) ); + + memset(res, ~0, 72); + set_insn(tilerelease); + regs.ecx =3D (unsigned long)res; + rc =3D x86_emulate(&ctxt, &emulops); + if ( rc =3D=3D X86EMUL_OKAY ) + rc =3D x86_emulate(&ctxt, &emulops); + if ( rc !=3D X86EMUL_OKAY || !check_eip(tilerelease) || + ~res[0] || ~res[17] || memchr_inv(res + 1, 0, 64) ) + goto fail; + printf("okay\n"); + } + else + printf("skipped\n"); + + printf("%-40s", "Testing ldtilecfg (%rdx)..."); + if ( stack_exec && cpu_has_amx_tile ) + { + decl_insn(ldtilecfg); + + asm volatile ( put_insn(ldtilecfg, + /* ldtilecfg (%0) */ + ".byte 0xC4, 0xE2, 0x78, 0x49, 0x02") + :: "d" (NULL) ); + + set_insn(ldtilecfg); + regs.edx =3D (unsigned long)&tilecfg; + rc =3D x86_emulate(&ctxt, &emulops); + if ( rc !=3D X86EMUL_OKAY || !check_eip(ldtilecfg) ) + goto fail; + printf("pending\n"); + } + else + printf("skipped\n"); + + printf("%-40s", "Testing sttilecfg -4(%rcx)..."); + if ( stack_exec && cpu_has_amx_tile ) + { + decl_insn(sttilecfg); + + asm volatile ( put_insn(sttilecfg, + /* sttilecfg -4(%0) */ + ".byte 0xC4, 0xE2, 0x79, 0x49, 0x41, 0xFC") + :: "c" (NULL) ); + + memset(res, ~0, 72); + set_insn(sttilecfg); + regs.ecx =3D (unsigned long)(res + 2); + rc =3D x86_emulate(&ctxt, &emulops); + if ( rc !=3D X86EMUL_OKAY || !check_eip(sttilecfg) || + ~res[0] || ~res[17] || memcmp(res + 1, &tilecfg, 64) ) + goto fail; + printf("okay\n"); + } + else + printf("skipped\n"); + printf("%-40s", "Testing vzeroupper (compat)..."); if ( cpu_has_avx ) { --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -68,6 +68,17 @@ =20 #define is_canonical_address(x) (((int64_t)(x) >> 47) =3D=3D ((int64_t)(x)= >> 63)) =20 +static inline void *memchr_inv(const void *s, int c, size_t n) +{ + const unsigned char *p =3D s; + + while ( n-- ) + if ( (unsigned char)c !=3D *p++ ) + return (void *)(p - 1); + + return NULL; +} + extern uint32_t mxcsr_mask; extern struct cpuid_policy cp; =20 @@ -171,6 +182,8 @@ static inline bool xcr0_mask(uint64_t ma #define cpu_has_avx512_4fmaps (cp.feat.avx512_4fmaps && xcr0_mask(0xe6)) #define cpu_has_avx512_vp2intersect (cp.feat.avx512_vp2intersect && xcr0_m= ask(0xe6)) #define cpu_has_serialize cp.feat.serialize +#define cpu_has_amx_tile (cp.feat.amx_tile && \ + xcr0_mask(X86_XCR0_TILECFG | X86_XCR0_TILEDATA= )) #define cpu_has_avx_vnni (cp.feat.avx_vnni && xcr0_mask(6)) #define cpu_has_avx512_bf16 (cp.feat.avx512_bf16 && xcr0_mask(0xe6)) =20 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -957,6 +957,7 @@ typedef union { uint64_t __attribute__ ((aligned(16))) xmm[2]; uint64_t __attribute__ ((aligned(32))) ymm[4]; uint64_t __attribute__ ((aligned(64))) zmm[8]; + struct x86_tilecfg tilecfg; uint32_t data32[16]; } mmval_t; =20 @@ -2880,6 +2881,10 @@ x86_decode_0f38( state->simd_size =3D simd_scalar_vexw; break; =20 + case X86EMUL_OPC_VEX_66(0, 0x49): /* sttilecfg */ + state->desc =3D DstMem | SrcImplicit | Mov; + break; + case X86EMUL_OPC_EVEX_66(0, 0x7a): /* vpbroadcastb */ case X86EMUL_OPC_EVEX_66(0, 0x7b): /* vpbroadcastw */ case X86EMUL_OPC_EVEX_66(0, 0x7c): /* vpbroadcast{d,q} */ @@ -9518,7 +9523,66 @@ x86_emulate( goto unrecognized_insn; } } - goto unimplemented_insn; + + switch ( modrm_reg & 7 ) + { + case 0: /* ldtilecfg mem */ + generate_exception_if(vex.reg !=3D 0xf, EXC_UD); + host_and_vcpu_must_have(amx_tile); + get_fpu(X86EMUL_FPU_tilecfg); + rc =3D ops->read(ea.mem.seg, ea.mem.off, mmvalp, 64, ctxt); + if ( rc !=3D X86EMUL_OKAY ) + goto done; + generate_exception_if((mmvalp->tilecfg.palette > + ctxt->cpuid->tile.max_palette), + EXC_GP, 0); + if ( mmvalp->tilecfg.palette ) + { + const typeof(*ctxt->cpuid->tile.palette) *palette; + + generate_exception_if(memchr_inv(mmvalp->tilecfg.res, 0, + sizeof(mmvalp->tilecfg.re= s)), + EXC_GP, 0); + + /* + * Parameters for valid registers must be within bounds, or + * both be zero at the same time. + */ + palette =3D &ctxt->cpuid->tile.palette[mmvalp->tilecfg.pal= ette]; + for ( i =3D 0; i < palette->num_regs; ++i ) + generate_exception_if(((mmvalp->tilecfg.colsb[i] > + palette->bytes_per_row) || + (mmvalp->tilecfg.rows[i] > + palette->max_rows) || + (!mmvalp->tilecfg.colsb[i] !=3D + !mmvalp->tilecfg.rows[i])), + EXC_GP, 0); + + /* All remaining entries must be zero. */ + for ( ; i < 16; ++i ) + generate_exception_if((mmvalp->tilecfg.colsb[i] || + mmvalp->tilecfg.rows[i]), + EXC_GP, 0); + } + op_bytes =3D 64; + goto simd_0f_common; + } + goto unrecognized_insn; + + case X86EMUL_OPC_VEX_66(0x0f38, 0x49): + generate_exception_if(!mode_64bit() || vex.l || vex.w, EXC_UD); + if ( ea.type =3D=3D OP_REG ) + goto unrecognized_insn; + + switch ( modrm_reg & 7 ) + { + case 0: /* sttilecfg mem */ + host_and_vcpu_must_have(amx_tile); + get_fpu(X86EMUL_FPU_tilecfg); + op_bytes =3D 64; + goto simd_0f_common; + } + goto unrecognized_insn; =20 case X86EMUL_OPC_VEX_66(0x0f38, 0x50): /* vpdpbusd [xy]mm/mem,[xy]mm,[= xy]mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x51): /* vpdpbusds [xy]mm/mem,[xy]mm,= [xy]mm */ From nobody Wed May 8 02:51:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 22 Apr 2021 14:55:09 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id d38beecf-193e-4509-a67c-88b993647bf2; Thu, 22 Apr 2021 14:55:08 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 67C13B16D; Thu, 22 Apr 2021 14:55:07 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d38beecf-193e-4509-a67c-88b993647bf2 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103307; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wgsKprQTlfADQ7Dypqlzd3WaFpCIjsLFSBPxGBvAlYo=; b=Z5jbW+Ic6sr7FGZtl64EWJU2IZjQNZ4aS32ryqANItdFgZJu5ix68GkEcRx1AEMMDGqBxM zQdX2Kb5I7w3RMwMNINosct+C+hM8k16O5KdVQ7xEILlaSZMRAhrnEjKJruYxQBkvug+X0 55croDHU8wUqhVoK23YwLB9BmoB3Swc= Subject: [PATCH v3 18/22] x86emul: support TILEZERO From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: Date: Thu, 22 Apr 2021 16:55:07 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" This is relatively straightforward, and hence best suited to introduce a few other wider use pieces. Testing of this will be added once a sensible test can be put together, i.e. when support for at least TILELOADD (to allow loading non-zero values in the first place) is also there. Signed-off-by: Jan Beulich --- v3: New. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1338,6 +1338,7 @@ static const struct vex { { { 0x49, 0x00 }, 2, F, R, pfx_no, W0, L0 }, /* ldtilecfg */ { { 0x49, 0x00 }, 2, F, W, pfx_66, W0, L0 }, /* sttilecfg */ { { 0x49, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tilerelease */ + { { 0x49, 0xc0 }, 2, F, N, pfx_f2, W0, L0 }, /* tilezero */ { { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */ { { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */ { { 0x52 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssd */ --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -3725,6 +3725,31 @@ x86_decode( #undef insn_fetch_bytes #undef insn_fetch_type =20 +#ifndef X86EMUL_NO_SIMD + +static void sttilecfg(struct x86_tilecfg *tilecfg) +{ + /* sttilecfg (%rdi) */ + asm volatile ( ".byte 0xc4, 0xe2, 0x79, 0x49, 0x07" + : "=3Dm" (*tilecfg) : "D" (tilecfg) ); +} + +static bool tiles_configured(const struct x86_tilecfg *tilecfg) +{ + return tilecfg->palette; +} + +static bool tile_valid(unsigned int tile, const struct x86_tilecfg *tilecf= g) +{ + /* + * Considering the checking LDTILECFG does, checking either would in + * principle be sufficient. + */ + return tilecfg->colsb[tile] && tilecfg->rows[tile]; +} + +#endif /* X86EMUL_NO_SIMD */ + /* Undo DEBUG wrapper. */ #undef x86_emulate =20 @@ -9584,6 +9609,29 @@ x86_emulate( } goto unrecognized_insn; =20 + case X86EMUL_OPC_VEX_F2(0x0f38, 0x49): + generate_exception_if(!mode_64bit() || vex.l || vex.w, EXC_UD); + if ( ea.type =3D=3D OP_REG ) + { + switch ( modrm_rm & 7 ) + { + case 0: /* tilezero */ + host_and_vcpu_must_have(amx_tile); + get_fpu(X86EMUL_FPU_tile); + sttilecfg(&mmvalp->tilecfg); + generate_exception_if(!tiles_configured(&mmvalp->tilecfg), + EXC_UD); + generate_exception_if(!tile_valid(modrm_reg, &mmvalp->tile= cfg), + EXC_UD); + op_bytes =3D 1; /* fake */ + goto simd_0f_common; + + default: + goto unrecognized_insn; + } + } + goto unrecognized_insn; + case X86EMUL_OPC_VEX_66(0x0f38, 0x50): /* vpdpbusd [xy]mm/mem,[xy]mm,[= xy]mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x51): /* vpdpbusds [xy]mm/mem,[xy]mm,= [xy]mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x52): /* vpdpwssd [xy]mm/mem,[xy]mm,[= xy]mm */ From nobody Wed May 8 02:51:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 22 Apr 2021 14:55:34 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id d4822181-164a-43d5-9cf2-1d3d2045b90d; Thu, 22 Apr 2021 14:55:33 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id D31C5ABB1; Thu, 22 Apr 2021 14:55:32 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d4822181-164a-43d5-9cf2-1d3d2045b90d X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103332; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8Q5FkhdLlmlc3eXCKxLrkqvoccRo5UNs3ZV3phIMfFs=; b=RI6y651llBkueekrHXf8xnzFGVhQkclhdphQZbybEakWNTkxa0s0SskApvdyJ073gLXfQ/ ibmnVxiznO4QPFN0RqiYFRNjB8jBW0WoO8b5fgPsxWY1ysDMfZvbOyC77/b/10WAegArmb Xp/T/zC+pYVLm66IqQWfxmA4hMK17ts= Subject: [PATCH v3 19/22] x86emul: support TILELOADD{,T1} and TILESTORE From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: Date: Thu, 22 Apr 2021 16:55:33 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" In order to be flexible about future growth of tile dimensions, use a separately allocated scratch buffer to read/write individual rows of a tile. Note that the separate write_tilecfg() function is needed because LDTILECFG wouldn't serve the purpose: It clears various state, unlike XRSTOR / XRSTORC. To keep things simple, the test harness variant of it leverages the state save/restore around library calls. To be sure the actual data gets restored (and not init state put in place), any extra override for the XSTATE_BV field is introduced. Signed-off-by: Jan Beulich --- v3: New. --- TBD: ISA extensions document 043 doesn't clarify either way whether duplicate stores to the same (linear) memory ranges may get squashed by TILESTORED just like is documented for AVX-512 scatters. For now similar behavior is assumed (or else hvm/emulate.c's respective checking would need altering, or we'd need to exit back to guest context after every individual row, albeit that would mean allowing interrupts to occur in the middle of an insn); an inquiry on the public forum [1] was left unanswered so far. [1] https://community.intel.com/t5/Intel-ISA-Extensions/TILESTORED-to-overl= apping-addresses/td-p/1226953 --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1339,6 +1339,9 @@ static const struct vex { { { 0x49, 0x00 }, 2, F, W, pfx_66, W0, L0 }, /* sttilecfg */ { { 0x49, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tilerelease */ { { 0x49, 0xc0 }, 2, F, N, pfx_f2, W0, L0 }, /* tilezero */ + { { 0x4b, VSIB(0) }, 3, F, R, pfx_66, W0, L0 }, /* tileloaddt1 */ + { { 0x4b, VSIB(0) }, 3, F, W, pfx_f3, W0, L0 }, /* tilestored */ + { { 0x4b, VSIB(0) }, 3, F, R, pfx_f2, W0, L0 }, /* tileloadd */ { { 0x50 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusd */ { { 0x51 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpbusds */ { { 0x52 }, 2, T, R, pfx_66, W0, Ln }, /* vpdpwssd */ --- a/tools/tests/x86_emulator/x86-emulate.c +++ b/tools/tests/x86_emulator/x86-emulate.c @@ -35,6 +35,8 @@ struct cpuid_policy cp; =20 static char fpu_save_area[0x4000] __attribute__((__aligned__((64)))); static bool use_xsave; +/* This will get OR-ed into xstate_bv prior to restoring state. */ +static uint64_t xstate_bv_or_mask; =20 /* * Re-use the area above also as scratch space for the emulator itself. @@ -57,13 +59,19 @@ void emul_restore_fpu_state(void) { /* Older gcc can't deal with "m" array inputs; make them outputs inste= ad. */ if ( use_xsave ) + { + *(uint64_t *)&fpu_save_area[0x200] |=3D xstate_bv_or_mask; + xstate_bv_or_mask =3D 0; asm volatile ( "xrstor %[ptr]" : [ptr] "+m" (fpu_save_area) : "a" (~0ul), "d" (~0ul) ); + } else asm volatile ( "fxrstor %0" : "+m" (fpu_save_area) ); } =20 +static void *tile_row; + bool emul_test_init(void) { union { @@ -121,6 +129,19 @@ bool emul_test_init(void) if ( fxs->mxcsr_mask ) mxcsr_mask =3D fxs->mxcsr_mask; =20 + if ( cpu_has_amx_tile ) + { + unsigned int i, max_bytes =3D 0; + + for ( i =3D 1; i <=3D cp.tile.max_palette; ++i ) + if ( cp.tile.palette[i].bytes_per_row > max_bytes ) + max_bytes =3D cp.tile.palette[i].bytes_per_row; + + if ( !cp.xstate.comp[X86_XCR0_TILECFG_POS].offset || + !max_bytes || !(tile_row =3D malloc(max_bytes)) ) + cp.feat.amx_tile =3D false; + } + /* * Mark the entire stack executable so that the stub executions * don't fault @@ -263,4 +284,22 @@ void emul_test_put_fpu( /* TBD */ } =20 +static void *get_tile_row_buf(void) +{ + return tile_row; +} + +WRAPPER(memcpy); + +static void write_tilecfg(const struct x86_tilecfg *tilecfg) +{ + /* + * Leverage the fact that the wrapper (saves and) restores all extended + * state around the actual library call. + */ + xstate_bv_or_mask =3D X86_XCR0_TILECFG; + emul_memcpy(fpu_save_area + cp.xstate.comp[X86_XCR0_TILECFG_POS].offse= t, + tilecfg, sizeof(*tilecfg)); +} + #include "x86_emulate/x86_emulate.c" --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -98,8 +98,9 @@ void emul_restore_fpu_state(void); # if 0 /* This only works for explicit calls, not for compiler generated o= nes. */ # define WRAP(x) typeof(x) x asm("emul_" #x) # else -# define WRAP(x) asm(".equ " #x ", emul_" #x) +# define WRAP(x) asm(".equ " #x ", emul_" #x) # endif +# define WRAPPER(x) typeof(x) emul_##x #endif =20 WRAP(fwrite); --- a/xen/arch/x86/x86_emulate.c +++ b/xen/arch/x86/x86_emulate.c @@ -9,6 +9,7 @@ * Keir Fraser */ =20 +#include #include #include #include @@ -52,6 +53,71 @@ # define X86EMUL_NO_SIMD #endif =20 +#ifndef X86EMUL_NO_SIMD + +static DEFINE_PER_CPU_READ_MOSTLY(void *, tile_row); +static unsigned int __read_mostly tile_row_max_bytes; + +static int amx_cpu_init(struct notifier_block *nfb, + unsigned long action, void *hcpu) +{ + int rc =3D 0; + void **prow =3D &per_cpu(tile_row, (unsigned long)hcpu); + + switch ( action ) + { + case CPU_UP_PREPARE: + *prow =3D xmalloc_array(uint8_t, tile_row_max_bytes); + if ( !*prow ) + rc =3D -ENOMEM; + break; + + case CPU_UP_CANCELED: + case CPU_DEAD: + XFREE(*prow); + break; + } + + return !rc ? NOTIFY_DONE : notifier_from_errno(rc); +} + +static struct notifier_block amx_cpu_nfb =3D { + .notifier_call =3D amx_cpu_init, +}; + +static int __init amx_init(void) +{ + const struct cpuid_policy *p =3D &host_cpuid_policy; + unsigned int i; + + if ( !cpu_has_amx_tile ) + return 0; + + for ( i =3D 1; i <=3D p->tile.max_palette; ++i ) + if ( p->tile.palette[i].bytes_per_row > tile_row_max_bytes ) + tile_row_max_bytes =3D p->tile.palette[i].bytes_per_row; + + if ( !tile_row_max_bytes ) + { + setup_clear_cpu_cap(X86_FEATURE_AMX_TILE); + return 0; + } + + amx_cpu_init(&amx_cpu_nfb, CPU_UP_PREPARE, + (void *)(unsigned long)smp_processor_id()); + register_cpu_notifier(&amx_cpu_nfb); + + return 0; +} +presmp_initcall(amx_init); + +static void *get_tile_row_buf(void) +{ + return this_cpu(tile_row); +} + +#endif /* X86EMUL_NO_SIMD */ + #include "x86_emulate/x86_emulate.c" =20 int x86emul_read_xcr(unsigned int reg, uint64_t *val, --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -476,6 +476,7 @@ static const struct ext0f38_table { [0x44] =3D { .simd_size =3D simd_packed_int, .two_op =3D 1, .d8s =3D d= 8s_vl }, [0x45 ... 0x47] =3D { .simd_size =3D simd_packed_int, .d8s =3D d8s_vl = }, [0x49] =3D { .simd_size =3D simd_other, .two_op =3D 1 }, + [0x4b] =3D { .simd_size =3D simd_other, .two_op =3D 1, .vsib =3D 1 }, [0x4c] =3D { .simd_size =3D simd_packed_fp, .two_op =3D 1, .d8s =3D d8= s_vl }, [0x4d] =3D { .simd_size =3D simd_scalar_vexw, .d8s =3D d8s_dq }, [0x4e] =3D { .simd_size =3D simd_packed_fp, .two_op =3D 1, .d8s =3D d8= s_vl }, @@ -2882,6 +2883,7 @@ x86_decode_0f38( break; =20 case X86EMUL_OPC_VEX_66(0, 0x49): /* sttilecfg */ + case X86EMUL_OPC_VEX_F3(0, 0x4b): /* tilestored */ state->desc =3D DstMem | SrcImplicit | Mov; break; =20 @@ -9632,6 +9634,99 @@ x86_emulate( } goto unrecognized_insn; =20 + case X86EMUL_OPC_VEX_66(0x0f38, 0x4b): /* tileloaddt1 mem,tmm */ + case X86EMUL_OPC_VEX_F3(0x0f38, 0x4b): /* tilestored tmm,mem */ + case X86EMUL_OPC_VEX_F2(0x0f38, 0x4b): /* tileloadd mem,tmm */ + { + struct x86_tilecfg *cfg =3D &mmvalp->tilecfg; + void *row; + + generate_exception_if(!mode_64bit() || vex.l || vex.w || vex.reg != =3D 0xf, + EXC_UD); + host_and_vcpu_must_have(amx_tile); + get_fpu(X86EMUL_FPU_tile); + sttilecfg(cfg); + generate_exception_if(!tiles_configured(cfg), EXC_UD); + generate_exception_if(!tile_valid(modrm_reg, cfg), EXC_UD); + generate_exception_if(cfg->colsb[modrm_reg] & 3, EXC_UD); + i =3D cfg->start_row; + n =3D cfg->rows[modrm_reg]; + generate_exception_if(i >=3D n, EXC_UD); + + /* Calculate stride. */ + if ( state->sib_index !=3D 4 ) + ea.val =3D truncate_ea(*decode_gpr(state->regs, + state->sib_index) << + state->sib_scale); + + if ( vex.pfx =3D=3D vex_f3 ) + { + /* + * hvmemul_linear_mmio_access() will find a cache slot based on + * linear address. hvmemul_phys_mmio_access() will crash the + * domain if observing varying data getting written to the same + * cache slot. Assume that squashing earlier writes to fully + * overlapping addresses is permitted (like for AVX-512 scatte= rs). + */ + if ( !ea.val ) + i =3D n - 1; + else if ( !(ea.val & + ((1ul << ((ad_bytes - sizeof(*cfg->rows)) * 8)) - = 1)) ) + { + unsigned int clr =3D __builtin_ffsl(ea.val) - 1; + unsigned int iter =3D 1u << (ad_bytes * 8 - clr); + + if ( iter < n - i ) + i =3D n - iter; + } + } + + row =3D get_tile_row_buf(); + memset(row, -1, + ctxt->cpuid->tile.palette[cfg->palette].bytes_per_row); + + /* Set up stub. */ + opc =3D init_prefixes(stub); + opc[0] =3D b; + /* Convert memory operand to (%rax,%riz,1) */ + vex.b =3D 1; + vex.x =3D 1; + opc[1] =3D modrm & 0x3f; + opc[2] =3D 0x20; + opc[3] =3D 0xc3; + copy_VEX(opc, vex); + + do { + /* Limit rows to just as many to cover the next one to access.= */ + cfg->start_row =3D i; + cfg->rows[modrm_reg] =3D i + 1; + write_tilecfg(cfg); + + if ( vex.pfx !=3D vex_f3 ) + rc =3D ops->read(ea.mem.seg, + truncate_ea(ea.mem.off + i * ea.val), + row, cfg->colsb[modrm_reg], ctxt); + + invoke_stub("", "", "=3Dm" (dummy) : "a" (row)); + + if ( vex.pfx =3D=3D vex_f3 ) + rc =3D ops->write(ea.mem.seg, + truncate_ea(ea.mem.off + i * ea.val), + row, cfg->colsb[modrm_reg], ctxt); + } while ( rc =3D=3D X86EMUL_OKAY && ++i < n ); + + put_stub(stub); + + if ( rc =3D=3D X86EMUL_OKAY ) + cfg->start_row =3D 0; + cfg->rows[modrm_reg] =3D n; + write_tilecfg(cfg); + + state->simd_size =3D simd_none; + dst.type =3D OP_NONE; + break; + } + case X86EMUL_OPC_VEX_66(0x0f38, 0x50): /* vpdpbusd [xy]mm/mem,[xy]mm,[= xy]mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x51): /* vpdpbusds [xy]mm/mem,[xy]mm,= [xy]mm */ case X86EMUL_OPC_VEX_66(0x0f38, 0x52): /* vpdpwssd [xy]mm/mem,[xy]mm,[= xy]mm */ --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 /* * Maximum size (in byte) of the XSAVE/XRSTOR save area required by all @@ -840,6 +841,37 @@ uint64_t read_bndcfgu(void) return xstate->xsave_hdr.xstate_bv & X86_XCR0_BNDCSR ? bndcsr->bndcfgu= : 0; } =20 +void write_tilecfg(const struct x86_tilecfg *tilecfg) +{ + unsigned long cr0 =3D read_cr0(); + struct xsave_struct *xstate + =3D idle_vcpu[smp_processor_id()]->arch.xsave_area; + + ASSERT(cpu_has_amx_tile); + clts(); + + memset(&xstate->xsave_hdr, 0, sizeof(xstate->xsave_hdr)); + xstate->xsave_hdr.xstate_bv =3D X86_XCR0_TILECFG; + + if ( cpu_has_xsavec ) + { + xstate->xsave_hdr.xcomp_bv =3D XSTATE_COMPACTION_ENABLED | + X86_XCR0_TILECFG; + + memcpy(xstate + 1, tilecfg, sizeof(*tilecfg)); + } + else + memcpy((void *)xstate + xstate_offset(X86_XCR0_TILECFG_POS), + tilecfg, sizeof(*tilecfg)); + + asm volatile ( ".byte 0x0f,0xae,0x2f\n" /* xrstor */ + :: "m" (*xstate), "D" (xstate), + "a" (X86_XCR0_TILECFG), "d" (0) ); + + if ( cr0 & X86_CR0_TS ) + write_cr0(cr0); +} + void xstate_set_init(uint64_t mask) { unsigned long cr0 =3D read_cr0(); --- a/xen/include/asm-x86/xstate.h +++ b/xen/include/asm-x86/xstate.h @@ -93,6 +93,8 @@ uint64_t get_xcr0(void); void set_msr_xss(u64 xss); uint64_t get_msr_xss(void); uint64_t read_bndcfgu(void); +struct x86_tilecfg; +void write_tilecfg(const struct x86_tilecfg *tilecfg); void xsave(struct vcpu *v, uint64_t mask); void xrstor(struct vcpu *v, uint64_t mask); void xstate_set_init(uint64_t mask); From nobody Wed May 8 02:51:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=quarantine dis=none) header.from=suse.com ARC-Seal: i=1; a=rsa-sha256; t=1619103394; cv=none; d=zohomail.com; s=zohoarc; b=aZXJ16QCVRUqlNiYu8j9u0BBBAnNLB3Hq+Ia7RJu2cfWwIvPHH8m/u+Za6I7TllXsdTAf6E+KpDW9tz1DGit2J55adrhnLqnEl0+qSo2IobL2Dy1yvJ14nG3b/QJyNAOkIlXUvB+2Ay7YvvYmBdvUNxMdfaBIGJrnBGM0jea/3U= ARC-Message-Signature: i=1; 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Thu, 22 Apr 2021 14:56:15 +0000 Received: by outflank-mailman (output) from mailman id 115562.220526; Thu, 22 Apr 2021 14:56:15 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZakZ-0006JF-2U; Thu, 22 Apr 2021 14:56:15 +0000 Received: by outflank-mailman (input) for mailman id 115562; Thu, 22 Apr 2021 14:56:13 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1lZakX-0006J3-SL for xen-devel@lists.xenproject.org; Thu, 22 Apr 2021 14:56:13 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id d8584a9d-4a1e-4881-916d-816828a3f1f5; Thu, 22 Apr 2021 14:56:12 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 1EA42ABB1; Thu, 22 Apr 2021 14:56:12 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: d8584a9d-4a1e-4881-916d-816828a3f1f5 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103372; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oPzs8oFNLCi5oM4f8KtDEq5j9aDmHv1L3If34/KJuW4=; b=Ea1YwjrfTjHdm6RC3GnBKBRVRAwBamaKIe8hjoe/AnGu1gzA/NUA36695NqufyYN2BQgMc 7vxDQLLV9bZY0lSTOBEpCR1eE0zexrKK5RaWGTvXz3SpYooHDDDB7UwStDwzZ+bVrSR+QF VrVou5J4UaXTRqPKIRTfbIb9sRF/PEQ= Subject: [PATCH v3 20/22] x86emul: support tile multiplication insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <33ff565f-0e08-4dc6-c041-ad3422544d54@suse.com> Date: Thu, 22 Apr 2021 16:56:12 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" Since these don't allow for memory operands, the main thing to do here is to check the large set of #UD conditions. Signed-off-by: Jan Beulich --- v3: New. --- a/tools/tests/x86_emulator/predicates.c +++ b/tools/tests/x86_emulator/predicates.c @@ -1349,6 +1349,11 @@ static const struct vex { { { 0x58 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastd */ { { 0x59 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastq */ { { 0x5a }, 2, F, R, pfx_66, W0, L1 }, /* vbroadcasti128 */ + { { 0x5c, 0xc0 }, 2, F, N, pfx_f3, W0, L0 }, /* tdpbf16ps */ + { { 0x5e, 0xc0 }, 2, F, N, pfx_no, W0, L0 }, /* tdpbuud */ + { { 0x5e, 0xc0 }, 2, F, N, pfx_66, W0, L0 }, /* tdpbusd */ + { { 0x5e, 0xc0 }, 2, F, N, pfx_f3, W0, L0 }, /* tdpbsud */ + { { 0x5e, 0xc0 }, 2, F, N, pfx_f2, W0, L0 }, /* tdpbssd */ { { 0x78 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastb */ { { 0x79 }, 2, T, R, pfx_66, W0, Ln }, /* vpbroadcastw */ { { 0x8c }, 2, F, R, pfx_66, Wn, Ln }, /* vpmaskmov{d,q} */ --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -487,6 +487,8 @@ static const struct ext0f38_table { [0x59] =3D { .simd_size =3D simd_other, .two_op =3D 1, .d8s =3D 3 }, [0x5a] =3D { .simd_size =3D simd_128, .two_op =3D 1, .d8s =3D 4 }, [0x5b] =3D { .simd_size =3D simd_256, .two_op =3D 1, .d8s =3D d8s_vl_b= y_2 }, + [0x5c] =3D { .simd_size =3D simd_other }, + [0x5e] =3D { .simd_size =3D simd_other }, [0x62] =3D { .simd_size =3D simd_packed_int, .two_op =3D 1, .d8s =3D d= 8s_bw }, [0x63] =3D { .simd_size =3D simd_packed_int, .to_mem =3D 1, .two_op = =3D 1, .d8s =3D d8s_bw }, [0x64 ... 0x66] =3D { .simd_size =3D simd_packed_int, .d8s =3D d8s_vl = }, @@ -2049,7 +2051,9 @@ amd_like(const struct x86_emulate_ctxt * #define vcpu_has_avx512_4fmaps() (ctxt->cpuid->feat.avx512_4fmaps) #define vcpu_has_avx512_vp2intersect() (ctxt->cpuid->feat.avx512_vp2inters= ect) #define vcpu_has_serialize() (ctxt->cpuid->feat.serialize) +#define vcpu_has_amx_bf16() (ctxt->cpuid->feat.amx_bf16) #define vcpu_has_amx_tile() (ctxt->cpuid->feat.amx_tile) +#define vcpu_has_amx_int8() (ctxt->cpuid->feat.amx_int8) #define vcpu_has_avx_vnni() (ctxt->cpuid->feat.avx_vnni) #define vcpu_has_avx512_bf16() (ctxt->cpuid->feat.avx512_bf16) =20 @@ -9799,6 +9803,59 @@ x86_emulate( generate_exception_if(ea.type !=3D OP_MEM || !vex.l || vex.w, EXC_= UD); goto simd_0f_avx2; =20 + case X86EMUL_OPC_VEX_F3(0x0f38, 0x5c): /* tdpbf16ps tmm,tmm,tmm */ + case X86EMUL_OPC_VEX(0x0f38, 0x5e): /* tdpbuud tmm,tmm,tmm */ + case X86EMUL_OPC_VEX_66(0x0f38, 0x5e): /* tdpbusd tmm,tmm,tmm */ + case X86EMUL_OPC_VEX_F3(0x0f38, 0x5e): /* tdpbsud tmm,tmm,tmm */ + case X86EMUL_OPC_VEX_F2(0x0f38, 0x5e): /* tdpbssd tmm,tmm,tmm */ + { + unsigned int vreg =3D vex.reg ^ 0xf; + + if ( ea.type !=3D OP_REG ) + goto unimplemented_insn; + generate_exception_if(!mode_64bit() || vex.l || vex.w, EXC_UD); + if ( b =3D=3D 0x5c ) + host_and_vcpu_must_have(amx_bf16); + else + host_and_vcpu_must_have(amx_int8); + generate_exception_if(modrm_reg =3D=3D modrm_rm, EXC_UD); + generate_exception_if(modrm_reg =3D=3D vreg, EXC_UD); + generate_exception_if(modrm_rm =3D=3D vreg, EXC_UD); + + get_fpu(X86EMUL_FPU_tile); + sttilecfg(&mmvalp->tilecfg); + generate_exception_if(!tiles_configured(&mmvalp->tilecfg), EXC_UD); + + /* accum: modrm_reg */ + generate_exception_if(!tile_valid(modrm_reg, &mmvalp->tilecfg), EX= C_UD); + /* src1: modrm_rm */ + generate_exception_if(!tile_valid(modrm_rm, &mmvalp->tilecfg), EXC= _UD); + /* src2: vreg */ + generate_exception_if(!tile_valid(vreg, &mmvalp->tilecfg), EXC_UD); + + generate_exception_if(mmvalp->tilecfg.colsb[modrm_reg] & 3, EXC_UD= ); + /* + * These are redundant with the check just below. + generate_exception_if(mmvalp->tilecfg.colsb[modrm_rm] & 3, EXC_UD); + generate_exception_if(mmvalp->tilecfg.colsb[vreg] & 3, EXC_UD); + */ + + generate_exception_if(mmvalp->tilecfg.rows[modrm_reg] !=3D + mmvalp->tilecfg.rows[modrm_rm], EXC_UD); + generate_exception_if(mmvalp->tilecfg.colsb[modrm_reg] !=3D + mmvalp->tilecfg.colsb[vreg], EXC_UD); + generate_exception_if(mmvalp->tilecfg.colsb[modrm_rm] !=3D + mmvalp->tilecfg.rows[vreg] * 4, EXC_UD); + + generate_exception_if(mmvalp->tilecfg.colsb[vreg] > + ctxt->cpuid->tmul.maxn, EXC_UD); + generate_exception_if(mmvalp->tilecfg.rows[vreg] > + ctxt->cpuid->tmul.maxk, EXC_UD); + + op_bytes =3D 1; /* fake */ + goto simd_0f_common; + } + case X86EMUL_OPC_EVEX_66(0x0f38, 0x62): /* vpexpand{b,w} [xyz]mm/mem,[= xyz]mm{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0x63): /* vpcompress{b,w} [xyz]mm,[xy= z]mm/mem{k} */ host_and_vcpu_must_have(avx512_vbmi2); --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -133,7 +133,9 @@ #define cpu_has_avx512_vp2intersect boot_cpu_has(X86_FEATURE_AVX512_VP2INT= ERSECT) #define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) #define cpu_has_serialize boot_cpu_has(X86_FEATURE_SERIALIZE) +#define cpu_has_amx_bf16 boot_cpu_has(X86_FEATURE_AMX_BF16) #define cpu_has_amx_tile boot_cpu_has(X86_FEATURE_AMX_TILE) +#define cpu_has_amx_int8 boot_cpu_has(X86_FEATURE_AMX_INT8) =20 /* CPUID level 0x00000007:1.eax */ #define cpu_has_avx_vnni boot_cpu_has(X86_FEATURE_AVX_VNNI) From nobody Wed May 8 02:51:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 22 Apr 2021 14:57:09 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 18ce7d23-7784-47a5-9f97-26855f358af4; Thu, 22 Apr 2021 14:57:07 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id D7905B183; Thu, 22 Apr 2021 14:57:05 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 18ce7d23-7784-47a5-9f97-26855f358af4 X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103426; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BnZJW8q+Psi2deBa+/DuTOElAH40rilmihBn23jtynU=; b=ufjUMTNSr5s1+ifoE88XzvrprycIhaeXF1PQfQPeI0SvDNYxjrSmNUmr0DAZcyD/FwrscJ PhirbSwZaeW2eJZ7RWyalbXuFHdOk90qji0C+/OIL1gGchNjiBcdU7/1I7gYytDCY4ONAS a5WQBcid15oAvZC75eJmOt8YyCthMjw= Subject: [PATCH v3 21/22] x86emul: test AMX insns From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: <19925d83-ae92-cdda-f5be-193cfb05c775@suse.com> Date: Thu, 22 Apr 2021 16:57:04 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" Carry out some basic matrix operations on 2x2, 3x3, and 4x4 matrixes. To also have a use of a non-square matrix, also transpose ones of said square formats via linearization and multiplication by the respective transposition permutation matrix. To generate the latter, introduce a small helper tool. This is mainly to avoid creating / populating a rather large matrix (up to 16x16) in a stack variable. Signed-off-by: Jan Beulich --- v3: New. --- a/tools/tests/x86_emulator/Makefile +++ b/tools/tests/x86_emulator/Makefile @@ -25,6 +25,12 @@ SHA :=3D sse4-sha avx-sha avx512f-sha GF :=3D sse2-gf avx2-gf avx512bw-gf TESTCASES :=3D blowfish $(SIMD) $(FMA) $(SG) $(AES) $(CLMUL) $(SHA) $(GF) =20 +MATRIX :=3D amx-bf16 amx-int8 + +ifeq ($(XEN_COMPILE_ARCH),x86_64) +TESTCASES +=3D $(MATRIX) +endif + OPMASK :=3D avx512f avx512dq avx512bw =20 ifeq ($(origin XEN_COMPILE_ARCH),override) @@ -96,6 +102,13 @@ avx512f-opmask-vecs :=3D 2 avx512dq-opmask-vecs :=3D 1 2 avx512bw-opmask-vecs :=3D 4 8 =20 +amx-bf16-dims :=3D 2 3 4 +amx-bf16-ints :=3D +amx-bf16-flts :=3D 2 +amx-int8-dims :=3D 2 3 4 +amx-int8-ints :=3D 1 +amx-int8-flts :=3D + # Suppress building by default of the harness if the compiler can't deal # with some of the extensions used. Don't alter the "run" target dependen= cies # though, as this target needs to be specified manually, and things may wo= rk @@ -170,6 +183,18 @@ endef define opmask-defs $(1)-opmask-cflags :=3D $(foreach vec,$($(1)-opmask-vecs), "-D_$(vec) -m$(= 1) -Os -DSIZE=3D$(vec)") endef +amx-cflags-common =3D $(CFLAGS_xeninclude) -Os -DN=3D$(1) -DTPM_H=3Dtpm-$(= 1)x$(1).h +define matrix-defs +$(1).h: $(foreach dim,$($(1)-dims),tpm-$(dim)x$(dim).h) +$(1)-cflags :=3D +$(1)-cflags-x86_64 :=3D \ + $(foreach dim,$($(1)-dims), \ + $(foreach flt,$($(1)-flts), \ + "-D_$(dim)x$(dim) -DFLOAT_SIZE=3D$(flt) $(call amx-cflags-common,$(di= m))") \ + $(foreach int,$($(1)-ints), \ + "-Di_$(dim)x$(dim) -DINT_SIZE=3D$(int) $(call amx-cflags-common,$(dim= ))" \ + "-Du_$(dim)x$(dim) -DUINT_SIZE=3D$(int) $(call amx-cflags-common,$(di= m))")) +endef =20 $(foreach flavor,$(SIMD) $(FMA),$(eval $(call simd-defs,$(flavor)))) $(foreach flavor,$(SG),$(eval $(call simd-sg-defs,$(flavor)))) @@ -178,6 +203,7 @@ $(foreach flavor,$(CLMUL),$(eval $(call $(foreach flavor,$(SHA),$(eval $(call simd-sha-defs,$(flavor)))) $(foreach flavor,$(GF),$(eval $(call simd-gf-defs,$(flavor)))) $(foreach flavor,$(OPMASK),$(eval $(call opmask-defs,$(flavor)))) +$(foreach flavor,$(MATRIX),$(eval $(call matrix-defs,$(flavor)))) =20 first-string =3D $(shell for s in $(1); do echo "$$s"; break; done) =20 @@ -248,6 +274,9 @@ $(addsuffix .h,$(SIMD) $(FMA) $(SG) $(AE =20 xop.h avx512f.h: simd-fma.c =20 +$(addsuffix .c,$(MATRIX)): + ln -sf matrix.c $@ + endif # 32-bit override =20 $(TARGET): x86-emulate.o cpuid.o test_x86_emulator.o evex-disp8.o predicat= es.o wrappers.o @@ -295,6 +324,12 @@ x86-emulate.o cpuid.o test_x86_emulator. x86-emulate.o: x86_emulate/x86_emulate.c x86-emulate.o: HOSTCFLAGS +=3D -D__XEN_TOOLS__ =20 +tpm-%.h: mktpm Makefile + set -x; ./$< $(subst x,$(space),$*) >$@ + +mktpm: mktpm.c + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< + # In order for our custom .type assembler directives to reliably land after # gcc's, we need to keep it from re-ordering top-level constructs. $(call cc-option-add,HOSTCFLAGS-toplevel,HOSTCC,-fno-toplevel-reorder) --- /dev/null +++ b/tools/tests/x86_emulator/matrix.c @@ -0,0 +1,229 @@ +#include + +typedef unsigned int __attribute__((mode(QI))) uint8_t; +typedef unsigned int __attribute__((mode(HI))) uint16_t; + +#define stringify_(x...) #x +#define stringify(x...) stringify_(x) + +#include + +asm ( "\t.text\n" + "\t.globl _start\n" + "_start:\n" + "\tjmp matrix_test" ); + +/* + * For the purposes here we consider the 32-bit elements to hold just a si= ngle + * value, with the other slots zero-filled. This way the 2- or 4-way dot + * products really end up as simple multiplications, allowing us to treat = the + * underlying insns as simple matrix multiply-and-accumulate ones. With + * suitably in-range numbers, this also allows us to have the compiler deal + * with, in particular, the bf16 fields without it actually knowing of suc= h a + * type. + * + * Notation in comments: + * I - identity matrix (all ones on the main diagonal) + * AI - all ones on the antidiagonal + */ + +typedef union { +#ifdef FLOAT_SIZE +# define MACC "tdpbf16ps" + float val; + float res; + struct { + unsigned int zero:16; + unsigned int bf16:16; + }; +#else +# ifdef INT_SIZE +# define SIGNED signed +# define MACC "tdpbssd" +# else +# define MACC "tdpbuud" +# define SIGNED unsigned +# endif + SIGNED int res; + struct { + SIGNED int val :8; + unsigned int zero:24; + }; +#endif +} elem_t; + +typedef elem_t tile_t[N][N]; + +static void ldtilecfg(const struct x86_tilecfg *cfg) +{ + asm volatile ( "ldtilecfg %0" :: "m" (*cfg) ); +} + +#define load_diag(r, v) ({ \ + struct { \ + elem_t arr[2 * N - 1]; \ + } in =3D { .arr[N - 1].val =3D (v) }; \ + asm volatile ( "tileloadd -%c[scale](%[base],%[stride],%c[scale]), %%"= #r \ + :: [base] "r" (&in.arr[N]), \ + [stride] "r" (-1L), \ + [scale] "i" (sizeof(elem_t)), \ + "m" (in) ); \ +}) + +#define load_antidiag(r, v) ({ \ + struct { \ + elem_t arr[2 * N - 1]; \ + } in =3D { .arr[N - 1].val =3D (v) }; \ + asm volatile ( "tileloadd (%[base],%[stride]), %%" #r \ + :: [base] "r" (&in.arr), \ + [stride] "r" (sizeof(elem_t)), \ + "m" (in) ); \ +}) + +#define load_linear(r, t) ({ \ + (void)((t) =3D=3D (const tile_t *)0); \ + asm volatile ( "tileloadd (%[base]), %%" #r \ + :: [base] "r" (t), \ + "m" (*(t)) ); \ +}) + +static const elem_t tpm[N * N][N * N] =3D { +#include stringify(TPM_H) +}; + +#define load_tpm(r) \ + asm volatile ( "tileloadd (%[base],%[stride],%c[scale]), %%" #r \ + :: [base] "r" (&tpm), \ + [stride] "r" (N * N * 1L), \ + [scale] "i" (sizeof(elem_t)), \ + "m" (tpm) ); \ + +#define store(t, r) ({ \ + (void)((t) =3D=3D (tile_t *)0); \ + asm volatile ( "tilestored %%" #r ", (%[base],%[stride],%c[scale])" \ + /* "+m" to keep the compiler from eliminating fill(). *= / \ + : "+m" (*(t)) \ + : [base] "r" (t), \ + [stride] "r" (N * 1L), \ + [scale] "i" (sizeof(elem_t)) ); \ +}) + +#define macc(srcdst, src1, src2) \ + asm volatile ( MACC " %" #src2 ", %" #src1 ", %" #srcdst ) + +#define mul(dst, src1, src2) ({ \ + asm volatile ( "tilezero %" #dst ); \ + macc(dst, src1, src2); \ +}) + +#define add(dst, src1, src2, scratch) ({ \ + load_diag(scratch, 1); \ + mul(dst, src1, scratch); \ + macc(dst, scratch, src2); \ +}) + +static inline void fill(tile_t *t) +{ + unsigned int cnt =3D N * N; + + asm ( "repe stosl" + : "=3Dm" (*t), "+D" (t), "+c" (cnt) + : "a" (~0) ); +} + +static inline bool zero(const tile_t *t) +{ + unsigned int cnt =3D N * N; + bool zf; + + asm ( "repe scasl" + : "=3D@ccz" (zf), "+D" (t), "+c" (cnt) + : "m" (*t), "a" (0) ); + + return zf; +} + +#define C(cols) ((cols) * sizeof(elem_t)) +#define R(rows) (rows) + +int matrix_test(void) +{ + struct x86_tilecfg cfg =3D { + .palette =3D 1, + .colsb =3D { C(N), C(N), C(N), C(N), 0, C(N * N), C(N * N), C(N = * N) }, + .rows =3D { R(N), R(N), R(N), R(N), 0, R(1), R(1), R(N = * N) }, + }; + tile_t x; + unsigned int i, j; + + ldtilecfg(&cfg); + + fill(&x); + store(&x, tmm0); + if ( !zero(&x) ) return __LINE__; + + /* Load and store I. */ + fill(&x); + load_diag(tmm0, 1); + store(&x, tmm0); + for ( i =3D 0; i < N; ++i ) + for ( j =3D 0; j < N; ++j ) + if ( x[i][j].res !=3D (i =3D=3D j) ) + return __LINE__; + + /* I + AI */ + fill(&x); + load_antidiag(tmm1, 1); + add(tmm2, tmm0, tmm1, tmm3); + store(&x, tmm2); + for ( i =3D 0; i < N; ++i ) + for ( j =3D 0; j < N; ++j ) + if ( i =3D=3D j && i + j =3D=3D N - 1 ) + { + if ( x[i][j].res !=3D 2 ) + return __LINE__; + } + else if ( i =3D=3D j || i + j =3D=3D N - 1 ) + { + if ( x[i][j].res !=3D 1 ) + return __LINE__; + } + else if ( x[i][j].res ) + return __LINE__; + +#ifndef UINT_SIZE + /* I + AI * -AI =3D=3D 0 */ + fill(&x); + load_antidiag(tmm2, -1); + macc(tmm0, tmm1, tmm2); + store(&x, tmm0); + if ( !zero(&x) ) return __LINE__; +#endif + + /* + * Transpose a matrix via linearization and multiplication by the + * respective transpostion permutation matrix. Note that linearization + * merely requires a different tile layout (see the initializer of cfg + * above). + */ +#ifdef UINT_SIZE +# define VAL(r, c) ((c) < (r) ? (c) : (r) + (c) ) +#else +# define VAL(r, c) ((c) < (r) ? -(r) : (r) + (c) ) +#endif + for ( i =3D 0; i < N; ++i ) + for (j =3D 0; j < N; ++j ) + x[i][j].val =3D VAL(i, j); + load_linear(tmm6, &x); + load_tpm(tmm7); + mul(tmm5, tmm6, tmm7); + /* There's just a single row, so re-use plain store() here. */ + store(&x, tmm5); + for ( i =3D 0; i < N; ++i ) + for (j =3D 0; j < N; ++j ) + if ( x[i][j].res !=3D VAL(j, i) ) + return __LINE__; +#undef VAL + + return 0; +} --- /dev/null +++ b/tools/tests/x86_emulator/mktpm.c @@ -0,0 +1,41 @@ +/* make Transposition Permutation Matrix */ + +#include +#include + +static void line(unsigned one, unsigned cols) +{ + unsigned i; + + printf(" { "); + for ( i =3D 0; i < cols - 1; ++i ) + printf("{ %d }, ", i =3D=3D one); + printf("{ %d } },\n", i =3D=3D one); +} + +int main(int argc, char*argv[]) +{ + unsigned i, j, m, n; + + switch ( argc ) + { + default: + fprintf(stderr, "Usage: %s []\n", argv[0]); + return argc !=3D 1; + + case 3: + n =3D strtoul(argv[2], NULL, 0); + /* fall-through */ + case 2: + m =3D strtoul(argv[1], NULL, 0); + if ( argc =3D=3D 2 ) + n =3D m; + break; + } + + for ( i =3D 0; i < m * n; ) + for ( j =3D i / n; j < m * n; j +=3D m, ++i ) + line(j, m * n); + + return 0; +} --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -44,6 +44,11 @@ asm ( ".pushsection .test, \"ax\", @prog #include "avx512vbmi.h" #include "avx512vbmi2-vpclmulqdq.h" =20 +#ifdef __x86_64__ +#include "amx-bf16.h" +#include "amx-int8.h" +#endif + #define verbose false /* Switch to true for far more logging. */ =20 static void blowfish_set_regs(struct cpu_user_regs *regs) @@ -263,6 +268,33 @@ static bool simd_check_regs(const struct return false; } =20 +#ifdef __x86_64__ + +static bool amx_check_bf16(void) +{ + return cp.feat.amx_bf16; +} + +static bool amx_check_int8(void) +{ + return cp.feat.amx_int8; +} + +static void amx_set_regs(struct cpu_user_regs *regs) +{ +} + +static bool amx_check_regs(const struct cpu_user_regs *regs) +{ + asm volatile ( ".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0" ); /* tilerelease = */ + if ( !regs->eax ) + return true; + printf("[line %u] ", (unsigned int)regs->eax); + return false; +} + +#endif + static const struct { const void *code; size_t size; @@ -534,6 +566,25 @@ static const struct { #undef AVX512VL #undef SIMD_ #undef SIMD +#ifdef __x86_64__ +# define AMX(desc, feat, t, dim) = \ + { .code =3D amx_ ## feat ## _x86_64_D ## t ## _ ## dim ## x ## dim, = \ + .size =3D sizeof(amx_ ## feat ## _x86_64_D ## t ## _ ## dim ## x ## = dim), \ + .bitness =3D 64, .name =3D "AMX-" #desc " (" #t #dim "x" #dim ")", = \ + .check_cpu =3D amx_check_ ## feat, = \ + .set_regs =3D amx_set_regs, = \ + .check_regs =3D amx_check_regs } + AMX(BF16, bf16, , 2), + AMX(BF16, bf16, , 3), + AMX(BF16, bf16, , 4), + AMX(INT8, int8, i, 2), + AMX(INT8, int8, i, 3), + AMX(INT8, int8, i, 4), + AMX(INT8, int8, u, 2), + AMX(INT8, int8, u, 3), + AMX(INT8, int8, u, 4), +# undef AMX +#endif }; =20 static unsigned int bytes_read; From nobody Wed May 8 02:51:57 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Thu, 22 Apr 2021 14:57:46 +0000 Received: from mx2.suse.de (unknown [195.135.220.15]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id 751cc7ac-e603-4a1f-a002-1c66535d470c; Thu, 22 Apr 2021 14:57:45 +0000 (UTC) Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 4F834B16A; Thu, 22 Apr 2021 14:57:44 +0000 (UTC) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 751cc7ac-e603-4a1f-a002-1c66535d470c X-Virus-Scanned: by amavisd-new at test-mx.suse.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1619103464; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0Kar8c0Mm+YFIHWmPbC+8g9omJWrv1zJZFI3hL51bIQ=; b=eBoUDSl4ml+KE6JjGdKtVsKE+2Wx9sR4QP1+q10TA8kbXIfKcC+zm84gssNoZHJdr0UWB7 sitgryWGEKbPDgd8TyrxPV2p9gvlA5b/Q48G/JA25MSVpy6bdgCyvyj0tdfcnLXqLXTa+Q Tdxo0rzbhLGtMx+1soYolNUJIghEpzY= Subject: [PATCH v3 22/22] x86: permit guests to use AMX and XFD From: Jan Beulich To: "xen-devel@lists.xenproject.org" Cc: Andrew Cooper , George Dunlap , Wei Liu , =?UTF-8?Q?Roger_Pau_Monn=c3=a9?= References: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Message-ID: Date: Thu, 22 Apr 2021 16:57:44 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <322de6db-e01f-0b57-5777-5d94a13c441a@suse.com> Content-Language: en-US Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @suse.com) Content-Type: text/plain; charset="utf-8" These features are marked experimental (for only parts of the code actually having got tested yet, while other parts require respective hardware) and opt-in for guests. Signed-off-by: Jan Beulich --- v3: New. --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,9 @@ The format is based on [Keep a Changelog =20 ## [unstable UNRELEASED](https://xenbits.xen.org/gitweb/?p=3Dxen.git;a=3Ds= hortlog;h=3Dstaging) - TBD =20 +### Added / support upgraded + - x86 AMX and XFD (Experimental) + ## [4.15.0 UNRELEASED](https://xenbits.xen.org/gitweb/?p=3Dxen.git;a=3Dsho= rtlog;h=3DRELEASE-4.15.0) - TBD =20 ### Added / support upgraded --- a/SUPPORT.md +++ b/SUPPORT.md @@ -61,6 +61,10 @@ For the Cortex A57 r0p0 - r1p1, see Erra =20 Status: Tech Preview =20 +### x86 AMX and XFD + + Status: Experimental + ### IOMMU =20 Status, AMD IOMMU: Supported --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -191,7 +191,7 @@ XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) / XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=3D1 */ XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ -XEN_CPUFEATURE(XFD, 4*32+ 4) /* XFD / XFD_ERR MSRs */ +XEN_CPUFEATURE(XFD, 4*32+ 4) /*a XFD / XFD_ERR MSRs */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instruction= s */ @@ -269,9 +269,9 @@ XEN_CPUFEATURE(MD_CLEAR, 9*32+10) / XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT = */ XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */ XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking= */ -XEN_CPUFEATURE(AMX_BF16, 9*32+22) /* AMX BFloat16 instructions */ -XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX tile architecture */ -XEN_CPUFEATURE(AMX_INT8, 9*32+25) /* AMX 8-bit integer instructions= */ +XEN_CPUFEATURE(AMX_BF16, 9*32+22) /*a AMX BFloat16 instructions */ +XEN_CPUFEATURE(AMX_TILE, 9*32+24) /*a AMX tile architecture */ +XEN_CPUFEATURE(AMX_INT8, 9*32+25) /*a AMX 8-bit integer instructions= */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by= Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */