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Tue, 16 Jun 2020 17:24:16 +0200 (CEST) Received: from belindir.nask.net.pl ([127.0.0.1]) by localhost (belindir.nask.net.pl [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id BU1h424fcYsI; Tue, 16 Jun 2020 17:24:11 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by belindir.nask.net.pl (Postfix) with ESMTP id 75AC0215F4; Tue, 16 Jun 2020 17:24:11 +0200 (CEST) Received: from belindir.nask.net.pl ([127.0.0.1]) by localhost (belindir.nask.net.pl [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id HFXNXOMpVXKA; Tue, 16 Jun 2020 17:24:11 +0200 (CEST) Received: from belindir.nask.net.pl (belindir.nask.net.pl [172.16.10.10]) by belindir.nask.net.pl (Postfix) with ESMTP id 594CB214C8; Tue, 16 Jun 2020 17:24:11 +0200 (CEST) X-Inumbo-ID: 842c0636-afe5-11ea-b7bb-bc764e2007e4 X-Virus-Scanned: amavisd-new at bagnar.nask.net.pl X-Virus-Scanned: amavisd-new at belindir.nask.net.pl Date: Tue, 16 Jun 2020 17:24:11 +0200 (CEST) From: =?utf-8?Q?Micha=C5=82_Leszczy=C5=84ski?= To: Xen-devel Message-ID: <317430261.8766476.1592321051337.JavaMail.zimbra@cert.pl> In-Reply-To: <1548605014.8764792.1592320576239.JavaMail.zimbra@cert.pl> References: <1548605014.8764792.1592320576239.JavaMail.zimbra@cert.pl> Subject: [PATCH v1 7/7] x86/vmx: switch IPT MSRs on vmentry/vmexit MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.16.10.10] X-Mailer: Zimbra 8.6.0_GA_1194 (ZimbraWebClient - GC83 (Win)/8.6.0_GA_1194) Thread-Topic: x86/vmx: switch IPT MSRs on vmentry/vmexit Thread-Index: KAn5ItxMsuAqHW3ZzkheyNf1oni9hiacNb1l X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Kevin Tian , Jun Nakajima , Wei Liu , Andrew Cooper , Jan Beulich , Roger Pau =?utf-8?Q?Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Content-Type: text/plain; charset="utf-8" Enable IPT when entering the VM and disable it on vmexit. Register state is persisted using vCPU ipt_state structure. Signed-off-by: Michal Leszczynski --- xen/arch/x86/hvm/vmx/vmx.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 97104c319e..01d9a7b584 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3698,6 +3698,15 @@ void vmx_vmexit_handler(struct cpu_user_regs *regs) __vmread(GUEST_RSP, ®s->rsp); __vmread(GUEST_RFLAGS, ®s->rflags); =20 + if ( unlikely(v->arch.hvm.vmx.ipt_state) ) + { + wrmsrl(MSR_IA32_RTIT_CTL, 0); + smp_rmb(); + + rdmsrl(MSR_IA32_RTIT_STATUS, v->arch.hvm.vmx.ipt_state->status); + rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, v->arch.hvm.vmx.ipt_state->outpu= t_mask); + } + hvm_invalidate_regs_fields(regs); =20 if ( paging_mode_hap(v->domain) ) @@ -4497,6 +4506,23 @@ bool vmx_vmenter_helper(const struct cpu_user_regs *= regs) } =20 out: + if ( unlikely(curr->arch.hvm.vmx.ipt_state) ) + { + wrmsrl(MSR_IA32_RTIT_CTL, 0); + + if (curr->arch.hvm.vmx.ipt_state->ctl) + { + wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, curr->arch.hvm.vmx.ipt_state= ->output_base); + wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, curr->arch.hvm.vmx.ipt_state= ->output_mask); + wrmsrl(MSR_IA32_RTIT_STATUS, curr->arch.hvm.vmx.ipt_state->sta= tus); + + // MSR_IA32_RTIT_CTL is context-switched manually instead of b= eing + // stored inside VMCS, as of Q2'20 only the most recent proces= sors + // support such field in VMCS + wrmsrl(MSR_IA32_RTIT_CTL, curr->arch.hvm.vmx.ipt_state->ctl); + } + } + if ( unlikely(curr->arch.hvm.vmx.lbr_flags & LBR_FIXUP_MASK) ) lbr_fixup(); =20 --=20 2.20.1