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[109.243.69.121]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5a4187e12e0sm3564564e87.51.2026.04.21.03.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 03:18:53 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776766735; x=1777371535; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=U1jc54BGtToaT12LTQTuzf+wdJ5L1Gzc0Hnuk+KSU3E=; b=fD+JmlI+AXOUVNf51VrV8JbEdfz+fH+yGUX4vdMTEPKBjG7Q7ztMl8JnSPW2gfbfjP VxrNLYj12kYkadFwnad3MIhFypIgNstlSxtU4Ddk1sWclDuKfOsoCcmv3KXChj4OXxuL j1KHMF6RRBagAlHDt/kORLIBq449X0YVs/sVcyk3F5fji5F1cLbPHyW2ChW8NrPAZsby PgZkBmmIqF0kYXLeR5FTIWf0siwt0cpi5fiZnj/N6JcfCnkD19k7c2D0N3UJUKikqvMr e0jde7AmqdkGNzx2zLus9bCPUlHmc026yFSmFpPNSMU8g3ddmZPp3Zo0ScBjiNnhbjVl Rx4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776766735; x=1777371535; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=U1jc54BGtToaT12LTQTuzf+wdJ5L1Gzc0Hnuk+KSU3E=; b=COwKmjNZOo95DZuGwa3MuOgH9MwDrK04SIWHhibv/bQ1YxaQhASL3c2e1MjYAlbceK 9X+DVY3T+xQdCSsm+QTBAqYIAKlOzNuBXWStorJucTaHox+NaeABBGjl0SmqqrfKueje Hq0K4LxdAAzxCwRMJc7A7T0Jb5elemHDJJgIDOzD0V5ZMQdShbQkPoNAgZuCDWaTkVzp 2nI4HdG8xBEolrRHMWKLQCT+mvbrX3AQJFlTzshnVxQJXhhCH7HBgdmQt+7QLOkkNTFF GK5gNABz9DzFF7jlFReLixdlbTyPMcYYnNG7/w8hCYtZrVxGzayXRkCpbk96z7/n2SIq zXCA== X-Gm-Message-State: AOJu0YzYDagfQDHqCu4B1N3dd5OMXutl8NnElIjBqnFszLt5qha7WYfg eB9JZhTJmbLlJ8UwXhgPSVtboJUtTVy0daGiOOaoko5q2vzzxGXoAd0CuynvvQ== X-Gm-Gg: AeBDiesV0IafGx+/ij/To3gHOqequx9F3xC+ux8l8AVlgVyZRYsbpvhd2R4fz3DdFgu 7mR9G989Nnubc2mLhKmz5a6i/c+UNKHgHhhhMOOOD4q/KH+1QB59z8kBK2M5DOODyvB91g4RGw4 IryNLvXvvOWpbRGjj5cMjk6gm/9IxlXnz5ur+3xXeTwitj5w+8WneBnuy0ke37cveQElxA9ciJ5 mzd/oDzkt/RmfIs6xWuUlAFKhMc7j2f9Y9k+XNfq7EyFWt/iJ5ZuJT+jnHSZZeFRUBOC5xUMnaV Qnv6rmMSLrV41+rqNICwGe4wRg/0ipMwhoZ+eaBON/NXkFkwun0Nefe6T6NrzBF+FKsJrI3yzev zeiL4slY33ibEv6pXU+9mtgQQBki53LYjTxKNoAevg/sjurhRB56ertBUo5ANK/UlpkcMJTqGSL FqvMczTM0OBWAVeuCoBCnxMy8srEHlOl4Jjd2fsveMIZ+ywd2poPCrgbQYf9hpnH/d3FoAKWmVz e1o X-Received: by 2002:a05:6512:138c:b0:5a4:6f3:e0a with SMTP id 2adb3069b0e04-5a417174ccamr5585750e87.8.1776766734014; Tue, 21 Apr 2026 03:18:54 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Romain Caritey Subject: [PATCH v5] xen/riscv: allow Xen to use SSTC while hiding it from guests Date: Tue, 21 Apr 2026 12:18:45 +0200 Message-ID: <2d5892447d6b6ad72962b8bbcb7c4d865b9e9989.1776765651.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-16d1c6/1776766735-90670D75-4D5EE2F0/10/73395122804 X-purgate-type: spam X-purgate-size: 13991 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1776766756644154100 Content-Type: text/plain; charset="utf-8" OpenSBI currently does not advertise the SSTC extension via the device tree, so if SSTC support is detected by Xen the riscv_isa bitmap is updated manually. Furthermore, removing the "sstc" string from riscv,isa is not a reliable way to disable SSTC, because OpenSBI probes support by attempting to access CSR_STIMECMP. Introduce a runtime probe in Xen to determine whether SSTC is available. The probe attempts to read CSR_STIMECMP using csr_read_safe(). If the access succeeds, SSTC is considered available; if a trap occurs, it is treated as unsupported. When SSTC is detected, Xen may use it internally to program timers. However, the extension is not exposed to guests because the required context switch handling for the SSTC CSRs is not yet implemented. Note: clearing RISCV_ISA_EXT_sstc from the DTS riscv,isa property is deferred to a follow-up patch. Also, the corresponding HENVCFG bit is not set so guests fall back to the SBI timer interface. Timer requests are then handled by Xen via the usual SBI interception path. Introduce set_xen_timer() to abstract how the timer is programmed, either via the SSTC extension or an SBI call. Drop sbi_set_timer() as it is more than enough to have only introduced set_xen_timer(). Drop "SBI v0.2 TIME extension detected" message to avoid confusion which set timer function is really used. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich ---- Changes in v5: - Update defintion of csr_write64() to avoid compilation issue. ---- Changes in v4: - Introduce csr_write64() and __csr_write32h(). - Sort numericaly definitions of CSR_VSTIMECMP{H}. --- Changes in v3: - Reword print message when SSTC extension is detected. - s/__clear_bit/__set_bit() for the case when SSTC is detected in riscv_fill_hwcap(). Update also the comment above __set_bit(). - Drop BUG_ON()s in vtimer.c. - s/printk/dprintk for the message: SSTC detected... - Drop sbi_set_timer global variable, it is enough just to have set_xen_ti= mer. - As we set bit in riscv_isa bitmap there is no need to use csr_read_safe(= CSR_STIMECMP) second time. - Move init of CSR_VSTIMECMP in preinit_xen_time as it looks more correct = place. - Update the commit message. --- Changes in v2: - Minor style fixes. - Drop from vcpu_csr_init() setting of SSTC bit in HENVCFG register. Add it back when SSTC for guests will be available. - Add static to set_xen_timer function pointer. - Refactor sstc_set_xen_timer(). - s/csr_allowed_read/csr_read_safe() --- xen/arch/riscv/cpufeature.c | 18 +++++++++ xen/arch/riscv/include/asm/cpufeature.h | 1 + xen/arch/riscv/include/asm/csr.h | 15 ++++++++ xen/arch/riscv/include/asm/riscv_encoding.h | 2 + xen/arch/riscv/include/asm/sbi.h | 18 --------- xen/arch/riscv/include/asm/time.h | 3 ++ xen/arch/riscv/sbi.c | 29 +++++++++++--- xen/arch/riscv/time.c | 42 +++++++++++++-------- xen/arch/riscv/vtimer.c | 1 + 9 files changed, 90 insertions(+), 39 deletions(-) diff --git a/xen/arch/riscv/cpufeature.c b/xen/arch/riscv/cpufeature.c index 03e27b037be0..92235fdfd5ab 100644 --- a/xen/arch/riscv/cpufeature.c +++ b/xen/arch/riscv/cpufeature.c @@ -17,6 +17,7 @@ #include =20 #include +#include =20 #ifdef CONFIG_ACPI # error "cpufeature.c functions should be updated to support ACPI" @@ -139,6 +140,7 @@ const struct riscv_isa_ext_data __initconst riscv_isa_e= xt[] =3D { RISCV_ISA_EXT_DATA(smaia), RISCV_ISA_EXT_DATA(smstateen), RISCV_ISA_EXT_DATA(ssaia), + RISCV_ISA_EXT_DATA(sstc), RISCV_ISA_EXT_DATA(svade), RISCV_ISA_EXT_DATA(svpbmt), }; @@ -483,6 +485,7 @@ void __init riscv_fill_hwcap(void) unsigned int i; const size_t req_extns_amount =3D ARRAY_SIZE(required_extensions); bool all_extns_available =3D true; + unsigned long tmp; =20 riscv_fill_hwcap_from_isa_string(); =20 @@ -495,6 +498,21 @@ void __init riscv_fill_hwcap(void) panic("HW capabilities parsing failed: %s\n", failure_msg); } =20 + if ( csr_read_safe(CSR_STIMECMP, &tmp) ) + { + dprintk(XENLOG_DEBUG, + "SSTC detected; supported for Xen use, but not for guests\= n"); + + /* + * As there is no any guarantee that SSTC will be added to riscv,i= sa + * property by OpenSBI(it doesn't add it now) or whatever ran befo= re + * Xen, it is needed to set this bit manually. + * + * Guest isolation is maintained by not setting ENVCFG_STCE in hen= vcfg. + */ + __set_bit(RISCV_ISA_EXT_sstc, riscv_isa); + } + for ( i =3D 0; i < req_extns_amount; i++ ) { const struct riscv_isa_ext_data ext =3D required_extensions[i]; diff --git a/xen/arch/riscv/include/asm/cpufeature.h b/xen/arch/riscv/inclu= de/asm/cpufeature.h index ef02a3e26d2c..0c48d57a03bb 100644 --- a/xen/arch/riscv/include/asm/cpufeature.h +++ b/xen/arch/riscv/include/asm/cpufeature.h @@ -38,6 +38,7 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_smaia, RISCV_ISA_EXT_smstateen, RISCV_ISA_EXT_ssaia, + RISCV_ISA_EXT_sstc, RISCV_ISA_EXT_svade, RISCV_ISA_EXT_svpbmt, RISCV_ISA_EXT_MAX diff --git a/xen/arch/riscv/include/asm/csr.h b/xen/arch/riscv/include/asm/= csr.h index 27d4b7942f6b..888d6a2a86d6 100644 --- a/xen/arch/riscv/include/asm/csr.h +++ b/xen/arch/riscv/include/asm/csr.h @@ -32,6 +32,21 @@ : "memory" ); \ }) =20 +#ifdef CONFIG_RISCV_32 +#define csr_write64(csr, val) \ +({ \ + uint64_t v_ =3D (val); \ + csr_write(csr, v_); \ + csr_write(csr ## H, v_ >> 32); \ +}) +#else +#define csr_write64(csr, val) \ +({ \ + csr_write(csr, val); \ + (void)csr ## H; \ +}) +#endif + #define csr_swap(csr, val) \ ({ \ unsigned long __v =3D (unsigned long)(val); \ diff --git a/xen/arch/riscv/include/asm/riscv_encoding.h b/xen/arch/riscv/i= nclude/asm/riscv_encoding.h index dd15731a86fa..03e186bcdb8c 100644 --- a/xen/arch/riscv/include/asm/riscv_encoding.h +++ b/xen/arch/riscv/include/asm/riscv_encoding.h @@ -395,6 +395,8 @@ #define CSR_VSCAUSE 0x242 #define CSR_VSTVAL 0x243 #define CSR_VSIP 0x244 +#define CSR_VSTIMECMP 0x24d +#define CSR_VSTIMECMPH 0x25d #define CSR_VSATP 0x280 =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ diff --git a/xen/arch/riscv/include/asm/sbi.h b/xen/arch/riscv/include/asm/= sbi.h index ed7af200288f..1952868e963c 100644 --- a/xen/arch/riscv/include/asm/sbi.h +++ b/xen/arch/riscv/include/asm/sbi.h @@ -13,7 +13,6 @@ #define ASM__RISCV__SBI_H =20 #include -#include =20 /* SBI-defined implementation ID */ #define SBI_XEN_IMPID 7 @@ -139,23 +138,6 @@ int sbi_remote_hfence_gvma(const cpumask_t *cpu_mask, = vaddr_t start, int sbi_remote_hfence_gvma_vmid(const cpumask_t *cpu_mask, vaddr_t start, size_t size, unsigned long vmid); =20 -/* - * Programs the clock for next event at (or after) stime_value. stime_valu= e is - * in absolute time. This function must clear the pending timer interrupt = bit - * as well. - * - * If the supervisor wishes to clear the timer interrupt without schedulin= g the - * next timer event, it can either request a timer interrupt infinitely far - * into the future (i.e., (uint64_t)-1), or it can instead mask the timer - * interrupt by clearing sie.STIE CSR bit. - * - * The stime_value parameter represents absolute time measured in ticks. - * - * This SBI call returns 0 upon success or an implementation specific nega= tive - * error code. - */ -extern int (* __ro_after_init sbi_set_timer)(uint64_t stime_value); - /* * Initialize SBI library * diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm= /time.h index be3875b9984e..4d68900151a7 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #include =20 @@ -26,6 +27,8 @@ static inline cycles_t get_cycles(void) =20 void preinit_xen_time(void); =20 +extern int (* __ro_after_init set_xen_timer)(uint64_t deadline); + #endif /* ASM__RISCV__TIME_H */ =20 /* diff --git a/xen/arch/riscv/sbi.c b/xen/arch/riscv/sbi.c index b4a7ae6940c1..3576e26033a5 100644 --- a/xen/arch/riscv/sbi.c +++ b/xen/arch/riscv/sbi.c @@ -22,6 +22,7 @@ =20 #include #include +#include =20 static unsigned long __ro_after_init sbi_spec_version =3D SBI_SPEC_VERSION= _DEFAULT; =20 @@ -249,6 +250,21 @@ static int (* __ro_after_init sbi_rfence)(unsigned lon= g fid, unsigned long arg4, unsigned long arg5); =20 +/* + * Programs the clock for next event at (or after) stime_value. stime_valu= e is + * in absolute time. This function must clear the pending timer interrupt = bit + * as well. + * + * If the supervisor wishes to clear the timer interrupt without schedulin= g the + * next timer event, it can either request a timer interrupt infinitely far + * into the future (i.e., (uint64_t)-1), or it can instead mask the timer + * interrupt by clearing sie.STIE CSR bit. + * + * The stime_value parameter represents absolute time measured in ticks. + * + * This SBI call returns 0 upon success or an implementation specific nega= tive + * error code. + */ static int cf_check sbi_set_timer_v02(uint64_t stime_value) { struct sbiret ret; @@ -264,6 +280,10 @@ static int cf_check sbi_set_timer_v02(uint64_t stime_v= alue) return sbi_err_map_xen_errno(ret.error); } =20 +/* + * Legacy SBI v0.1 SET_TIMER; functionally equivalent to sbi_set_timer_v02 + * from Xen's perspective. + */ static int cf_check sbi_set_timer_v01(uint64_t stime_value) { struct sbiret ret; @@ -279,8 +299,6 @@ static int cf_check sbi_set_timer_v01(uint64_t stime_va= lue) return sbi_err_map_xen_errno(ret.error); } =20 -int (* __ro_after_init sbi_set_timer)(uint64_t stime_value) =3D sbi_set_ti= mer_v01; - int sbi_remote_sfence_vma(const cpumask_t *cpu_mask, vaddr_t start, size_t size) { @@ -360,10 +378,9 @@ int __init sbi_init(void) } =20 if ( sbi_probe_extension(SBI_EXT_TIME) > 0 ) - { - sbi_set_timer =3D sbi_set_timer_v02; - dprintk(XENLOG_INFO, "SBI v0.2 TIME extension detected\n"); - } + set_xen_timer =3D sbi_set_timer_v02; + else + set_xen_timer =3D sbi_set_timer_v01; } else panic("Ooops. SBI spec version 0.1 detected. Need to add support"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c index 698ab49d1292..8769709e5227 100644 --- a/xen/arch/riscv/time.c +++ b/xen/arch/riscv/time.c @@ -7,12 +7,21 @@ #include #include =20 +#include #include -#include =20 unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ uint64_t __ro_after_init boot_clock_cycles; =20 +static int cf_check sstc_set_xen_timer(uint64_t deadline) +{ + csr_write64(CSR_STIMECMP, deadline); + + return 0; +} + +int (* __ro_after_init set_xen_timer)(uint64_t deadline); + s_time_t get_s_time(void) { uint64_t ticks =3D get_cycles() - boot_clock_cycles; @@ -61,20 +70,7 @@ int reprogram_timer(s_time_t timeout) if ( deadline <=3D now ) return 0; =20 - /* - * TODO: When the SSTC extension is supported, it would be preferable = to - * use the supervisor timer registers directly here for better - * performance, since an SBI call and mode switch would no longer - * be required. - * - * This would also reduce reliance on a specific SBI implementat= ion. - * For example, it is not ideal to panic() if sbi_set_timer() re= turns - * a non-zero value. Currently it can return 0 or -ENOSUPP, and - * without SSTC we still need an implementation because only the - * M-mode timer is available, and it can only be programmed in - * M-mode. - */ - if ( (rc =3D sbi_set_timer(deadline)) ) + if ( (rc =3D set_xen_timer(deadline)) ) panic("%s: timer wasn't set because: %d\n", __func__, rc); =20 /* Enable timer interrupt */ @@ -91,4 +87,20 @@ void __init preinit_xen_time(void) panic("%s: ACPI isn't supported\n", __func__); =20 boot_clock_cycles =3D get_cycles(); + + /* set_xen_timer must have been set by sbi_init() already */ + ASSERT(set_xen_timer); + + if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_sstc) ) + { + set_xen_timer =3D sstc_set_xen_timer; + + /* + * A VS-timer interrupt becomes pending whenever the value of + * (time + htimedelta) is greater than or equal to vstimecmp CSR. + * Thereby to avoid spurious VS-timer irqs set vstimecmp CSR to + * ULONG_MAX. + */ + csr_write64(CSR_STIMECMP, ULONG_MAX); + } } diff --git a/xen/arch/riscv/vtimer.c b/xen/arch/riscv/vtimer.c index afd8a53a7387..d5a8dfcb2edb 100644 --- a/xen/arch/riscv/vtimer.c +++ b/xen/arch/riscv/vtimer.c @@ -4,6 +4,7 @@ #include #include =20 +#include #include =20 static void vtimer_expired(void *data) --=20 2.53.0