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[109.243.67.101]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485359bf807sm119619845e9.2.2026.03.10.10.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 10:09:13 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: dd807af5-1ca3-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773162554; x=1773767354; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y2l9GSTVdHf37ct2dJEvx0io7ScAIs5lEweSLfZGouo=; b=iIuPKO4b+qUhMQwTITvT3pvAvG6IJR50piZmXbxla5v5v6ZUcQx+0PAERuup0F1qlo g+FE2eOCLD8mjE0gXjHmdmxpAgiwWuZdOaWlO3IefvaqRIQtkhnHWmOiYGIkKNtXYLew c2TrlXp0JEhUZGoOBTJoT1jiqDQ4t2nLhvhT/16OSaxAflo58U8L5NMDJPbRgwvkkOrw fWej3C0xAQ5hvmvPh4hOgQ64RBzdavG4B9uU4sVCEA6lkpInrhHeTedkBC8wQvIQ5Ofa iCbzDRUgAoHILRIEB6kt9FMU1QXS3xOrp1Bu1cVxBuM5K6SlH3YZaNZXNmzLEps2tA10 RDMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773162554; x=1773767354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=y2l9GSTVdHf37ct2dJEvx0io7ScAIs5lEweSLfZGouo=; b=MusXI6CI1bXU+TVEazp83y9f5vrpZoeWQygPJLTYc8pkPDwi0kXNrN6j/DJBMvFdkR TfyBMUtgZT+42ctFQ7YzI/yO6Pl3O8JM99nXBq+W92s3loFIDBeYZzEfgZqIlz3PPxy+ w79mR6Oy4biyVBq/xCutI9F4GcMnd0zHru5fKLyuZB7OBM3BUoaK4rZHI5u40VYAzqJw SFR585z/HuBYnUiM3sWrnsMIc/dNVh9txRv7v19/A6GuY+ATM1cDC+5CeF4EcihlB7R3 3SZjUzSZ2LBCKmnKzq5MEJHcWtq852JTkTTQCIEvwhe/KwIu0fN7HMHf3tDIp6ny1DVS e8ew== X-Gm-Message-State: AOJu0YyN9sxMqexhh67wh+yTR/Rvo6e2m3q+QyI5dufTLdKT+48mvyfE Y8eXMJN3hqQYwYwpWsaGAmz33zKA7++ouWIAss0mid7kiihgBM0Ny3wQ3xBJcKMt X-Gm-Gg: ATEYQzzbuSk7Qv9YN0xCaZhJA+xrSIbwJQSnzkdGONzi20jpYAa5jeJ+qlhKXz7dIGX Hju9abVBhIt/V0A88CeIKgGv+uuP5OXVAwMO37rxr6JcgLyCuLn9r2UpCTV7Q9Ei5QQ0j/Ve6G/ rPSNoTWaHaG5/oAp1zjMslUuoM5PsHsybKG0YvtgQWe0PzVTr1BrRfVmsn9YP+fJOZcRnAzEbn6 BeuwwNAmbOhBJfdptYXPhmSObybJO2HBbOyd6zM2A6H11omDItrO34DIJMkBNi1qdgwy1aSfXaG CUmVfRvLB5SuKDHBX6a8W23LoKSu40yI0HgOv0wOJr6h/T9a241pz19HwngaC7I7qkBWkjVZwGC xoXqB+OH41NMjRPPx+560g4IrgMlBssqezdvb5JCk38T5oD+qGu6o1rTc/vhtopr4xrrFC0JFRA XZ849b55hPNphvrboaCMIU1PzBysaAr0Rf2rL0lLGUyl3kv4sXeGMcn1rrTBAvguicJg== X-Received: by 2002:a05:600c:a12:b0:483:badb:618f with SMTP id 5b1f17b1804b1-48526966b07mr244053275e9.25.1773162553878; Tue, 10 Mar 2026 10:09:13 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Romain Caritey , Oleksii Kurochko , Alistair Francis , Connor Davis , Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini Subject: [PATCH v1 04/27] xen/riscv: rework G-stage mode handling Date: Tue, 10 Mar 2026 18:08:37 +0100 Message-ID: <2c8f1ea25b8d3ec78b00510fbe604a87e759e194.1773157782.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773162584491158500 Content-Type: text/plain; charset="utf-8" Rework G-stage mode handling to make the selected mode descriptor reusable outside of p2m initialization. As max_gstage_mode is going to be reused by code that creates CPU nodes for guest domains, not only max_gstage_mode->mode but also max_gstage_mode->name is required. To support this, make max_gstage_mode a global pointer to one = of the entries in a global modes[] array, and remove get_max_supported_mode(). Update struct p2m_domain to store a pointer to a mode descriptor instead of embedding the structure directly. Refactor the modes[] array so that mode->name contains only the MMU scheme name (without the "x4" suffix), as this value is reused when filling the maximum MMU type passed to the guest. According to DT bindings [1], the MMU type must not include the "x4" suffix. Use "none" for the Bare mode to match the DT binding requirements. Adjust modes[]->paging_levels to represent the maximum paging level rather than the total number of levels. This ensures that P2M_ROOT_LEVEL() and its users behave correctly without relying on hardcoded p2m mode values. Finally, drop __initconst from the modes[] declaration, as the array is referenced via p2m->mode and max_gstage_mode beyond the init stage. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /Documentation/devicetree/bindings/riscv/cpus.yaml?h=3Dv6.19-rc3#n82 Signed-off-by: Oleksii Kurochko --- xen/arch/riscv/include/asm/p2m.h | 7 ++-- xen/arch/riscv/p2m.c | 60 +++++++++++++------------------- xen/arch/riscv/vmid.c | 2 +- 3 files changed, 30 insertions(+), 39 deletions(-) diff --git a/xen/arch/riscv/include/asm/p2m.h b/xen/arch/riscv/include/asm/= p2m.h index c6d846b96fb4..4441c0400b83 100644 --- a/xen/arch/riscv/include/asm/p2m.h +++ b/xen/arch/riscv/include/asm/p2m.h @@ -13,7 +13,7 @@ =20 #define P2M_ROOT_ORDER (ilog2(GSTAGE_ROOT_PAGE_TABLE_SIZE) - PAGE_SHIFT) #define P2M_ROOT_PAGES BIT(P2M_ROOT_ORDER, U) -#define P2M_ROOT_LEVEL(p2m) ((p2m)->mode.paging_levels) +#define P2M_ROOT_LEVEL(p2m) ((p2m)->mode->paging_levels) =20 /* * According to the RISC-V spec: @@ -58,6 +58,8 @@ struct gstage_mode_desc { char name[8]; }; =20 +extern const struct gstage_mode_desc *max_gstage_mode; + /* Per-p2m-table state */ struct p2m_domain { /* @@ -71,7 +73,7 @@ struct p2m_domain { /* The root of the p2m tree. May be concatenated */ struct page_info *root; =20 - struct gstage_mode_desc mode; + const struct gstage_mode_desc *mode; =20 /* Back pointer to domain */ struct domain *domain; @@ -218,7 +220,6 @@ static inline bool arch_acquire_resource_check(struct d= omain *d) } =20 void guest_mm_init(void); -unsigned char get_max_supported_mode(void); =20 int p2m_init(struct domain *d); =20 diff --git a/xen/arch/riscv/p2m.c b/xen/arch/riscv/p2m.c index 886e06196ba2..dce1eb205ec9 100644 --- a/xen/arch/riscv/p2m.c +++ b/xen/arch/riscv/p2m.c @@ -45,18 +45,32 @@ struct p2m_pte_ctx { unsigned int level; /* Paging level at which the PTE resides.= */ }; =20 -static struct gstage_mode_desc __ro_after_init max_gstage_mode =3D { - .mode =3D HGATP_MODE_OFF, - .paging_levels =3D 0, - .name =3D "Bare", -}; - /* * Set to the maximum configured support for IPA bits, so the number of IP= A bits can be * restricted by external entity (e.g. IOMMU). */ unsigned int __read_mostly p2m_ipa_bits =3D PADDR_BITS; =20 +static const struct gstage_mode_desc modes[] =3D { + /* + * Based on the RISC-V spec: + * Bare mode is always supported, regardless of SXLEN. + * When SXLEN=3D32, the only other valid setting for MODE is Sv32. + * When SXLEN=3D64, three paged virtual-memory schemes are defined: + * Sv39, Sv48, and Sv57. + */ + [0] =3D { HGATP_MODE_OFF, 0, "none" }, +#ifdef CONFIG_RISCV_32 + [1] =3D { HGATP_MODE_SV32X4, 1, "sv32" } +#else + [2] =3D { HGATP_MODE_SV39X4, 2, "sv39" }, + [3] =3D { HGATP_MODE_SV48X4, 3, "sv48" }, + [4] =3D { HGATP_MODE_SV57X4, 4, "sv57" }, +#endif +}; + +const struct gstage_mode_desc * __ro_after_init max_gstage_mode =3D &modes= [0]; + static void p2m_free_page(struct p2m_domain *p2m, struct page_info *pg); =20 static inline void p2m_free_metadata_page(struct p2m_domain *p2m, @@ -69,11 +83,6 @@ static inline void p2m_free_metadata_page(struct p2m_dom= ain *p2m, } } =20 -unsigned char get_max_supported_mode(void) -{ - return max_gstage_mode.mode; -} - /* * If anything is changed here, it may also require updates to * p2m_{get,set}_type(). @@ -154,23 +163,6 @@ static pte_t *p2m_get_root_pointer(struct p2m_domain *= p2m, gfn_t gfn) =20 static void __init gstage_mode_detect(void) { - static const struct gstage_mode_desc modes[] __initconst =3D { - /* - * Based on the RISC-V spec: - * Bare mode is always supported, regardless of SXLEN. - * When SXLEN=3D32, the only other valid setting for MODE is Sv3= 2. - * When SXLEN=3D64, three paged virtual-memory schemes are defin= ed: - * Sv39, Sv48, and Sv57. - */ -#ifdef CONFIG_RISCV_32 - { HGATP_MODE_SV32X4, 2, "Sv32x4" } -#else - { HGATP_MODE_SV39X4, 3, "Sv39x4" }, - { HGATP_MODE_SV48X4, 4, "Sv48x4" }, - { HGATP_MODE_SV57X4, 5, "Sv57x4" }, -#endif - }; - for ( unsigned int mode_idx =3D ARRAY_SIZE(modes); mode_idx-- > 0; ) { unsigned long mode =3D modes[mode_idx].mode; @@ -179,16 +171,16 @@ static void __init gstage_mode_detect(void) =20 if ( MASK_EXTR(csr_read(CSR_HGATP), HGATP_MODE_MASK) =3D=3D mode ) { - max_gstage_mode =3D modes[mode_idx]; + max_gstage_mode =3D &modes[mode_idx]; =20 break; } } =20 - if ( max_gstage_mode.mode =3D=3D HGATP_MODE_OFF ) + if ( max_gstage_mode->mode =3D=3D HGATP_MODE_OFF ) panic("Xen expects that G-stage won't be Bare mode\n"); =20 - printk("Max supported G-stage mode is %s\n", max_gstage_mode.name); + printk("Max supported G-stage mode is %sx4\n", max_gstage_mode->name); =20 csr_write(CSR_HGATP, 0); =20 @@ -289,7 +281,7 @@ static void clear_and_clean_page(struct page_info *page= , bool clean_dcache) unsigned long construct_hgatp(const struct p2m_domain *p2m, uint16_t vmid) { return MASK_INSR(mfn_x(page_to_mfn(p2m->root)), HGATP_PPN_MASK) | - MASK_INSR(p2m->mode.mode, HGATP_MODE_MASK) | + MASK_INSR(p2m->mode->mode, HGATP_MODE_MASK) | MASK_INSR(vmid, HGATP_VMID_MASK); } =20 @@ -369,9 +361,7 @@ int p2m_init(struct domain *d) #endif =20 /* TODO: don't hardcode used for a domain g-stage mode. */ - p2m->mode.mode =3D HGATP_MODE_SV39X4; - p2m->mode.paging_levels =3D 2; - safe_strcpy(p2m->mode.name, "Sv39x4"); + p2m->mode =3D &modes[2]; =20 return 0; } diff --git a/xen/arch/riscv/vmid.c b/xen/arch/riscv/vmid.c index 8fbcd500f24d..11c7e9d6d6c8 100644 --- a/xen/arch/riscv/vmid.c +++ b/xen/arch/riscv/vmid.c @@ -52,7 +52,7 @@ static DEFINE_PER_CPU(struct vmid_data, vmid_data); static unsigned int vmidlen_detect(void) { unsigned int vmid_bits; - unsigned char gstage_mode =3D get_max_supported_mode(); + unsigned char gstage_mode =3D max_gstage_mode->mode; =20 /* * According to the RISC-V Privileged Architecture Spec: --=20 2.53.0