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Wed, 25 Oct 2023 12:30:15 -0700 (PDT) From: =?UTF-8?q?Edwin=20T=C3=B6r=C3=B6k?= To: xen-devel@lists.xenproject.org Cc: =?UTF-8?q?Edwin=20T=C3=B6r=C3=B6k?= , Jan Beulich , Andrew Cooper , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Wei Liu Subject: [RFC PATCH 21/22] x86/AMD: fix CPUID for PerfCtr{4,5} Date: Wed, 25 Oct 2023 20:29:51 +0100 Message-Id: <29b4fbb1045bb7cb49facfe2bc3e470fd74234bf.1698261255.git.edwin.torok@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @cloud.com) X-ZM-MESSAGEID: 1698262257370100007 From: Edwin T=C3=B6r=C3=B6k These are available, but were hidden by CPUID previously. There are IR (all guests), NB and L2I (dom0 only) performance counters too that need to be implemented, add placeholder entries for them. Signed-off-by: Edwin T=C3=B6r=C3=B6k --- xen/arch/x86/cpu-policy.c | 14 +++++++++++--- xen/arch/x86/hvm/svm/svm.c | 1 + xen/arch/x86/pv/emul-priv-op.c | 1 + xen/include/public/arch-x86/cpufeatureset.h | 4 ++++ 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index e38b648f7d..4242a21e1d 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -340,9 +340,16 @@ static void recalculate_misc(struct cpu_policy *p) p->extd.raw[0x1e] =3D EMPTY_LEAF; /* TopoExt APIC ID/Core/Node */ p->extd.raw[0x1f] =3D EMPTY_LEAF; /* SEV */ p->extd.raw[0x20] =3D EMPTY_LEAF; /* Platform QoS */ - break; - } -} + + /* These are not implemented yet, hide from CPUID. + * When they become implemented, make them available when full vpm= u is on */ + p->extd.irperf =3D 0; + p->extd.perfctrextnb =3D 0; + p->extd.perfctrextl2i =3D 0; + + break; + } + } =20 void calculate_raw_cpu_policy(void) { @@ -391,6 +398,7 @@ static void __init calculate_host_policy(void) if ( vpmu_mode =3D=3D XENPMU_MODE_OFF ) { p->basic.raw[0xa] =3D EMPTY_LEAF; p->basic.pdcm =3D 0; + p->extd.perfctrextcore =3D 0; } =20 if ( p->extd.svm ) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 45f8e1ffd1..ecb6184f51 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -1905,6 +1905,7 @@ static int cf_check svm_msr_read_intercept( case MSR_AMD_FAM15H_EVNTSEL3: case MSR_AMD_FAM15H_EVNTSEL4: case MSR_AMD_FAM15H_EVNTSEL5: + /* TODO: IRPerfCnt, L2I_* and NB_* support */ if ( vpmu_do_rdmsr(msr, msr_content) ) goto gpf; break; diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 105485bb1e..8d802b5df0 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -1156,6 +1156,7 @@ static int cf_check write_msr( if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) { vpmu_msr =3D true; + /* fall-through */ case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5: case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: if ( vpmu_msr || (boot_cpu_data.x86_vendor & diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/publ= ic/arch-x86/cpufeatureset.h index 0aa3251397..5faca0bf7a 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -166,7 +166,10 @@ XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands= MAC instructions */ XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leaf= s */ +XEN_CPUFEATURE(PERFCTREXTCORE, 3*32+23) /*A! Extended core performance eve= nt-select registers */ +XEN_CPUFEATURE(PERFCTREXTNB, 3*32+24) /* Extended Northbridge performan= ce counters */ XEN_CPUFEATURE(DBEXT, 3*32+26) /*A data breakpoint extension */ +XEN_CPUFEATURE(PERFCTREXTL2I, 3*32+28) /* Extended L2 cache performance = counters */ XEN_CPUFEATURE(MONITORX, 3*32+29) /* MONITOR extension (MONITORX/MW= AITX) */ =20 /* Intel-defined CPU features, CPUID level 0x0000000D:1.eax, word 4 */ @@ -238,6 +241,7 @@ XEN_CPUFEATURE(EFRO, 7*32+10) /* APERF/MPERF= Read Only interface */ =20 /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ +XEN_CPUFEATURE(IRPERF, 8*32+ 1) /* Instruction Retired Performance = Counter */ XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always sav= es/restores FPU Error pointers */ XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, us= ed by AMD) */ --=20 2.41.0