From nobody Fri Nov 22 18:34:00 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1715954131; cv=none; d=zohomail.com; s=zohoarc; b=fOHHWmJu0ns8am1VPQad4VrR8LLZ8PUfWXYQqPBj7MebQd5bQ/9MsU9UiMaYffPU6nCB9CFscg6cO13gty86cZZvCtP2duBsIgLjx6mHPyEcAMKFIc0Ku4fomaLe0nI4BzaOmvPiIGvOTKscYad63yVIxPC0j2UJPNxz5abhOQs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1715954131; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=54376BKXaMRj0bU8DqMJL73bnzloZBB1RI+aKenu2eI=; b=HOpdW+5ssHZNjBUsiXc/jUi1O/t3DOIO6DVwdn4evoxGcgXzXqZk7F5DmDP/E63VEzIWUiXHTHNZdqfeqZN2vXvuKyBeL1nk5+5Ugw0JWe51TTdw7NXRF0Ajj7OeDggOqqF3I/Qw1bHYX6fJse4JmHwxqVE09z6z4pBiVDQxL5Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 171595413133334.486632818109456; Fri, 17 May 2024 06:55:31 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.724180.1129368 (Exim 4.92) (envelope-from ) id 1s7y3E-0001zh-Kt; Fri, 17 May 2024 13:55:12 +0000 Received: by outflank-mailman (output) from mailman id 724180.1129368; Fri, 17 May 2024 13:55:12 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3E-0001yl-Dk; Fri, 17 May 2024 13:55:12 +0000 Received: by outflank-mailman (input) for mailman id 724180; Fri, 17 May 2024 13:55:11 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1s7y3D-0001cB-3M for xen-devel@lists.xenproject.org; Fri, 17 May 2024 13:55:11 +0000 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [2a00:1450:4864:20::132]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1341fefd-1455-11ef-909e-e314d9c70b13; Fri, 17 May 2024 15:55:10 +0200 (CEST) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-52389c1308dso767289e87.3 for ; Fri, 17 May 2024 06:55:10 -0700 (PDT) Received: from fedora.. ([94.75.70.14]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c81b4sm1117456466b.113.2024.05.17.06.55.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 May 2024 06:55:08 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1341fefd-1455-11ef-909e-e314d9c70b13 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1715954109; x=1716558909; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=54376BKXaMRj0bU8DqMJL73bnzloZBB1RI+aKenu2eI=; b=gdP/4CI5TOgI/sY/pNh+WFS4+XybeGcT1WuN6QrFkaQ4JFfbQuBsbhCeZertfIEhV3 69LA4PywRqRIGyU3Cn8h8mSC5tgYJEG9SE0BloJoGtNVre7+LkqrJBAzLZoPonu8o9kZ XvDy96JtXu7gKGCLfSW65UblpDTvzUCGHCXj7+ou/D1z1Kb5IuUxR+0cNqWqxTPFOnhW XKIEI0Am24RD6pzMKN0c4kOFPB+TLyNpC4Sgpv/lvtaJnaP4+aAnuDgNfbyOYSB6ssJE 5vDs0wfBh+OIAoGtyzi9zP5IArq2qPwP8YYtRug4B+4KhPt0XfqMOS7x4xndQXQpR+8E 6TCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715954109; x=1716558909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=54376BKXaMRj0bU8DqMJL73bnzloZBB1RI+aKenu2eI=; b=Y/8Yp/59OpnUNW8pYT3D3QSE7fN7NNjLc9yXkUiZeYPeiCMari0sCEYLswm89steCB CBOfvGzPb8eTbAACd7Su08GrQ1D34WwMRUk/Ybreul9fCMGY4V4fJH0ov3lT62dpVrXi 1N2KDbeKWedse3cf99pJyPcNCcbFzr/7kSQCHhl95gddbVnBF9PL+MEHEHJKUaZvDiax hQIuAMAY845ftd2RBA1P2miGzMukWjRe1j1EnJG8mTRtT51VuOLPQLAnuIcunIy7evIo /n/SuiyZkdWUQRJaO8p57SlTJAoYJHkhHf2wTD3PDnTcsF3pDOId4J1G8cg6T17c3esK X4hw== X-Gm-Message-State: AOJu0YzBbBrhRZMSMP8OVOzAUBTZDM1cEy+MmcXAhfxL4tujukVvjlMj pR2YlZvy6FysaQ2xEB7wydPohuySEv8db5Xs27/apBlJ+JjgTiCmjg6RYTn7 X-Google-Smtp-Source: AGHT+IFTfWDRo3Tqa1PCPq1VbAzDPpfputSHVqpLpWWJ1xgDRzivP3CQXXKgxgm1Xq7uMSyW791i5A== X-Received: by 2002:a05:6512:2254:b0:523:294f:7fe6 with SMTP id 2adb3069b0e04-523294f806bmr11415779e87.44.1715954109015; Fri, 17 May 2024 06:55:09 -0700 (PDT) From: Oleksii Kurochko To: xen-devel@lists.xenproject.org Cc: Oleksii Kurochko , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Ross Lagerwall , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , George Dunlap , Jan Beulich , Shawn Anastasio Subject: [PATCH v10 02/14] xen: introduce generic non-atomic test_*bit() Date: Fri, 17 May 2024 15:54:51 +0200 Message-ID: <219df9d840a183fc55de02aff011c0972a68587c.1715952103.git.oleksii.kurochko@gmail.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1715954133475100003 Content-Type: text/plain; charset="utf-8" The following generic functions were introduced: * test_bit * generic__test_and_set_bit * generic__test_and_clear_bit * generic__test_and_change_bit These functions and macros can be useful for architectures that don't have corresponding arch-specific instructions. Also, the patch introduces the following generics which are used by the functions mentioned above: * BITOP_BITS_PER_WORD * BITOP_MASK * BITOP_WORD * BITOP_TYPE The following approach was chosen for generic*() and arch*() bit operation functions: If the bit operation function that is going to be generic starts with the prefix "__", then the corresponding generic/arch function will also contain the "__" prefix. For example: * test_bit() will be defined using arch_test_bit() and generic_test_bit(). * __test_and_set_bit() will be defined using arch__test_and_set_bit() and generic__test_and_set_bit(). Signed-off-by: Oleksii Kurochko Reviewed-by: Jan Beulich --- The context ("* Find First Set bit. Bits are labelled from 1." in xen/b= itops.h ) suggests there's a dependency on an uncommitted patch. It happens becuas= e the current patch series is based on Andrew's patch series ( https://lore.kernel.org/xen-d= evel/20240313172716.2325427-1-andrew.cooper3@citrix.com/T/#t ), but if everything is okay with the current one patch it can be merged wi= thout Andrew's patch series being merged. --- Changes in V10: - update the commit message. ( re-order paragraphs and add explanation usa= ge of prefix "__" in bit operation function names ) - add parentheses around the whole expression of bitop_bad_size() macros. - move macros bitop_bad_size() above asm/bitops.h as it is not arch-specif= ic anymore and there is no need for overriding it. - drop macros check_bitop_size() and use "if ( bitop_bad_size(addr) ) __bi= top_bad_size();" implictly where it is needed. - in use 'int' as a first parameter for __test_and_*(), gen= eric__test_and_*() to be consistent with how the mentioned functions were declared in the origina= l per-arch functions. - add 'const' to p variable in generic_test_bit(). - move definition of BITOP_BITS_PER_WORD and bitop_uint_t to xen/bitops.h = as we don't allow for arch overrides these definitions anymore.=20 --- Changes in V9: - move up xen/bitops.h in ppc/asm/page.h. - update defintion of arch_check_bitop_size. And drop correspondent macros from x86/asm/bitops.h - drop parentheses in generic__test_and_set_bit() for definition of local variable p. - fix indentation inside #ifndef BITOP_TYPE...#endif - update the commit message. --- Changes in V8: - drop __pure for function which uses volatile. - drop unnessary () in generic__test_and_change_bit() for addr casting. - update prototype of generic_test_bit() and test_bit(): now it returns b= ool instead of int. - update generic_test_bit() to use BITOP_MASK(). - Deal with fls{l} changes: it should be in the patch with introduced gen= eric fls{l}. - add a footer with explanation of dependency on an uncommitted patch aft= er Signed-off. - abstract bitop_size(). - move BITOP_TYPE define to . --- Changes in V7: - move everything to xen/bitops.h to follow the same approach for all gen= eric bit ops. - put together BITOP_BITS_PER_WORD and bitops_uint_t. - make BITOP_MASK more generic. - drop #ifdef ... #endif around BITOP_MASK, BITOP_WORD as they are generic enough. - drop "_" for generic__{test_and_set_bit,...}(). - drop " !=3D 0" for functions which return bool. - add volatile during the cast for generic__{...}(). - update the commit message. - update arch related code to follow the proposed generic approach. --- Changes in V6: - Nothing changed ( only rebase ) --- Changes in V5: - new patch --- xen/arch/arm/arm64/livepatch.c | 1 - xen/arch/arm/include/asm/bitops.h | 67 --------------- xen/arch/ppc/include/asm/bitops.h | 52 ------------ xen/arch/ppc/include/asm/page.h | 2 +- xen/arch/ppc/mm-radix.c | 2 +- xen/arch/x86/include/asm/bitops.h | 31 ++----- xen/include/xen/bitops.h | 131 ++++++++++++++++++++++++++++++ 7 files changed, 142 insertions(+), 144 deletions(-) diff --git a/xen/arch/arm/arm64/livepatch.c b/xen/arch/arm/arm64/livepatch.c index df2cebedde..4bc8ed9be5 100644 --- a/xen/arch/arm/arm64/livepatch.c +++ b/xen/arch/arm/arm64/livepatch.c @@ -10,7 +10,6 @@ #include #include =20 -#include #include #include #include diff --git a/xen/arch/arm/include/asm/bitops.h b/xen/arch/arm/include/asm/b= itops.h index 5104334e48..8e16335e76 100644 --- a/xen/arch/arm/include/asm/bitops.h +++ b/xen/arch/arm/include/asm/bitops.h @@ -22,9 +22,6 @@ #define __set_bit(n,p) set_bit(n,p) #define __clear_bit(n,p) clear_bit(n,p) =20 -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1UL << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) #define BITS_PER_BYTE 8 =20 #define ADDR (*(volatile int *) addr) @@ -76,70 +73,6 @@ bool test_and_change_bit_timeout(int nr, volatile void *= p, bool clear_mask16_timeout(uint16_t mask, volatile void *p, unsigned int max_try); =20 -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old =3D *p; - - *p =3D old | mask; - return (old & mask) !=3D 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old =3D *p; - - *p =3D old & ~mask; - return (old & mask) !=3D 0; -} - -/* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, - volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D - ((volatile unsigned int *)addr) + BITOP_WORD(nr); - unsigned int old =3D *p; - - *p =3D old ^ mask; - return (old & mask) !=3D 0; -} - -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p =3D (const volatile unsigned int *)= addr; - return 1UL & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD-1))); -} - /* * On ARMv5 and above those functions can be implemented around * the clz instruction for much better code efficiency. diff --git a/xen/arch/ppc/include/asm/bitops.h b/xen/arch/ppc/include/asm/b= itops.h index 20f7865358..049aa62b89 100644 --- a/xen/arch/ppc/include/asm/bitops.h +++ b/xen/arch/ppc/include/asm/bitops.h @@ -15,9 +15,6 @@ #define __set_bit(n, p) set_bit(n, p) #define __clear_bit(n, p) clear_bit(n, p) =20 -#define BITOP_BITS_PER_WORD 32 -#define BITOP_MASK(nr) (1U << ((nr) % BITOP_BITS_PER_WORD)) -#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) #define BITS_PER_BYTE 8 =20 /* PPC bit number conversion */ @@ -69,17 +66,6 @@ static inline void clear_bit(int nr, volatile void *addr) clear_bits(BITOP_MASK(nr), (volatile unsigned int *)addr + BITOP_WORD(= nr)); } =20 -/** - * test_bit - Determine whether a bit is set - * @nr: bit number to test - * @addr: Address to start counting from - */ -static inline int test_bit(int nr, const volatile void *addr) -{ - const volatile unsigned int *p =3D addr; - return 1 & (p[BITOP_WORD(nr)] >> (nr & (BITOP_BITS_PER_WORD - 1))); -} - static inline unsigned int test_and_clear_bits( unsigned int mask, volatile unsigned int *p) @@ -133,44 +119,6 @@ static inline int test_and_set_bit(unsigned int nr, vo= latile void *addr) (volatile unsigned int *)addr + BITOP_WORD(nr)) !=3D 0; } =20 -/** - * __test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_set_bit(int nr, volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D (volatile unsigned int *)addr + BITOP_WOR= D(nr); - unsigned int old =3D *p; - - *p =3D old | mask; - return (old & mask) !=3D 0; -} - -/** - * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is non-atomic and can be reordered. - * If two examples of this operation race, one can appear to succeed - * but actually fail. You must protect multiple accesses with a lock. - */ -static inline int __test_and_clear_bit(int nr, volatile void *addr) -{ - unsigned int mask =3D BITOP_MASK(nr); - volatile unsigned int *p =3D (volatile unsigned int *)addr + BITOP_WOR= D(nr); - unsigned int old =3D *p; - - *p =3D old & ~mask; - return (old & mask) !=3D 0; -} - #define flsl(x) generic_flsl(x) #define fls(x) generic_fls(x) =20 diff --git a/xen/arch/ppc/include/asm/page.h b/xen/arch/ppc/include/asm/pag= e.h index 890e285051..6d4cd2611c 100644 --- a/xen/arch/ppc/include/asm/page.h +++ b/xen/arch/ppc/include/asm/page.h @@ -2,9 +2,9 @@ #ifndef _ASM_PPC_PAGE_H #define _ASM_PPC_PAGE_H =20 +#include #include =20 -#include #include =20 #define PDE_VALID PPC_BIT(0) diff --git a/xen/arch/ppc/mm-radix.c b/xen/arch/ppc/mm-radix.c index ab5a10695c..9055730997 100644 --- a/xen/arch/ppc/mm-radix.c +++ b/xen/arch/ppc/mm-radix.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include #include #include #include #include #include =20 -#include #include #include #include diff --git a/xen/arch/x86/include/asm/bitops.h b/xen/arch/x86/include/asm/b= itops.h index dd439b69a0..23f09fdb7a 100644 --- a/xen/arch/x86/include/asm/bitops.h +++ b/xen/arch/x86/include/asm/bitops.h @@ -19,9 +19,6 @@ #define ADDR (*(volatile int *) addr) #define CONST_ADDR (*(const volatile int *) addr) =20 -extern void __bitop_bad_size(void); -#define bitop_bad_size(addr) (sizeof(*(addr)) < 4) - /** * set_bit - Atomically set a bit in memory * @nr: the bit to set @@ -175,7 +172,7 @@ static inline int test_and_set_bit(int nr, volatile voi= d *addr) }) =20 /** - * __test_and_set_bit - Set a bit and return its old value + * arch__test_and_set_bit - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -183,7 +180,7 @@ static inline int test_and_set_bit(int nr, volatile voi= d *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_set_bit(int nr, void *addr) +static inline int arch__test_and_set_bit(int nr, volatile void *addr) { int oldbit; =20 @@ -194,10 +191,7 @@ static inline int __test_and_set_bit(int nr, void *add= r) =20 return oldbit; } -#define __test_and_set_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_set_bit(nr, addr); \ -}) +#define arch__test_and_set_bit arch__test_and_set_bit =20 /** * test_and_clear_bit - Clear a bit and return its old value @@ -224,7 +218,7 @@ static inline int test_and_clear_bit(int nr, volatile v= oid *addr) }) =20 /** - * __test_and_clear_bit - Clear a bit and return its old value + * arch__test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to set * @addr: Address to count from * @@ -232,7 +226,7 @@ static inline int test_and_clear_bit(int nr, volatile v= oid *addr) * If two examples of this operation race, one can appear to succeed * but actually fail. You must protect multiple accesses with a lock. */ -static inline int __test_and_clear_bit(int nr, void *addr) +static inline int arch__test_and_clear_bit(int nr, volatile void *addr) { int oldbit; =20 @@ -243,13 +237,10 @@ static inline int __test_and_clear_bit(int nr, void *= addr) =20 return oldbit; } -#define __test_and_clear_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_clear_bit(nr, addr); \ -}) +#define arch__test_and_clear_bit arch__test_and_clear_bit =20 /* WARNING: non atomic and it can be reordered! */ -static inline int __test_and_change_bit(int nr, void *addr) +static inline int arch__test_and_change_bit(int nr, volatile void *addr) { int oldbit; =20 @@ -260,10 +251,7 @@ static inline int __test_and_change_bit(int nr, void *= addr) =20 return oldbit; } -#define __test_and_change_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ - __test_and_change_bit(nr, addr); \ -}) +#define arch__test_and_change_bit arch__test_and_change_bit =20 /** * test_and_change_bit - Change a bit and return its new value @@ -307,8 +295,7 @@ static inline int variable_test_bit(int nr, const volat= ile void *addr) return oldbit; } =20 -#define test_bit(nr, addr) ({ \ - if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ +#define arch_test_bit(nr, addr) ({ \ __builtin_constant_p(nr) ? \ constant_test_bit(nr, addr) : \ variable_test_bit(nr, addr); \ diff --git a/xen/include/xen/bitops.h b/xen/include/xen/bitops.h index f14ad0d33a..6eeeff0117 100644 --- a/xen/include/xen/bitops.h +++ b/xen/include/xen/bitops.h @@ -65,10 +65,141 @@ static inline int generic_flsl(unsigned long x) * scope */ =20 +#define BITOP_BITS_PER_WORD 32 +typedef uint32_t bitop_uint_t; + +#define BITOP_MASK(nr) ((bitop_uint_t)1 << ((nr) % BITOP_BITS_PER_WORD)) + +#define BITOP_WORD(nr) ((nr) / BITOP_BITS_PER_WORD) + +extern void __bitop_bad_size(void); + +#define bitop_bad_size(addr) (sizeof(*(addr)) < sizeof(bitop_uint_t)) + /* --------------------- Please tidy above here --------------------- */ =20 #include =20 +/** + * generic__test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_set_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask =3D BITOP_MASK(nr); + volatile bitop_uint_t *p =3D (volatile bitop_uint_t *)addr + BITOP_WOR= D(nr); + bitop_uint_t old =3D *p; + + *p =3D old | mask; + return (old & mask); +} + +/** + * generic__test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static always_inline bool +generic__test_and_clear_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask =3D BITOP_MASK(nr); + volatile bitop_uint_t *p =3D (volatile bitop_uint_t *)addr + BITOP_WOR= D(nr); + bitop_uint_t old =3D *p; + + *p =3D old & ~mask; + return (old & mask); +} + +/* WARNING: non atomic and it can be reordered! */ +static always_inline bool +generic__test_and_change_bit(int nr, volatile void *addr) +{ + bitop_uint_t mask =3D BITOP_MASK(nr); + volatile bitop_uint_t *p =3D (volatile bitop_uint_t *)addr + BITOP_WOR= D(nr); + bitop_uint_t old =3D *p; + + *p =3D old ^ mask; + return (old & mask); +} +/** + * generic_test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static always_inline bool generic_test_bit(int nr, const volatile void *ad= dr) +{ + bitop_uint_t mask =3D BITOP_MASK(nr); + const volatile bitop_uint_t *p =3D + (const volatile bitop_uint_t *)addr + BITOP_WORD(n= r); + + return (*p & mask); +} + +static always_inline bool +__test_and_set_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_set_bit +#define arch__test_and_set_bit generic__test_and_set_bit +#endif + + return arch__test_and_set_bit(nr, addr); +} +#define __test_and_set_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_set_bit(nr, addr); \ +}) + +static always_inline bool +__test_and_clear_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_clear_bit +#define arch__test_and_clear_bit generic__test_and_clear_bit +#endif + + return arch__test_and_clear_bit(nr, addr); +} +#define __test_and_clear_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_clear_bit(nr, addr); \ +}) + +static always_inline bool +__test_and_change_bit(int nr, volatile void *addr) +{ +#ifndef arch__test_and_change_bit +#define arch__test_and_change_bit generic__test_and_change_bit +#endif + + return arch__test_and_change_bit(nr, addr); +} +#define __test_and_change_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + __test_and_change_bit(nr, addr); \ +}) + +static always_inline bool test_bit(int nr, const volatile void *addr) +{ +#ifndef arch_test_bit +#define arch_test_bit generic_test_bit +#endif + + return arch_test_bit(nr, addr); +} +#define test_bit(nr, addr) ({ \ + if ( bitop_bad_size(addr) ) __bitop_bad_size(); \ + test_bit(nr, addr); \ +}) + /* * Find First Set bit. Bits are labelled from 1. */ --=20 2.45.0