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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485885be1c1sm5501729f8f.32.2026.09.04.04.12.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 04:12:33 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788520354; x=1789125154; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=IAj5V/bmI918usNj6g2EqlOZB06ZEviH3X3JOCZBsg0=; b=X3nN+PPaimN6A+z7e+wvnsF+kpa4GdbmWawPypI4A9jDfc95SwzpsDShaZdLbrgs6A GGZllrRxWCfWgryRbKwOqiloIMcOPndz9K6UxM+UOPAjV8R5VUuPWx65Hc6nd4yCWMKl 7luTdMEtAPW63qqbi04aDGtcUihH8ghR02TL4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788520354; x=1789125154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=IAj5V/bmI918usNj6g2EqlOZB06ZEviH3X3JOCZBsg0=; b=I/riddpCBaYpDJETHfguTPLqp9OcTi7rXBRLQ/Czx9MwThCLnYEtuqjbIND4Lv9oFC k5GbrQdV/3O1s72Pi+jQmamWBFifiSpCJoP0x2ibg83l/itvFyZQp0odF6iE7XGs7RsE nEohQijtMhWlEkiYiAf7bDF+mU4ZNX7KvsyUwGnpuIVw0Eb22pysj5cLDhmztDsLhzA6 Vr1q3FH6X5Lec7w1G1Z+Ep/yIJ7u8Kzooqus7rCmbHEm+gBqqHhCx8rzpia61gBFJbJ7 J5KpTFwZRICXpGT6IwFcVV4/lVzhFh6Ok6wjEAUBDBWzZMHDglYCqHo4KGqmnmfBBaLR ZpKg== X-Gm-Message-State: AFuF++kgWpub0wCngpb1UoVwssXotul2nWoLS9BxxR0Jv5xfSWoByxoU nvvOD8QaqGR05Z8Nt/+s9TLvnA+fIWVozuUtx9jtCmA2ziyv8WyefEGmQ15BVfmSUHAEfa9NS/u adPAB9C0= X-Gm-Gg: AYBFou0oxxdYeDV+dArx5+9kZD2M3al5N/IdHB4BKuEe6d8wwLdpn0/RAuSluG79X43 Z63xGAs+bYhTB/g5V1gdlqjFa6YfkhbqPPwQKUY6iOlQvQKonQndBgtm2Ed+CYNahuy2nXvIBST HYC5HdR0GlFgnBrzJRCdaDiF3PiZUxQjwaCdJs+S2JpvmZCa2qLpGiG5hC4BTxpPG98gs6MAw4m WbnJafa6MhSB5RWrEIxIQRI4wcYJkOZPskFEoBscDtdHrm6gYe5Em0Qlv2kdIaDoifBIWvS9isj AOni7DSNsftGM+5yBPAmHY/8l1LL3ZHgeWrCBQ16DJKbUS8cDjtqVbFWQKpWAegOIzCOOM8g6qN XIRHGy/7XmCyycrtFe+hR6Dq2HqXqL0Xr2adJKvLNEnghlUMbDShoYZdMD4wIJSFsaZRNuzycsa CUJXgaol7DN5IegrG+3xt6z1U5+bnum8G41qT4Et4JOVhCuNpsjC5DNffn5fehzln/ueKns0v/W lbx7M06NKFk+eTojXjgIn02fEEB3HQFkvPktfZJVElCOj5PrA== X-Received: by 2002:a05:600c:154f:b0:49c:fc6e:8cb5 with SMTP id 5b1f17b1804b1-49cfc6e8ee3mr27356755e9.25.1788520353571; Fri, 04 Sep 2026 04:12:33 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Setje-Eilers , Bertrand Marquis , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Michal Orzel Subject: [PATCH v2 1/5] xen/arm: Fix evaluation of parameters for SMCCC calls Date: Fri, 4 Sep 2026 12:12:24 +0100 Message-Id: <20260904111228.3022634-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260904111228.3022634-1-andrew.cooper3@citrix.com> References: <20260904111228.3022634-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1788520354-4B4D7CFC-79B07C3E/0/0 X-purgate-type: clean X-purgate-size: 4639 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788520392323154100 Content-Type: text/plain; charset="utf-8" Contrary to what was claimed in commit 67bcf5eae709 ("xen/arm: Simplify type handling for SMCCC declarations"), there is an important reason to retain t= he intermediate variable. It is unsafe to have any logic between the assignme= nt of the register variabes and the asm() block they're used in. This logically reverts commit 67bcf5eae709 ("xen/arm: Simplify type handling for SMCCC declarations") while retaining the conversions from commit 7f15d5d13221 ("xen/treewide: More typeof() -> auto conversions"). Adjust __declare_arg_0() to match. It happens to be safe because it's the first register expression once all macros are expanded, but it really should be consistent with the others. Leave a comment explaining why they must be written like this. Fixes: 67bcf5eae709 ("xen/arm: Simplify type handling for SMCCC declaration= s") Reported-by: Jan Setje-Eilers Signed-off-by: Andrew Cooper Reviewed-by: Bertrand Marquis --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers --- xen/arch/arm/include/asm/smccc.h | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 62c6985e7315..53cdddb690b7 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -108,37 +108,52 @@ struct arm_smccc_res { #define __constraint_read_6 __constraint_read_5, "r" (arg6) #define __constraint_read_7 __constraint_read_6, "r" (arg7) =20 +/* + * Macro arguments MUST be evaluated before being assigned to a register + * variable. + * + * This is manual register scheduling for the asm() statement, and any oth= er + * logic to evaluate may clobber the already-scheduled registers. + */ #define __declare_arg_0(a0, res) \ + auto __a0 =3D (uint32_t)(a0); \ struct arm_smccc_res *___res =3D (res); \ - register unsigned long arg0 ASM_REG(0) =3D (uint32_t)(a0) + register unsigned long arg0 ASM_REG(0) =3D __a0 =20 #define __declare_arg_1(a0, a1, res) \ + auto __a1 =3D (a1); \ __declare_arg_0(a0, res); \ - register auto arg1 ASM_REG(1) =3D (a1) + register auto arg1 ASM_REG(1) =3D __a1 =20 #define __declare_arg_2(a0, a1, a2, res) \ + auto __a2 =3D (a2); \ __declare_arg_1(a0, a1, res); \ - register auto arg2 ASM_REG(2) =3D (a2) + register auto arg2 ASM_REG(2) =3D __a2 =20 #define __declare_arg_3(a0, a1, a2, a3, res) \ + auto __a3 =3D (a3); \ __declare_arg_2(a0, a1, a2, res); \ - register auto arg3 ASM_REG(3) =3D (a3) + register auto arg3 ASM_REG(3) =3D __a3 =20 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + auto __a4 =3D (a4); \ __declare_arg_3(a0, a1, a2, a3, res); \ - register auto arg4 ASM_REG(4) =3D (a4) + register auto arg4 ASM_REG(4) =3D __a4 =20 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + auto __a5 =3D (a5); \ __declare_arg_4(a0, a1, a2, a3, a4, res); \ - register auto arg5 ASM_REG(5) =3D (a5) + register auto arg5 ASM_REG(5) =3D __a5 =20 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + auto __a6 =3D (a6); \ __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ - register auto arg6 ASM_REG(6) =3D (a6) + register auto arg6 ASM_REG(6) =3D __a6 =20 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + auto __a7 =3D (a7); \ __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ - register auto arg7 ASM_REG(7) =3D (a7) + register auto arg7 ASM_REG(7) =3D __a7 =20 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) --=20 2.39.5 From nobody Thu Sep 24 20:23:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485885be1c1sm5501729f8f.32.2026.09.04.04.12.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 04:12:33 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788520354; x=1789125154; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Ppy5o97De8trlM8n4YR2jLYgSbac3XUfe4LKYxgPMgw=; b=KnFkU5zEsshsz0eFEDQ5VQx3BdvkrSQqudzhEQbMjapwrptxNkMdmVEiuQB+EXe4cS MNyYdnKtP4UsABLLIhMdU0Xtdw8R35GcJwN6oaWxt71cUu3x/7WbVcuvvm23mPWnkbTl ja0OcMLHk7LHXYjXYc9YIRRTJE9Y/34tqSDsE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788520354; x=1789125154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=Ppy5o97De8trlM8n4YR2jLYgSbac3XUfe4LKYxgPMgw=; b=bFT/Zpe1AOhW9kFMCabyrVHgIouqMg4E/B8zB4e72XEv784bUebay55Z1wSKX/oKJ5 dWEA62D4trpQa7rCO18Nu6ZpHgBJRcIjtwtD7GdYiDPyS2u9fXF+5SqD96yiZcD62b7U 32HVFvEPlqPOewdND/uais6jo3J2bfvHBaV8bxTzdMVVjQ0nq4TaDUMlLM6PXznGgt3k lYw3hUQs8DTl+wwtejwiAyUREfWVPZg5NCYHiHPRbbfjyB4vnxZ5CSHvKr3Ys3UAoGXB 1WWzwZZ6bH432g9xZBerS9sLLmPp4EAsXjFAu39AoT/nPbTx3F2OHDN7kvjVC2BVGixX UfGw== X-Gm-Message-State: AFuF++l2bOGlO9Kz/IjYP0LimuCvYHys5z5ECRmj2sVbFGET1b4kOqj4 N5MpDHWSOu+quyCybZE69ImDQeUQ9Bk29JY2IHjq1aozK8okCDq17zPUvfzgCjpwr7BrxbZ7kd9 Om90LDYs= X-Gm-Gg: AYBFou0R98gNdImlg5Cdi0HpaEWpvxPU75MsHwq9ZDO3cEDLvdPT2aDMpllCWtM60D+ 4Kl86SSRqwEkvz8g45byAfwM+lit5kuTnBhXpi2KzIWeRMdMcQO8E+hAFG4cwmcbCJHVK3Blw6y bgPLZOrvQ+/6uZ2KPNAd4UCwdcald8sC/mkQFf0zYCuHXchVyj13OlvUH/DQeVH6TBvuu3N75rU 3VZLUOnBmf7D6UuXZr8EV/N94cIuwnRXaL5/wOu/IHIfo0LrpbcFoCryQclPOUDVFh5WMgSGRkZ o8ADn3p/I4B8dySjbDzJhaF5QqN6xvQfQJ5iZ1RJ5W3UdD4iOQcF4KUIliRnpyO6qYDKOuYhG+x A+3B3qm+/DBjfATR0Br4Gl7CI5lH9ig/XLrVeP5lMQkSZ8g9fkreGJ0WfuFG75zVUBJbSmyus4N C7fp9/NolJUoIjg2+RP0vn7vBh8e4B4GUBimAwC8XMrd8HIIreUX+H04yWXc7IHbSr4yXIozuHx 4yIBN/Zh+VrV2Psm8zeiuZ0aW2ozB7x54QjP4Y= X-Received: by 2002:a05:6000:2084:b0:482:f0ee:1390 with SMTP id ffacd0b85a97d-48587289c5bmr10690519f8f.22.1788520354233; Fri, 04 Sep 2026 04:12:34 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Bertrand Marquis , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Michal Orzel , Jan Setje-Eilers Subject: [PATCH v2 2/5] xen/arm: Introduce arm_smccc_guest_smc() Date: Fri, 4 Sep 2026 12:12:25 +0100 Message-Id: <20260904111228.3022634-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260904111228.3022634-1-andrew.cooper3@citrix.com> References: <20260904111228.3022634-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1788520355-660A82AC-E334D494/0/0 X-purgate-type: clean X-purgate-size: 8348 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788520389461158500 Content-Type: text/plain; charset="utf-8" Both {get,set}_user_reg() are out-of-line functions, leading to awful code generation. Introduce arm_smccc_guest_smc() to operate directly on guest registers. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Bertrand Marquis --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers For arm64: add/remove: 0/0 grow/shrink: 2/4 up/down: 27/-864 (-837) Function old new delta symbols_addresses 35096 35120 +24 symbols_names 42958 42961 +3 imx8qm_smc 544 348 -196 scmi_handle_smc 372 152 -220 imx8m_smc 576 356 -220 zynqmp_eemi 864 636 -228 For arm32: add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-160 (-160) Function old new delta scmi_handle_smc 392 232 -160 --- xen/arch/arm/firmware/scmi-smc.c | 16 +----------- xen/arch/arm/include/asm/smccc.h | 29 +++++++++++++++++++++ xen/arch/arm/platforms/imx8m.c | 16 +----------- xen/arch/arm/platforms/imx8qm.c | 16 +----------- xen/arch/arm/platforms/xilinx-zynqmp-eemi.c | 17 ++---------- 5 files changed, 34 insertions(+), 60 deletions(-) diff --git a/xen/arch/arm/firmware/scmi-smc.c b/xen/arch/arm/firmware/scmi-= smc.c index 0835ddeeeccc..a0cc6c6192f8 100644 --- a/xen/arch/arm/firmware/scmi-smc.c +++ b/xen/arch/arm/firmware/scmi-smc.c @@ -50,7 +50,6 @@ static bool scmi_is_valid_smc_id(uint32_t fid) static bool scmi_handle_smc(struct cpu_user_regs *regs) { uint32_t fid =3D (uint32_t)get_user_reg(regs, 0); - struct arm_smccc_res res; =20 if ( !scmi_is_valid_smc_id(fid) ) return false; @@ -63,20 +62,7 @@ static bool scmi_handle_smc(struct cpu_user_regs *regs) } =20 /* For the moment, forward the SCMI Request to FW running at EL3 */ - arm_smccc_1_1_smc(fid, - get_user_reg(regs, 1), - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); + arm_smccc_guest_smc(regs); =20 return true; } diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 53cdddb690b7..832157f43734 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -202,6 +202,21 @@ struct arm_smccc_res { #ifdef CONFIG_ARM_32 #define arm_smccc_1_0_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) #define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) + +/* Make an SMCCC v1.1 compliant SMC call with guest register state. */ +static inline void arm_smccc_guest_smc(struct cpu_user_regs *regs) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_smc(regs->r0, regs->r1, regs->r2, regs->r3, + regs->r4, regs->r5, regs->r6, regs->r7, &res); + + regs->r0 =3D res.a0; + regs->r1 =3D res.a1; + regs->r2 =3D res.a2; + regs->r3 =3D res.a3; +} + #else =20 void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, @@ -251,6 +266,20 @@ void __arm_smccc_1_0_smc(register_t a0, register_t a1,= register_t a2, arm_smccc_1_0_smc(__VA_ARGS__); \ } while ( 0 ) =20 +/* Make an SMCCC v1.1 compliant SMC call with guest register state. */ +static inline void arm_smccc_guest_smc(struct cpu_user_regs *regs) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_smc(regs->x0, regs->x1, regs->x2, regs->x3, + regs->x4, regs->x5, regs->x6, regs->x7, &res); + + regs->x0 =3D res.a0; + regs->x1 =3D res.a1; + regs->x2 =3D res.a2; + regs->x3 =3D res.a3; +} + /* * struct arm_smccc_1_2_regs - Arguments for or Results from SMC call * @a0-a17 argument values from registers 0 to 17 diff --git a/xen/arch/arm/platforms/imx8m.c b/xen/arch/arm/platforms/imx8m.c index 669dd517e057..efb0ad20d6e8 100644 --- a/xen/arch/arm/platforms/imx8m.c +++ b/xen/arch/arm/platforms/imx8m.c @@ -50,7 +50,6 @@ static bool imx8m_smc(struct cpu_user_regs *regs) { uint32_t function_id =3D get_user_reg(regs, 0); uint32_t subfunction_id =3D get_user_reg(regs, 1); - struct arm_smccc_res res; =20 if ( !cpus_have_const_cap(ARM_SMCCC_1_1) ) { @@ -122,20 +121,7 @@ static bool imx8m_smc(struct cpu_user_regs *regs) return false; } =20 - arm_smccc_1_1_smc(function_id, - subfunction_id, - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); + arm_smccc_guest_smc(regs); =20 return true; } diff --git a/xen/arch/arm/platforms/imx8qm.c b/xen/arch/arm/platforms/imx8q= m.c index 3600a073e8ba..7249e14ab640 100644 --- a/xen/arch/arm/platforms/imx8qm.c +++ b/xen/arch/arm/platforms/imx8qm.c @@ -67,7 +67,6 @@ static bool imx8qm_smc(struct cpu_user_regs *regs) { uint32_t function_id =3D get_user_reg(regs, 0); uint32_t subfunction_id =3D get_user_reg(regs, 1); - struct arm_smccc_res res; =20 if ( !cpus_have_const_cap(ARM_SMCCC_1_1) ) { @@ -106,20 +105,7 @@ static bool imx8qm_smc(struct cpu_user_regs *regs) } =20 allow_call: - arm_smccc_1_1_smc(function_id, - subfunction_id, - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); + arm_smccc_guest_smc(regs); =20 return true; } diff --git a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c b/xen/arch/arm/pla= tforms/xilinx-zynqmp-eemi.c index 2053ed7ac5f6..326c8a1ba6e5 100644 --- a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c +++ b/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c @@ -51,7 +51,6 @@ static inline bool domain_has_reset_access(struct domain = *d, uint32_t rst) =20 bool zynqmp_eemi(struct cpu_user_regs *regs) { - struct arm_smccc_res res; uint32_t fid =3D get_user_reg(regs, 0); uint32_t nodeid =3D get_user_reg(regs, 1); unsigned int pm_fn =3D fid & 0xFFFF; @@ -187,20 +186,8 @@ bool zynqmp_eemi(struct cpu_user_regs *regs) * can forward the whole command to firmware without additional * parameters checks. */ - arm_smccc_1_1_smc(get_user_reg(regs, 0), - get_user_reg(regs, 1), - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); + arm_smccc_guest_smc(regs); + return true; =20 done: --=20 2.39.5 From nobody Thu Sep 24 20:23:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485885be1c1sm5501729f8f.32.2026.09.04.04.12.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 04:12:34 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788520356; x=1789125156; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=OKNHZdlEt0x1ge8w8zMMA0euhweC/5SXf88v2qkE/1s=; b=FFvZSbAx+ad8M+G4vQ+lQ0ZJW1yKISbGM+51Axr8M4q1mIdiSYlT3ftg/Un51Lim60 UPWekGrSrNBXCQ6bnSgt9e2vRb9REwAZ+FwUpMPpNXMWkycVNGOOT292hm4aUsxNvUwl NuzQzFXemW5F36TdHp9YK48he1PqlyfiBOruw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788520356; x=1789125156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=OKNHZdlEt0x1ge8w8zMMA0euhweC/5SXf88v2qkE/1s=; b=FkOujCbm9xuSyRekJMr3+ZEW9GFhd6zcRmPH2CK3mW9WOyrJyqb1Q8jzxuTV3c9gWO GfhRAj9HjabgE4TRpkU8ok/Ho7lOGTXzZtJzwjHZ0P5ckh2kQKhJU+0Z2WN1NPLgXz4R xAbdqQWGc/e8wqRbdS1uCK8LQxoKAg/eL86I7h2HNllO/6d3g6G/lAIDB+2b+RdeEyBB T1L/ddskY0LwZDGIn2Bfa3R8CcnS77V56JA9BUzZAd+oTP2r4jc0+ZyUmUp8n+XnoxF/ d42An+44OTpGuuEUscL2nAEvsCUOeE0QY0fiiNOvK6ogQue9vErJtkMVhF6h+jV4nXlp yjfw== X-Gm-Message-State: AFuF++nilzSre5ZcGoo89hiwCYseP4s7K5Hdc/9IPhmY0cenJHYanqWX Y6H3IlqFiyjkazgPIe4GBOutlOfXOgILTbWbJt3H5s1rniW27scZ8oNWFiTUHO0IPgQ7bAKkeOW DOjwkYKI= X-Gm-Gg: AYBFou1ywGctguzqn+d5XnpqbaW8EhaBRvG1N0VFLBy7cbFkjaXW6K4WSC/O7UoVxPY sptoxiNLyTfMXYZItf1qqfo1POClfw3KM8gM//j5d68ua1KR/9VS10YQRCp66C6gyqpfEqh8lxd lVryzaep86ZihAbPRI1fULqoxxncXqCWRQnaktvsQFozYJA/R25x+fNSR89/lk2vWBhgKyiy8Jh e87J8xhLxrmYJO0F6qBlvLgK/Prx4ectadBlOmdUaq71NeXT6wRhCJmynJmgfU/8jzNhucdIcrX 6G+649mlJyJeuxwRxWUtNmWrq6M5I3jKTn8cWPDR+mP5RkP0hOLlqfSsKBw9k2kGhlQTilNwFG8 nej9Jl5gdfyEWKi3ZHxkrntvJvvrv/GhOBUetfdDmTSbFziLb9lD5/OvOLn1zhcNeE10LSF5+7y mXeOc9klfiCRRpkvowJv6v0sR7t0u0oVeKEuQc87L41NS3eyIPEQBioJgmmUm3hkGFL9b01++0v nBWylhUqT1BSORyKwZmWOvZMVila0VK9qP+R6c= X-Received: by 2002:a05:6000:4796:b0:484:3312:f127 with SMTP id ffacd0b85a97d-4858709b371mr8520454f8f.27.1788520355821; Fri, 04 Sep 2026 04:12:35 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Bertrand Marquis , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Michal Orzel , Jan Setje-Eilers Subject: [PATCH v2 3/5] xen/arm: Clean up 32bit arm_smccc_1_1_smc() Date: Fri, 4 Sep 2026 12:12:26 +0100 Message-Id: <20260904111228.3022634-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260904111228.3022634-1-andrew.cooper3@citrix.com> References: <20260904111228.3022634-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1788520356-F30B02AC-56B4610A/0/0 X-purgate-type: clean X-purgate-size: 5507 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788520392296154100 Content-Type: text/plain; charset="utf-8" ... before making a related copy of it. * Drop __constraints() so the output parameters are visible in the same bl= ock as they're defined. Use PASTE() rather than opencoding it. * Adust the indentation of trailing \'s for consistency. * Drop the newline at the end of the instruction. * Indent the if condition correctly. ___res is always of type arm_smccc_res (declared in __declare_arg_0()), so drop the typeof(). * Drop arm_smccc_1_0_smc() as it has no users. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Bertrand Marquis --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers --- xen/arch/arm/include/asm/smccc.h | 45 ++++++++++++++++---------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 832157f43734..5fe54013ac83 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -56,6 +56,8 @@ =20 #ifndef __ASSEMBLER__ =20 +#include + extern uint32_t smccc_ver; =20 /* Check if this is fast call. */ @@ -115,24 +117,24 @@ struct arm_smccc_res { * This is manual register scheduling for the asm() statement, and any oth= er * logic to evaluate may clobber the already-scheduled registers. */ -#define __declare_arg_0(a0, res) \ - auto __a0 =3D (uint32_t)(a0); \ - struct arm_smccc_res *___res =3D (res); \ +#define __declare_arg_0(a0, res) \ + auto __a0 =3D (uint32_t)(a0); \ + struct arm_smccc_res *___res =3D (res); \ register unsigned long arg0 ASM_REG(0) =3D __a0 =20 -#define __declare_arg_1(a0, a1, res) \ - auto __a1 =3D (a1); \ - __declare_arg_0(a0, res); \ +#define __declare_arg_1(a0, a1, res) \ + auto __a1 =3D (a1); \ + __declare_arg_0(a0, res); \ register auto arg1 ASM_REG(1) =3D __a1 =20 -#define __declare_arg_2(a0, a1, a2, res) \ - auto __a2 =3D (a2); \ - __declare_arg_1(a0, a1, res); \ +#define __declare_arg_2(a0, a1, a2, res) \ + auto __a2 =3D (a2); \ + __declare_arg_1(a0, a1, res); \ register auto arg2 ASM_REG(2) =3D __a2 =20 -#define __declare_arg_3(a0, a1, a2, a3, res) \ - auto __a3 =3D (a3); \ - __declare_arg_2(a0, a1, a2, res); \ +#define __declare_arg_3(a0, a1, a2, a3, res) \ + auto __a3 =3D (a3); \ + __declare_arg_2(a0, a1, a2, res); \ register auto arg3 ASM_REG(3) =3D __a3 =20 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ @@ -158,12 +160,6 @@ struct arm_smccc_res { #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) =20 -#define ___constraints(count) \ - : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3) \ - : __constraint_read_ ## count \ - : "memory" -#define __constraints(count) ___constraints(count) - /* * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call * @@ -189,10 +185,14 @@ struct arm_smccc_res { register unsigned long r2 ASM_REG(2); \ register unsigned long r3 ASM_REG(3); \ __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ - asm volatile("smc #0\n" \ - __constraints(__count_args(__VA_ARGS__))); \ + asm volatile ( \ + "smc #0" \ + : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3) \ + : PASTE(__constraint_read_, \ + __count_args(__VA_ARGS__)) \ + : "memory" ); \ if ( ___res ) \ - *___res =3D (typeof(*___res)){r0, r1, r2, r3}; \ + *___res =3D (struct arm_smccc_res){ r0, r1, r2, r3 }; \ } while ( 0 ) =20 /* @@ -200,7 +200,6 @@ struct arm_smccc_res { * v1.1. */ #ifdef CONFIG_ARM_32 -#define arm_smccc_1_0_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) #define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) =20 /* Make an SMCCC v1.1 compliant SMC call with guest register state. */ @@ -217,7 +216,7 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) regs->r3 =3D res.a3; } =20 -#else +#else /* CONFIG_ARM_64 */ =20 void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, register_t a3, register_t a4, register_t a5, --=20 2.39.5 From nobody Thu Sep 24 20:23:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485885be1c1sm5501729f8f.32.2026.09.04.04.12.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 04:12:36 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788520357; x=1789125157; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=gQNZV3/Wwp2qSBWtwYPdoz/wcPd4hlfIxvJUtY/sSz4=; b=erjHWhRIjbMv3Np6Gy060tckZwPnDImNH/xbvlnuCMAUvYCMbMUmO99hSgwaxBHCxa dkUon0pvd/nfcX+ptOQyL+9gj8XUOTbIsDCGAIigyc1Z0r6sQYkGa94mJjEbtpvh2fPM fIgBzS703RP7zy5VJzzNTncfpDae0AQrMrv88= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788520357; x=1789125157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=gQNZV3/Wwp2qSBWtwYPdoz/wcPd4hlfIxvJUtY/sSz4=; b=EHfvuJQf8e53V9K8LUT7fsKG+C/U7jmpkXeyigoSkCHK4Ebk7LZqVcHznNw33wIPTm crtK7c2V8tZ/HYmoGS57low6JKYeBn6ZS0GaG0DePxRfEmzb5568WoB72OWnLCpzRVp2 +sL2+g8JqAqrbu65sJtAq0cohr86jT+TOcdDlvM+gflnMRuQtKjy28JqE/AFcNgtShii sNHyQFztAu2WtQvUbYUqhNNbxnVBUmaSDR1PTyS1x860B5Ynaza5rLMOpr4wqprlTZ83 zVo3GcB3T3BBbCDmpC4+hpPu8DMW/+Pg7pMZp4HsKrg0HyPt3lk6pgxnPFT7kyzxFem9 bbCQ== X-Gm-Message-State: AFuF++ldUJ4WR0mso2CgxdSDuUphUR67OgKCevX3Ag57e4/sKiuYcLpy ETNnmL5bSPYaeg6XDA3yU8GBdYo2TLuZ+Dwtd1fBGgkiJjtdrUNxfrN3ywfQqsKOGnatU9wWwT5 Q4W4Ac2g= X-Gm-Gg: AYBFou3dXkrp5QYRJWDk6YPbHJ4yMVTod0an82n65yNK0/hf47vXFMfrFqXb4OaOuvD JmmyrAVlZLil0lwKszegp7XnnYq/JYGK0CBJUv82L9Qulu24vmz4n+ADMTlotwv/w6Dk0x+Lh6Q DYHwHTgwlT9rN825EKtkBfLltlEX9oH3tcTAclRx0QAOuY7+tRUMR/0M3DYiY7heUCHKOxC8n/y lEa3sfsMB4nZNNah618flpV+VRHHJZsVcLb+1n33joAhnEVF3kg/hKtDqpFUPdW6cU9t3+dxK/7 BaT3/n9X0f3sYpwEEc7WyLNYC34t+aUs9ZS3fuZkpQGXmYlrnoCyovGAdrZ7lnt1io4fbNp7fja QUWmaYpgAOvsOJXM6T5ScqliF3DTrj4PwMvjOA5/nAaCYd2z2TiaHD2kUbTY+SjxMmF34nQZCCS GEP05zfRUGB4b7aKx/4xUc6lWGApTVWjOuu/HjxYtH51R1qUT0dljcoIKw73sxNrDAxhoM1Cq5y tj9OQOr96gpaRhIMIMEizF/Tko2VS9yBtQPOu8= X-Received: by 2002:a05:600c:190b:b0:49c:fc6c:be12 with SMTP id 5b1f17b1804b1-49cfc6cc0acmr22537745e9.24.1788520356605; Fri, 04 Sep 2026 04:12:36 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel , Jan Setje-Eilers Subject: [PATCH v2 4/5] xen/arm: Rewrite arm_smccc_smc() for arm64 Date: Fri, 4 Sep 2026 12:12:27 +0100 Message-Id: <20260904111228.3022634-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260904111228.3022634-1-andrew.cooper3@citrix.com> References: <20260904111228.3022634-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-33051d/1788520357-75EFF4E9-7DA99E5D/0/0 X-purgate-type: clean X-purgate-size: 9681 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788520391477154100 Content-Type: text/plain; charset="utf-8" SMCCC v1.0 says that x4 through x17 may be clobbered. SMCCC v1.1 says they are strictly preserved, and SMCCC v1.2 permits them to contain extra return values. Xen deals with this by having __arm_smccc_1_0_smc() as an out-of-line function, but this causes awful code generation in arm_smccc_smc(). cpus_have_const_cap() is opaque to the optimiser, so we end up with one bas= ic block doing the reasonably-ok arm_smccc_1_1_smc() code generation and a sec= ond basic block setting up all 8 input registers even when they're not needed, spilling or discarding x8 through x17, and calling an out-of-line function. Remove __arm_smccc_1_0_smc() entirely, and rewrite arm_smccc_smc() to decla= re x4 through x17 as clobbered. This fully inlines the SMC, is a single basic block which instructs the compiler to spill or discard the potentially clobbered registers, and only sets up the necessary number of arguments for the call. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Bertrand Marquis --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers v2: * s/PSCI/SMCCC/g * Rewrite the comment for the new arm_smccc_smc(). Bloat-o-meter reports: add/remove: 0/1 grow/shrink: 0/10 up/down: 0/-795 (-795) Function old new delta symbols_sorted_offsets 23832 23824 -8 symbols_names 42962 42943 -19 symbols_addresses 35128 35104 -24 __arm_smccc_1_0_smc 32 - -32 call_psci_cpu_off 144 76 -68 seattle_system_reset 92 16 -76 seattle_system_off 92 16 -76 call_psci_system_reset 112 32 -80 call_psci_system_off 112 32 -80 call_psci_cpu_on 252 124 -128 psci_init 628 424 -204 An alternative way to do this would be to have x8 thru x17 in the clobber l= ist rather than the output list which would reduce the source size, but this fo= rm is more amenable to having SMCCC v1.2 worked into it too. --- xen/arch/arm/arm64/smc.S | 16 ------ xen/arch/arm/include/asm/smccc.h | 92 ++++++++++++++++---------------- 2 files changed, 45 insertions(+), 63 deletions(-) diff --git a/xen/arch/arm/arm64/smc.S b/xen/arch/arm/arm64/smc.S index 68b05e8ddd12..65b4eabe4f87 100644 --- a/xen/arch/arm/arm64/smc.S +++ b/xen/arch/arm/arm64/smc.S @@ -13,22 +13,6 @@ * GNU General Public License for more details. */ =20 -/* - * void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, - * register_t a3, register_t a4, register_t a5, - * register_t a6, register_t a7, - * struct arm_smccc_res *res) - */ -FUNC(__arm_smccc_1_0_smc) - smc #0 - ldr x4, [sp] - cbz x4, 1f /* No need to store the result */ - stp x0, x1, [x4, #SMCCC_RES_a0] - stp x2, x3, [x4, #SMCCC_RES_a2] -1: - ret -END(__arm_smccc_1_0_smc) - /* * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, * struct arm_smccc_1_2_regs *res) diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 5fe54013ac83..4ed2a40ed0ac 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -16,9 +16,6 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ =20 -#include -#include - #define SMCCC_VERSION_MAJOR_SHIFT 16 #define SMCCC_VERSION_MINOR_MASK \ ((1U << SMCCC_VERSION_MAJOR_SHIFT) - 1) @@ -57,6 +54,9 @@ #ifndef __ASSEMBLER__ =20 #include +#include + +#include =20 extern uint32_t smccc_ver; =20 @@ -160,6 +160,8 @@ struct arm_smccc_res { #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) =20 +#ifdef CONFIG_ARM_32 + /* * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call * @@ -199,7 +201,6 @@ struct arm_smccc_res { * The calling convention for arm32 is the same for both SMCCC v1.0 and * v1.1. */ -#ifdef CONFIG_ARM_32 #define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) =20 /* Make an SMCCC v1.1 compliant SMC call with guest register state. */ @@ -218,53 +219,50 @@ static inline void arm_smccc_guest_smc(struct cpu_use= r_regs *regs) =20 #else /* CONFIG_ARM_64 */ =20 -void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, - register_t a3, register_t a4, register_t a5, - register_t a6, register_t a7, - struct arm_smccc_res *res); - -/* Macros to handle variadic parameter for SMCCC v1.0 helper */ -#define __arm_smccc_1_0_smc_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ - __arm_smccc_1_0_smc(a0, a1, a2, a3, a4, a5, a6, a7, res) - -#define __arm_smccc_1_0_smc_6(a0, a1, a2, a3, a4, a5, a6, res) \ - __arm_smccc_1_0_smc_7(a0, a1, a2, a3, a4, a5, a6, 0, res) - -#define __arm_smccc_1_0_smc_5(a0, a1, a2, a3, a4, a5, res) \ - __arm_smccc_1_0_smc_6(a0, a1, a2, a3, a4, a5, 0, res) - -#define __arm_smccc_1_0_smc_4(a0, a1, a2, a3, a4, res) \ - __arm_smccc_1_0_smc_5(a0, a1, a2, a3, a4, 0, res) - -#define __arm_smccc_1_0_smc_3(a0, a1, a2, a3, res) \ - __arm_smccc_1_0_smc_4(a0, a1, a2, a3, 0, res) - -#define __arm_smccc_1_0_smc_2(a0, a1, a2, res) \ - __arm_smccc_1_0_smc_3(a0, a1, a2, 0, res) - -#define __arm_smccc_1_0_smc_1(a0, a1, res) \ - __arm_smccc_1_0_smc_2(a0, a1, 0, res) - -#define __arm_smccc_1_0_smc_0(a0, res) \ - __arm_smccc_1_0_smc_1(a0, 0, res) - -#define ___arm_smccc_1_0_smc_count(count, ...) \ - __arm_smccc_1_0_smc_ ## count(__VA_ARGS__) - -#define __arm_smccc_1_0_smc_count(count, ...) \ - ___arm_smccc_1_0_smc_count(count, __VA_ARGS__) - -#define arm_smccc_1_0_smc(...) = \ - __arm_smccc_1_0_smc_count(__count_args(__VA_ARGS__), __VA_ARGS__) - +/* + * Make an SMC call compatible with both SMCCC v1.1 and v1.0. + * + * SMCCC v1.0 says that x4 through x17 are clobbered. SMCCC v1.1 says they + * are strictly preserved. Always mark x4 through x17 as clobbered. + */ #define arm_smccc_smc(...) \ do { \ - if ( cpus_have_const_cap(ARM_SMCCC_1_1) ) \ - arm_smccc_1_1_smc(__VA_ARGS__); \ - else \ - arm_smccc_1_0_smc(__VA_ARGS__); \ + register unsigned long r0 ASM_REG(0); \ + register unsigned long r1 ASM_REG(1); \ + register unsigned long r2 ASM_REG(2); \ + register unsigned long r3 ASM_REG(3); \ + /* Potentially clobbered in SMCCC v1.0 */ \ + register unsigned long c4 ASM_REG(4); \ + register unsigned long c5 ASM_REG(5); \ + register unsigned long c6 ASM_REG(6); \ + register unsigned long c7 ASM_REG(7); \ + register unsigned long c8 ASM_REG(8); \ + register unsigned long c9 ASM_REG(9); \ + register unsigned long c10 ASM_REG(10); \ + register unsigned long c11 ASM_REG(11); \ + register unsigned long c12 ASM_REG(12); \ + register unsigned long c13 ASM_REG(13); \ + register unsigned long c14 ASM_REG(14); \ + register unsigned long c15 ASM_REG(15); \ + register unsigned long c16 ASM_REG(16); \ + register unsigned long c17 ASM_REG(17); \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile ( \ + "smc #0" \ + : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3), \ + "=3Dr" (c4), "=3Dr" (c5), "=3Dr" (c6), "=3Dr" (c7), \ + "=3Dr" (c8), "=3Dr" (c9), "=3Dr" (c10), "=3Dr" (c11), \ + "=3Dr" (c12), "=3Dr" (c13), "=3Dr" (c14), "=3Dr" (c15), \ + "=3Dr" (c16), "=3Dr" (c17) \ + : PASTE(__constraint_read_, \ + __count_args(__VA_ARGS__)) \ + : "memory" ); \ + if ( ___res ) \ + *___res =3D (struct arm_smccc_res){ r0, r1, r2, r3 }; \ } while ( 0 ) =20 +#define arm_smccc_1_1_smc(...) arm_smccc_smc(__VA_ARGS__) + /* Make an SMCCC v1.1 compliant SMC call with guest register state. */ static inline void arm_smccc_guest_smc(struct cpu_user_regs *regs) { --=20 2.39.5 From nobody Thu Sep 24 20:23:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-485885be1c1sm5501729f8f.32.2026.09.04.04.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2026 04:12:36 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788520358; x=1789125158; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=04LSpSbvGT7DUfjS/h4Xju9eXZbdvvnkNdn9duYaZ48=; b=dOsg4CycfVClRRmAg419hlxRUS99DLzE6QWlaPcRQtu+OfkRcE+eIWEqHUwRSRURRS vy2i2xFBqWOIal4PPxNX0ev/Z7Hv7b85RIWvHzeH3SEAk3qQ3YH1uU1Pt0jvX4n2c0cG eXPXLrFtFmK7byyBFjiT4O2CAvEQLqR12JdPY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788520358; x=1789125158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=04LSpSbvGT7DUfjS/h4Xju9eXZbdvvnkNdn9duYaZ48=; b=VUXQV6coVWA54MinkS37SA0qJg6oYGMdpeMKFz/ObJFTIy2blMTJRtyD4hp1EVSPuG +bhlGlJdrGgXcx7HZp+/AdAEYKc6xtVtSz2KC78+G82JB52YXVzDTu4PBJ2ZSA0QiFHU 2NTLHtfbDpWpUaWxShpsR/hMXaX7bIYepPA6somlCOT5A09hNy0VT/m8NTZ/v7hqZdJ5 aSM2DOiSX9aobpiBw69P6iMrUQrEUS0scQE/I/20hnCwGGeWrW+x3viF7udPuYoK4mWG IIhdtP3I923mE9S3nUgRE/Fd49cNC5PTwjBqtQifa4lgI6glAm7m/JCD3RRHTRuLec1i dQ6Q== X-Gm-Message-State: AFuF++nJsNQBxm+ljsVghaSv1xtKvniHTs8ZIGs1ej50W8CGkreWaK4r 3GRdFSUB1099/Fr3BGZMZRUGALMKkrZDZfulTKQQc+A/vMdR25novlFqXz6EEPlfFaOsLg18nrN at8UBalk= X-Gm-Gg: AYBFou3K70uU6v8xSCFOmKLhLXpvkSO1EnyOwc08y2dP1CGf5E7BNnR5eBsDN/4JCBr soetPMJZ5SeuO1porTq4dVTv3dkAzii2qF5R42HWzfejJu+BBcivIt+VYQzKK5y4CG8WJIBbDVr qSlcQVVlrxT5d2aPjfWotyadYoo9MNgtJ9EXzjHW3bPFeAmdjl+SmEkb7HdHElP3jgs4+zCPkXf boGjAk8bmcsnfGeOwmZp7yFru/X8MRoRpXiYxI7XNnM4hIZvMJr2mt+nD4+k/S2sZwuJld9swfT feGX5YWI0bbDyze1bW/hmxoIZQPaiiubEYe3L7M/9Pyttmcx0DUsJIcnFlniXTxT7wZuelWyxT9 odbb6PXN1/kccdLIcTdK+Ihrq1dVndAPicJWY1JcZB0RWM+sp7R2/LxJbc60CUgloO1b/5b0yn9 JpJ6iMClyjbhmMVDPBdunfzYPBJ0NwOU1qnzsG8EjHcBh9c6cG4tlg9WnGF278sDsdui4ySC8Hf w9DFeYPXdCbNH+KWsy6X5eykv+i8fK2qjMN1As= X-Received: by 2002:a05:6000:4610:b0:485:8a47:5b86 with SMTP id ffacd0b85a97d-4858a475c82mr3512586f8f.35.1788520357493; Fri, 04 Sep 2026 04:12:37 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel , Jan Setje-Eilers Subject: [PATCH v2 5/5] xen/arm: Rewrite arm_smccc_*() to return by value Date: Fri, 4 Sep 2026 12:12:28 +0100 Message-Id: <20260904111228.3022634-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260904111228.3022634-1-andrew.cooper3@citrix.com> References: <20260904111228.3022634-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d25034/1788520358-00ACCA5B-99FB727D/0/0 X-purgate-type: clean X-purgate-size: 24069 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788520391471158501 Content-Type: text/plain; charset="utf-8" Use statement expressions to return struct arm_smccc_res which makes the co= de read a lot more normally, and avoids needing to pass in NULL in order to sk= ip return information. More importantly, it removes the local implementation of __count_args() whi= ch is off by two and deeply confusing to try and follow. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Bertrand Marquis --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers v2: * Transform extra call in optee_probe() Xen compiles identically before and after this change, for both arm32 and a= rm64. --- xen/arch/arm/cpuerrata.c | 18 +++---- xen/arch/arm/include/asm/smccc.h | 87 ++++++++++++++------------------ xen/arch/arm/platforms/exynos5.c | 2 +- xen/arch/arm/platforms/seattle.c | 4 +- xen/arch/arm/psci.c | 17 +++---- xen/arch/arm/tee/optee.c | 50 +++++++++--------- xen/arch/arm/traps.c | 4 +- 7 files changed, 86 insertions(+), 96 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 3a32183618dc..35ad98d29d14 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -179,8 +179,8 @@ static int enable_smccc_arch_workaround_1(void *data) if ( smccc_ver < SMCCC_VERSION(1, 1) ) goto warn; =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, - ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); + res =3D arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_1_FID); /* The return value is in the lower 32-bits. */ if ( (int)res.a0 < 0 ) goto warn; @@ -256,8 +256,8 @@ static int enable_spectre_bhb_workaround(void *data) if ( smccc_ver < SMCCC_VERSION(1, 1) ) goto warn; =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, - ARM_SMCCC_ARCH_WORKAROUND_3_FID, &res); + res =3D arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_3_FID); /* The return value is in the lower 32-bits. */ if ( (int)res.a0 < 0 ) { @@ -398,8 +398,8 @@ static bool has_ssbd_mitigation(const struct arm_cpu_ca= pabilities *entry) if ( smccc_ver < SMCCC_VERSION(1, 1) ) return false; =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, - ARM_SMCCC_ARCH_WORKAROUND_2_FID, &res); + res =3D arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_2_FID); =20 switch ( (int)res.a0 ) { @@ -429,7 +429,7 @@ static bool has_ssbd_mitigation(const struct arm_cpu_ca= pabilities *entry) case ARM_SSBD_FORCE_DISABLE: printk_once("%s disabled from command-line\n", entry->desc); =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0); required =3D false; break; =20 @@ -437,7 +437,7 @@ static bool has_ssbd_mitigation(const struct arm_cpu_ca= pabilities *entry) if ( required ) { this_cpu(ssbd_callback_required) =3D 1; - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1); } =20 break; @@ -445,7 +445,7 @@ static bool has_ssbd_mitigation(const struct arm_cpu_ca= pabilities *entry) case ARM_SSBD_FORCE_ENABLE: printk_once("%s forced from command-line\n", entry->desc); =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1); required =3D true; break; =20 diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 4ed2a40ed0ac..2d0f2db0b256 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -95,20 +95,14 @@ struct arm_smccc_res { unsigned long a3; }; =20 -/* SMCCC v1.1 implementation madness follows */ -#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x - -#define __count_args(...) \ - ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) - -#define __constraint_read_0 "r" (arg0) -#define __constraint_read_1 __constraint_read_0, "r" (arg1) -#define __constraint_read_2 __constraint_read_1, "r" (arg2) -#define __constraint_read_3 __constraint_read_2, "r" (arg3) -#define __constraint_read_4 __constraint_read_3, "r" (arg4) -#define __constraint_read_5 __constraint_read_4, "r" (arg5) -#define __constraint_read_6 __constraint_read_5, "r" (arg6) -#define __constraint_read_7 __constraint_read_6, "r" (arg7) +#define __constraint_read_1 "r" (arg0) +#define __constraint_read_2 __constraint_read_1, "r" (arg1) +#define __constraint_read_3 __constraint_read_2, "r" (arg2) +#define __constraint_read_4 __constraint_read_3, "r" (arg3) +#define __constraint_read_5 __constraint_read_4, "r" (arg4) +#define __constraint_read_6 __constraint_read_5, "r" (arg5) +#define __constraint_read_7 __constraint_read_6, "r" (arg6) +#define __constraint_read_8 __constraint_read_7, "r" (arg7) =20 /* * Macro arguments MUST be evaluated before being assigned to a register @@ -117,44 +111,43 @@ struct arm_smccc_res { * This is manual register scheduling for the asm() statement, and any oth= er * logic to evaluate may clobber the already-scheduled registers. */ -#define __declare_arg_0(a0, res) \ +#define __declare_arg_1(a0) \ auto __a0 =3D (uint32_t)(a0); \ - struct arm_smccc_res *___res =3D (res); \ register unsigned long arg0 ASM_REG(0) =3D __a0 =20 -#define __declare_arg_1(a0, a1, res) \ +#define __declare_arg_2(a0, a1) \ auto __a1 =3D (a1); \ - __declare_arg_0(a0, res); \ + __declare_arg_1(a0); \ register auto arg1 ASM_REG(1) =3D __a1 =20 -#define __declare_arg_2(a0, a1, a2, res) \ +#define __declare_arg_3(a0, a1, a2) \ auto __a2 =3D (a2); \ - __declare_arg_1(a0, a1, res); \ + __declare_arg_2(a0, a1); \ register auto arg2 ASM_REG(2) =3D __a2 =20 -#define __declare_arg_3(a0, a1, a2, a3, res) \ +#define __declare_arg_4(a0, a1, a2, a3) \ auto __a3 =3D (a3); \ - __declare_arg_2(a0, a1, a2, res); \ + __declare_arg_3(a0, a1, a2); \ register auto arg3 ASM_REG(3) =3D __a3 =20 -#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ +#define __declare_arg_5(a0, a1, a2, a3, a4) \ auto __a4 =3D (a4); \ - __declare_arg_3(a0, a1, a2, a3, res); \ + __declare_arg_4(a0, a1, a2, a3); \ register auto arg4 ASM_REG(4) =3D __a4 =20 -#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ +#define __declare_arg_6(a0, a1, a2, a3, a4, a5) \ auto __a5 =3D (a5); \ - __declare_arg_4(a0, a1, a2, a3, a4, res); \ + __declare_arg_5(a0, a1, a2, a3, a4); \ register auto arg5 ASM_REG(5) =3D __a5 =20 -#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ - auto __a6 =3D (a6); \ - __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6) \ + auto __a6 =3D (a6); \ + __declare_arg_6(a0, a1, a2, a3, a4, a5); \ register auto arg6 ASM_REG(6) =3D __a6 =20 -#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ - auto __a7 =3D (a7); \ - __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ +#define __declare_arg_8(a0, a1, a2, a3, a4, a5, a6, a7) \ + auto __a7 =3D (a7); \ + __declare_arg_7(a0, a1, a2, a3, a4, a5, a6); \ register auto arg7 ASM_REG(7) =3D __a7 =20 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) @@ -181,21 +174,20 @@ struct arm_smccc_res { * makes it stick. */ #define arm_smccc_1_1_smc(...) \ - do { \ + ({ \ register unsigned long r0 ASM_REG(0); \ register unsigned long r1 ASM_REG(1); \ register unsigned long r2 ASM_REG(2); \ register unsigned long r3 ASM_REG(3); \ - __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + __declare_args(count_args(__VA_ARGS__), __VA_ARGS__); \ asm volatile ( \ "smc #0" \ : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3) \ : PASTE(__constraint_read_, \ - __count_args(__VA_ARGS__)) \ + count_args(__VA_ARGS__)) \ : "memory" ); \ - if ( ___res ) \ - *___res =3D (struct arm_smccc_res){ r0, r1, r2, r3 }; \ - } while ( 0 ) + (struct arm_smccc_res){ r0, r1, r2, r3 }; \ + }) =20 /* * The calling convention for arm32 is the same for both SMCCC v1.0 and @@ -208,8 +200,8 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) { struct arm_smccc_res res; =20 - arm_smccc_1_1_smc(regs->r0, regs->r1, regs->r2, regs->r3, - regs->r4, regs->r5, regs->r6, regs->r7, &res); + res =3D arm_smccc_1_1_smc(regs->r0, regs->r1, regs->r2, regs->r3, + regs->r4, regs->r5, regs->r6, regs->r7); =20 regs->r0 =3D res.a0; regs->r1 =3D res.a1; @@ -226,7 +218,7 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) * are strictly preserved. Always mark x4 through x17 as clobbered. */ #define arm_smccc_smc(...) \ - do { \ + ({ \ register unsigned long r0 ASM_REG(0); \ register unsigned long r1 ASM_REG(1); \ register unsigned long r2 ASM_REG(2); \ @@ -246,7 +238,7 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) register unsigned long c15 ASM_REG(15); \ register unsigned long c16 ASM_REG(16); \ register unsigned long c17 ASM_REG(17); \ - __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + __declare_args(count_args(__VA_ARGS__), __VA_ARGS__); \ asm volatile ( \ "smc #0" \ : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3), \ @@ -255,11 +247,10 @@ static inline void arm_smccc_guest_smc(struct cpu_use= r_regs *regs) "=3Dr" (c12), "=3Dr" (c13), "=3Dr" (c14), "=3Dr" (c15), \ "=3Dr" (c16), "=3Dr" (c17) \ : PASTE(__constraint_read_, \ - __count_args(__VA_ARGS__)) \ + count_args(__VA_ARGS__)) \ : "memory" ); \ - if ( ___res ) \ - *___res =3D (struct arm_smccc_res){ r0, r1, r2, r3 }; \ - } while ( 0 ) + (struct arm_smccc_res){ r0, r1, r2, r3 }; \ + }) =20 #define arm_smccc_1_1_smc(...) arm_smccc_smc(__VA_ARGS__) =20 @@ -268,8 +259,8 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) { struct arm_smccc_res res; =20 - arm_smccc_1_1_smc(regs->x0, regs->x1, regs->x2, regs->x3, - regs->x4, regs->x5, regs->x6, regs->x7, &res); + res =3D arm_smccc_1_1_smc(regs->x0, regs->x1, regs->x2, regs->x3, + regs->x4, regs->x5, regs->x6, regs->x7); =20 regs->x0 =3D res.a0; regs->x1 =3D res.a1; diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exyn= os5.c index f7c09520675e..f08d50c1fe38 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -249,7 +249,7 @@ static int exynos5_cpu_up(int cpu) iounmap(power); =20 if ( secure_firmware ) - arm_smccc_smc(SMC_CMD_CPU1BOOT, cpu, NULL); + arm_smccc_smc(SMC_CMD_CPU1BOOT, cpu); =20 return cpu_up_send_sgi(cpu); } diff --git a/xen/arch/arm/platforms/seattle.c b/xen/arch/arm/platforms/seat= tle.c index 64cc1868c24b..dfa5cf4265c0 100644 --- a/xen/arch/arm/platforms/seattle.c +++ b/xen/arch/arm/platforms/seattle.c @@ -33,12 +33,12 @@ static const char * const seattle_dt_compat[] __initcon= st =3D */ static void seattle_system_reset(void) { - arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET, NULL); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET); } =20 static void seattle_system_off(void) { - arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF, NULL); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF); } =20 PLATFORM_START(seattle, "SEATTLE") diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index b6860a776031..634d0d7467cf 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -41,8 +41,8 @@ int call_psci_cpu_on(int cpu) { struct arm_smccc_res res; =20 - arm_smccc_smc(psci_cpu_on_nr, cpu_logical_map(cpu), __pa(init_secondar= y), - &res); + res =3D arm_smccc_smc(psci_cpu_on_nr, cpu_logical_map(cpu), + __pa(init_secondary)); =20 return PSCI_RET(res); } @@ -54,7 +54,7 @@ void call_psci_cpu_off(void) struct arm_smccc_res res; =20 /* If successfull the PSCI cpu_off call doesn't return */ - arm_smccc_smc(PSCI_0_2_FN32_CPU_OFF, &res); + res =3D arm_smccc_smc(PSCI_0_2_FN32_CPU_OFF); panic("PSCI cpu off failed for CPU%d err=3D%d\n", smp_processor_id= (), PSCI_RET(res)); } @@ -63,13 +63,13 @@ void call_psci_cpu_off(void) void call_psci_system_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF, NULL); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF); } =20 void call_psci_system_reset(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET, NULL); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET); } =20 static int __init psci_features(uint32_t psci_func_id) @@ -79,7 +79,7 @@ static int __init psci_features(uint32_t psci_func_id) if ( psci_ver < PSCI_VERSION(1, 0) ) return PSCI_NOT_SUPPORTED; =20 - arm_smccc_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, &res); + res =3D arm_smccc_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id); =20 return PSCI_RET(res); } @@ -116,9 +116,8 @@ static void __init psci_init_smccc(void) =20 if ( psci_features(ARM_SMCCC_VERSION_FID) !=3D PSCI_NOT_SUPPORTED ) { - struct arm_smccc_res res; + struct arm_smccc_res res =3D arm_smccc_smc(ARM_SMCCC_VERSION_FID); =20 - arm_smccc_smc(ARM_SMCCC_VERSION_FID, &res); if ( PSCI_RET(res) !=3D ARM_SMCCC_NOT_SUPPORTED ) smccc_ver =3D PSCI_RET(res); } @@ -191,7 +190,7 @@ static int __init psci_init_0_2(void) } } =20 - arm_smccc_smc(PSCI_0_2_FN32_PSCI_VERSION, &res); + res =3D arm_smccc_smc(PSCI_0_2_FN32_PSCI_VERSION); psci_ver =3D PSCI_RET(res); =20 /* For the moment, we only support PSCI 0.2 and PSCI 1.x */ diff --git a/xen/arch/arm/tee/optee.c b/xen/arch/arm/tee/optee.c index 3d2633237074..5e94daee0686 100644 --- a/xen/arch/arm/tee/optee.c +++ b/xen/arch/arm/tee/optee.c @@ -178,7 +178,7 @@ static bool optee_probe(void) return false; =20 /* Check UID */ - arm_smccc_smc(ARM_SMCCC_CALL_UID_FID(TRUSTED_OS_END), &resp); + resp =3D arm_smccc_smc(ARM_SMCCC_CALL_UID_FID(TRUSTED_OS_END)); =20 if ( (uint32_t)resp.a0 !=3D OPTEE_MSG_UID_0 || (uint32_t)resp.a1 !=3D OPTEE_MSG_UID_1 || @@ -187,7 +187,7 @@ static bool optee_probe(void) return false; =20 /* Read number of threads */ - arm_smccc_smc(OPTEE_SMC_GET_THREAD_COUNT, &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_GET_THREAD_COUNT); if ( resp.a0 =3D=3D OPTEE_SMC_RETURN_OK ) { max_optee_threads =3D resp.a1; @@ -209,7 +209,7 @@ static bool optee_probe(void) * call. It will return OPTEE_SMC_RETURN_UNKNOWN_FUNCTION if * OP-TEE have no virtualization support enabled. */ - arm_smccc_smc(OPTEE_SMC_VM_DESTROYED, 0, 0, 0, 0, 0, 0, 0, &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_VM_DESTROYED, 0, 0, 0, 0, 0, 0, 0); if ( resp.a0 =3D=3D OPTEE_SMC_RETURN_UNKNOWN_FUNCTION ) return false; =20 @@ -243,8 +243,8 @@ static int optee_domain_init(struct domain *d) * * a7 should be 0, so we can't skip last 6 parameters of arm_smccc_smc= () */ - arm_smccc_smc(OPTEE_SMC_VM_CREATED, OPTEE_CLIENT_ID(d), 0, 0, 0, 0, 0,= 0, - &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_VM_CREATED, OPTEE_CLIENT_ID(d), + 0, 0, 0, 0, 0, 0); if ( resp.a0 !=3D OPTEE_SMC_RETURN_OK ) { printk(XENLOG_WARNING "%pd: Unable to create OPTEE client: rc =3D = 0x%X\n", @@ -681,8 +681,8 @@ static int optee_relinquish_resources(struct domain *d) * * a7 should be 0, so we can't skip last 6 parameters of arm_smccc_smc= () */ - arm_smccc_smc(OPTEE_SMC_VM_DESTROYED, OPTEE_CLIENT_ID(d), 0, 0, 0, 0, = 0, 0, - &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_VM_DESTROYED, OPTEE_CLIENT_ID(d), + 0, 0, 0, 0, 0, 0); =20 ASSERT(!spin_is_locked(&ctx->lock)); ASSERT(!atomic_read(&ctx->call_count)); @@ -1171,15 +1171,15 @@ static void do_call_with_arg(struct optee_domain *c= tx, { struct arm_smccc_res res; =20 - arm_smccc_smc(a0, a1, a2, a3, a4, a5, 0, OPTEE_CLIENT_ID(current->doma= in), - &res); + res =3D arm_smccc_smc(a0, a1, a2, a3, a4, a5, 0, + OPTEE_CLIENT_ID(current->domain)); =20 if ( OPTEE_SMC_RETURN_IS_RPC(res.a0) ) { while ( handle_rpc_return(ctx, &res, regs, call) =3D=3D -ERESTART= ) { - arm_smccc_smc(res.a0, res.a1, res.a2, res.a3, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &res); + res =3D arm_smccc_smc(res.a0, res.a1, res.a2, res.a3, 0, 0, 0, + OPTEE_CLIENT_ID(current->domain)); =20 if ( !OPTEE_SMC_RETURN_IS_RPC(res.a0) ) break; @@ -1619,8 +1619,8 @@ static void handle_exchange_capabilities(struct cpu_u= ser_regs *regs) caps =3D get_user_reg(regs, 1); caps &=3D OPTEE_KNOWN_NSEC_CAPS; =20 - arm_smccc_smc(OPTEE_SMC_EXCHANGE_CAPABILITIES, caps, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_EXCHANGE_CAPABILITIES, caps, 0, 0, 0,= 0, 0, + OPTEE_CLIENT_ID(current->domain)); if ( resp.a0 !=3D OPTEE_SMC_RETURN_OK ) { set_user_reg(regs, 0, resp.a0); return; @@ -1664,8 +1664,8 @@ static bool optee_handle_call(struct cpu_user_regs *r= egs) return true; =20 case OPTEE_SMC_CALLS_UID: - arm_smccc_smc(OPTEE_SMC_CALLS_UID, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_CALLS_UID, 0, 0, 0, 0, 0, 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); set_user_reg(regs, 1, resp.a1); set_user_reg(regs, 2, resp.a2); @@ -1673,15 +1673,15 @@ static bool optee_handle_call(struct cpu_user_regs = *regs) return true; =20 case OPTEE_SMC_CALLS_REVISION: - arm_smccc_smc(OPTEE_SMC_CALLS_REVISION, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_CALLS_REVISION, 0, 0, 0, 0, 0, 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); set_user_reg(regs, 1, resp.a1); return true; =20 case OPTEE_SMC_CALL_GET_OS_UUID: - arm_smccc_smc(OPTEE_SMC_CALL_GET_OS_UUID, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain),&resp); + resp =3D arm_smccc_smc(OPTEE_SMC_CALL_GET_OS_UUID, 0, 0, 0, 0, 0, = 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); set_user_reg(regs, 1, resp.a1); set_user_reg(regs, 2, resp.a2); @@ -1689,21 +1689,21 @@ static bool optee_handle_call(struct cpu_user_regs = *regs) return true; =20 case OPTEE_SMC_CALL_GET_OS_REVISION: - arm_smccc_smc(OPTEE_SMC_CALL_GET_OS_REVISION, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_CALL_GET_OS_REVISION, 0, 0, 0, 0,= 0, 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); set_user_reg(regs, 1, resp.a1); return true; =20 case OPTEE_SMC_ENABLE_SHM_CACHE: - arm_smccc_smc(OPTEE_SMC_ENABLE_SHM_CACHE, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_ENABLE_SHM_CACHE, 0, 0, 0, 0, 0, = 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); return true; =20 case OPTEE_SMC_DISABLE_SHM_CACHE: - arm_smccc_smc(OPTEE_SMC_DISABLE_SHM_CACHE, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_DISABLE_SHM_CACHE, 0, 0, 0, 0, 0,= 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); if ( resp.a0 =3D=3D OPTEE_SMC_RETURN_OK ) { free_shm_rpc(ctx, regpair_to_uint64(resp.a1, resp.a2)); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 625d229396bb..6a5dcef2aa87 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1991,7 +1991,7 @@ void asmlinkage enter_hypervisor_from_guest_preirq(vo= id) =20 /* If the guest has disabled the workaround, bring it back on. */ if ( needs_ssbd_flip(v) ) - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1); } =20 /* @@ -2334,7 +2334,7 @@ void asmlinkage leave_hypervisor_to_guest(void) * If the guest wants it disabled, so be it... */ if ( needs_ssbd_flip(current) ) - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0); } =20 /* --=20 2.39.5