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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48440e094d0sm847709f8f.23.2026.08.31.05.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 05:19:52 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788178793; x=1788783593; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=ErWLaEnj10uj3lU2o4qVnGamxA9UVeFuuO35JsiTkDA=; b=gwUuILzhgdQwlH1vs8jcPGWvHW0NXiUqe0GjTpKNWXabscKTnfitj7iVD/qeR0mNQM TqMBvc3sG8ZpV9vaUXBpZPkT7Se0VRuGJ7VGi3FhiVogC11UIyCsIv8yMRdUtrAsb5Zt nQpF2tNS5Ysr79OxHzw0iJCaa7ieKVBhsZrDM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788178793; x=1788783593; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=ErWLaEnj10uj3lU2o4qVnGamxA9UVeFuuO35JsiTkDA=; b=EojxHvLpoQVsx6Jcn1KkRID6jQV1DvBVLxivb58bSOUu0EzyRP/jywqpuoOirlCvG+ OdBCfsyG5KKhjs80qcKLz2EDAfSZo74g/uPHV909Sq7H/ipHs3HfDPexp8NSHwomid6L VOEnPWx8ISHPWmbyK+N75WIgJlnx4SYCixSoLJS0Qe+1BY+xDULqNkEvlvyVLTfH7Qxn SfINRi398Nw+qX5pEUkTxGBi/79IY5g5eIl2AWEWmR+SDXy/Mp1lLGTyMSLJcYRO9/yO uWFeAAODaIadVUlHBVMmlBKZpGUay+ura7ETgkZI+lsw6FM4mIrmYCFiojoBNX1yMtyw U4jQ== X-Gm-Message-State: AFuF++nAbUSMtFz6n4hGk0Y4ETZZ7aKvGRmMGKVAzZnMiJEdgOp5yVoo Oq9yBxt84RI5OBQXFoa+JrDWCy21fSaXbCZ4SpWQUBHvT0Z2NJbcWOp/HA2S1M6RxT9ry83xIK8 /nWgVJn0= X-Gm-Gg: AR+sD13CvRpoD2WY2o5aRa29mc7Z/SFMgH+evrlZJCgrwKJ/fBvG47EBfNkss6Cf2bD UfPHkHzCv5UkVhy9vGJ1OwegH+jHS7Fb9cmYWXrW9w0+5ctFyevjOYlo/42/N44DthY1msMUfXO fE0gzTYrhHrIqoLuxv514CDLdbaPyZeO3CY/e0Oux/E5Q0iMsP28MebSKWQ4CmI1VXd/Lv0bl3E +jVhFrBPtTUTMAFL1KAXPpsfjVL6CjR0COpE6+JBDmz4hi2NSWME0GnXnICE/EmjNJ0b3PiFY+O Mh+MD2GD7MiINO9YTrC4cMOMD+eRMRcJrA6OhRA6cU76OWjLHcON5KERj1BHDCNx4o0SaOZd2JF 44qStXpnFaX/HdQA4RlWi5zcTPbi5K3R7qPEUwuF/Zz4GCbXKq6VPzZOGvTjI9ETaxLuTYoMwiY JBz7FDPIdgt6DdVy+1XdrYO6EpfSti5hW3QKxdFufBzxM0mmrUBfURb55E61ZTzhfQel424GS2E n0rGLFWkvrZvHVMUZ/IPlE9wz8IUSYVLsriKwU= X-Received: by 2002:a05:600c:4744:b0:499:8b13:3a98 with SMTP id 5b1f17b1804b1-49b91c2479amr389264755e9.4.1788178792772; Mon, 31 Aug 2026 05:19:52 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Setje-Eilers , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel Subject: [PATCH 1/6] xen/arm: Fix evaluation of parameters for SMCCC calls Date: Mon, 31 Aug 2026 13:19:40 +0100 Message-Id: <20260831121944.2908139-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260831121944.2908139-1-andrew.cooper3@citrix.com> References: <20260831121944.2908139-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-42698a/1788178793-AAEDE9EA-3C1B024F/0/0 X-purgate-type: clean X-purgate-size: 4638 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788178812040154100 Content-Type: text/plain; charset="utf-8" Contrary to what was claimed in commit 67bcf5eae709 ("xen/arm: Simplify type handling for SMCCC declarations"), there is an important reason to retain t= he intermediate variable. It is unsafe to have any logic between the assignme= nt of the register variabes and the asm() block they're used in. This logically reverts commit 67bcf5eae709 ("xen/arm: Simplify type handling for SMCCC declarations") while retaining the conversions from commit 7f15d5d13221 ("xen/treewide: More typeof() -> auto conversions"). Adjust __declare_arg_0() to match. It happens to be safe because it's the first register expression once all macros are expanded, but it really should be consistent with the others. Leave a comment explaining why they must be written like this. Fixes: 67bcf5eae709 ("xen/arm: Simplify type handling for SMCCC declaration= s") Reported-by: Jan Setje-Eilers Signed-off-by: Andrew Cooper --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers --- xen/arch/arm/include/asm/smccc.h | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 62c6985e7315..53cdddb690b7 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -108,37 +108,52 @@ struct arm_smccc_res { #define __constraint_read_6 __constraint_read_5, "r" (arg6) #define __constraint_read_7 __constraint_read_6, "r" (arg7) =20 +/* + * Macro arguments MUST be evaluated before being assigned to a register + * variable. + * + * This is manual register scheduling for the asm() statement, and any oth= er + * logic to evaluate may clobber the already-scheduled registers. + */ #define __declare_arg_0(a0, res) \ + auto __a0 =3D (uint32_t)(a0); \ struct arm_smccc_res *___res =3D (res); \ - register unsigned long arg0 ASM_REG(0) =3D (uint32_t)(a0) + register unsigned long arg0 ASM_REG(0) =3D __a0 =20 #define __declare_arg_1(a0, a1, res) \ + auto __a1 =3D (a1); \ __declare_arg_0(a0, res); \ - register auto arg1 ASM_REG(1) =3D (a1) + register auto arg1 ASM_REG(1) =3D __a1 =20 #define __declare_arg_2(a0, a1, a2, res) \ + auto __a2 =3D (a2); \ __declare_arg_1(a0, a1, res); \ - register auto arg2 ASM_REG(2) =3D (a2) + register auto arg2 ASM_REG(2) =3D __a2 =20 #define __declare_arg_3(a0, a1, a2, a3, res) \ + auto __a3 =3D (a3); \ __declare_arg_2(a0, a1, a2, res); \ - register auto arg3 ASM_REG(3) =3D (a3) + register auto arg3 ASM_REG(3) =3D __a3 =20 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ + auto __a4 =3D (a4); \ __declare_arg_3(a0, a1, a2, a3, res); \ - register auto arg4 ASM_REG(4) =3D (a4) + register auto arg4 ASM_REG(4) =3D __a4 =20 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ + auto __a5 =3D (a5); \ __declare_arg_4(a0, a1, a2, a3, a4, res); \ - register auto arg5 ASM_REG(5) =3D (a5) + register auto arg5 ASM_REG(5) =3D __a5 =20 #define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ + auto __a6 =3D (a6); \ __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ - register auto arg6 ASM_REG(6) =3D (a6) + register auto arg6 ASM_REG(6) =3D __a6 =20 #define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ + auto __a7 =3D (a7); \ __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ - register auto arg7 ASM_REG(7) =3D (a7) + register auto arg7 ASM_REG(7) =3D __a7 =20 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) base-commit: 79225a0c77e13b693b4d2b903a88289704b79db6 --=20 2.39.5 From nobody Thu Sep 3 07:04:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48440e094d0sm847709f8f.23.2026.08.31.05.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 05:19:53 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788178794; x=1788783594; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=MVv38LcWR6swmevPdVRrJrsniqIiQEzhS6N0zpQmzY8=; b=dIHg9EM3i3uShTC9Y48KQmQXv8PiVCrVPxu0q0OGpuYFAUIfgXFx5c2BZg6f+jDFvK Z3FIGYRzlUTjziWRQQ+GPJpIl4wodz34DJsvl0HQhUwmd+uS9ERM/+6Am+qYtRyGo6EK NdGPxGa+J093ujxy0r22ygy/Rq3U8QzPJdkmM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788178794; x=1788783594; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=MVv38LcWR6swmevPdVRrJrsniqIiQEzhS6N0zpQmzY8=; b=gb1UanIix2qrIfesedjJbNHIJ3xVzrAGhXFiC1CWGcqeCf7QOWewIzUDYRuycGBVyS JwFCVsNt70FpA6U3DkzfdUmeCPCsFDNUB/L6l48jrrj1ND0O5TcAMycK4q3Ik6raTcsz E2pT4BB1JwchU4HAg9CqpFWQmw8QKQDZI0D+KHiw/lGl6cyHBlPCRF9uzUL0tPl+tTTe 4zvxgEuj2qcUgoFmjB/aCKNJ5znjdAdZx5Gnew1caQcK1+46jzBuQrNUIHivr92D741l cHVyPBECrVXrUTWQaCL+vg+8g1SooLRGZKLTVgCgNQj6/0tzgumJodRWkyTAd/XhD8US +c9Q== X-Gm-Message-State: AFuF++nS27tyAykEhzOZnptHIFxycdYkJmlfmud9CGR+iEWLlUQU22Sl CURlXWUSxYqWBWQY4qhN5rsAOMXzfK6KwPrbXFNzTmjJAzFcNuQK8Xkf5QAwhiWmcXrqAP2HUC+ t62x7umw= X-Gm-Gg: AR+sD13cuDfw7j6LZKp5+N4FPqHhpHnDyY+vcnZwS/47KYopynglYqposoBltOCkZEv QG6hOfP35FjV0RMcy9jw6b2As1YGlwII8EYWigT9g1whGAoMnHGrJzJCP10K+vHRv3bBnGn+tbt eJXoOJcEVEFFm2dNMvS3Y3jTlO53PEgAQGE98V6lpGAo4TkPccJVxyJR+uYZjTYwFp16rAqHcgG L81HKmnzo1yWr7nMRk4eeWoLhzT8x2EaZVkIELR+xb59rSRm/JwI4eFQiyZFR3Rgx5+6yTmxdK/ BNIuqqXf1sAvotbz2Y116J4++vGFx2klP7+9Vc5x9DAH+XLwN/T+M4xnSciqIuEBnFqzPDDHZug O5eqAztSRtsEblw69hKCPDM0qbhu8gKsHoMLNN/eQlQYZh349AclvdqlmyhA5I/uTWZlgy9O+vc fTA/3vKhuSKhHrBI32ggK1xmXIfOxczZxcCtI/mVpDcQIKjyP3cIcnHdb8Qt2lp14nrkrdT1biV aPgQxwlZxi7uo1bx2gsUyP71uy3QtntYOXm5uw= X-Received: by 2002:a05:600c:3492:b0:49b:909e:922e with SMTP id 5b1f17b1804b1-49cdc4523d5mr2030625e9.10.1788178793786; Mon, 31 Aug 2026 05:19:53 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel , Jan Setje-Eilers Subject: [PATCH 2/6] xen/arm: Introduce arm_smccc_guest_smc() Date: Mon, 31 Aug 2026 13:19:41 +0100 Message-Id: <20260831121944.2908139-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260831121944.2908139-1-andrew.cooper3@citrix.com> References: <20260831121944.2908139-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-bad1c0/1788178794-FCC15034-9B0C6FF7/0/0 X-purgate-type: clean X-purgate-size: 8290 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788178816432158500 Content-Type: text/plain; charset="utf-8" Both {get,set}_user_reg() are out-of-line functions, leading to awful code generation. Introduce arm_smccc_guest_smc() to operate directly on guest registers. No functional change. Signed-off-by: Andrew Cooper --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers For arm64: add/remove: 0/0 grow/shrink: 2/4 up/down: 27/-864 (-837) Function old new delta symbols_addresses 35096 35120 +24 symbols_names 42958 42961 +3 imx8qm_smc 544 348 -196 scmi_handle_smc 372 152 -220 imx8m_smc 576 356 -220 zynqmp_eemi 864 636 -228 For arm32: add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-160 (-160) Function old new delta scmi_handle_smc 392 232 -160 --- xen/arch/arm/firmware/scmi-smc.c | 16 +----------- xen/arch/arm/include/asm/smccc.h | 29 +++++++++++++++++++++ xen/arch/arm/platforms/imx8m.c | 16 +----------- xen/arch/arm/platforms/imx8qm.c | 16 +----------- xen/arch/arm/platforms/xilinx-zynqmp-eemi.c | 17 ++---------- 5 files changed, 34 insertions(+), 60 deletions(-) diff --git a/xen/arch/arm/firmware/scmi-smc.c b/xen/arch/arm/firmware/scmi-= smc.c index 0835ddeeeccc..a0cc6c6192f8 100644 --- a/xen/arch/arm/firmware/scmi-smc.c +++ b/xen/arch/arm/firmware/scmi-smc.c @@ -50,7 +50,6 @@ static bool scmi_is_valid_smc_id(uint32_t fid) static bool scmi_handle_smc(struct cpu_user_regs *regs) { uint32_t fid =3D (uint32_t)get_user_reg(regs, 0); - struct arm_smccc_res res; =20 if ( !scmi_is_valid_smc_id(fid) ) return false; @@ -63,20 +62,7 @@ static bool scmi_handle_smc(struct cpu_user_regs *regs) } =20 /* For the moment, forward the SCMI Request to FW running at EL3 */ - arm_smccc_1_1_smc(fid, - get_user_reg(regs, 1), - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); + arm_smccc_guest_smc(regs); =20 return true; } diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 53cdddb690b7..832157f43734 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -202,6 +202,21 @@ struct arm_smccc_res { #ifdef CONFIG_ARM_32 #define arm_smccc_1_0_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) #define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) + +/* Make an SMCCC v1.1 compliant SMC call with guest register state. */ +static inline void arm_smccc_guest_smc(struct cpu_user_regs *regs) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_smc(regs->r0, regs->r1, regs->r2, regs->r3, + regs->r4, regs->r5, regs->r6, regs->r7, &res); + + regs->r0 =3D res.a0; + regs->r1 =3D res.a1; + regs->r2 =3D res.a2; + regs->r3 =3D res.a3; +} + #else =20 void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, @@ -251,6 +266,20 @@ void __arm_smccc_1_0_smc(register_t a0, register_t a1,= register_t a2, arm_smccc_1_0_smc(__VA_ARGS__); \ } while ( 0 ) =20 +/* Make an SMCCC v1.1 compliant SMC call with guest register state. */ +static inline void arm_smccc_guest_smc(struct cpu_user_regs *regs) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_smc(regs->x0, regs->x1, regs->x2, regs->x3, + regs->x4, regs->x5, regs->x6, regs->x7, &res); + + regs->x0 =3D res.a0; + regs->x1 =3D res.a1; + regs->x2 =3D res.a2; + regs->x3 =3D res.a3; +} + /* * struct arm_smccc_1_2_regs - Arguments for or Results from SMC call * @a0-a17 argument values from registers 0 to 17 diff --git a/xen/arch/arm/platforms/imx8m.c b/xen/arch/arm/platforms/imx8m.c index 669dd517e057..efb0ad20d6e8 100644 --- a/xen/arch/arm/platforms/imx8m.c +++ b/xen/arch/arm/platforms/imx8m.c @@ -50,7 +50,6 @@ static bool imx8m_smc(struct cpu_user_regs *regs) { uint32_t function_id =3D get_user_reg(regs, 0); uint32_t subfunction_id =3D get_user_reg(regs, 1); - struct arm_smccc_res res; =20 if ( !cpus_have_const_cap(ARM_SMCCC_1_1) ) { @@ -122,20 +121,7 @@ static bool imx8m_smc(struct cpu_user_regs *regs) return false; } =20 - arm_smccc_1_1_smc(function_id, - subfunction_id, - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); + arm_smccc_guest_smc(regs); =20 return true; } diff --git a/xen/arch/arm/platforms/imx8qm.c b/xen/arch/arm/platforms/imx8q= m.c index 3600a073e8ba..7249e14ab640 100644 --- a/xen/arch/arm/platforms/imx8qm.c +++ b/xen/arch/arm/platforms/imx8qm.c @@ -67,7 +67,6 @@ static bool imx8qm_smc(struct cpu_user_regs *regs) { uint32_t function_id =3D get_user_reg(regs, 0); uint32_t subfunction_id =3D get_user_reg(regs, 1); - struct arm_smccc_res res; =20 if ( !cpus_have_const_cap(ARM_SMCCC_1_1) ) { @@ -106,20 +105,7 @@ static bool imx8qm_smc(struct cpu_user_regs *regs) } =20 allow_call: - arm_smccc_1_1_smc(function_id, - subfunction_id, - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); + arm_smccc_guest_smc(regs); =20 return true; } diff --git a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c b/xen/arch/arm/pla= tforms/xilinx-zynqmp-eemi.c index 2053ed7ac5f6..326c8a1ba6e5 100644 --- a/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c +++ b/xen/arch/arm/platforms/xilinx-zynqmp-eemi.c @@ -51,7 +51,6 @@ static inline bool domain_has_reset_access(struct domain = *d, uint32_t rst) =20 bool zynqmp_eemi(struct cpu_user_regs *regs) { - struct arm_smccc_res res; uint32_t fid =3D get_user_reg(regs, 0); uint32_t nodeid =3D get_user_reg(regs, 1); unsigned int pm_fn =3D fid & 0xFFFF; @@ -187,20 +186,8 @@ bool zynqmp_eemi(struct cpu_user_regs *regs) * can forward the whole command to firmware without additional * parameters checks. */ - arm_smccc_1_1_smc(get_user_reg(regs, 0), - get_user_reg(regs, 1), - get_user_reg(regs, 2), - get_user_reg(regs, 3), - get_user_reg(regs, 4), - get_user_reg(regs, 5), - get_user_reg(regs, 6), - get_user_reg(regs, 7), - &res); - - set_user_reg(regs, 0, res.a0); - set_user_reg(regs, 1, res.a1); - set_user_reg(regs, 2, res.a2); - set_user_reg(regs, 3, res.a3); + arm_smccc_guest_smc(regs); + return true; =20 done: --=20 2.39.5 From nobody Thu Sep 3 07:04:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Use PASTE() rather than opencoding it. * Adust the indentation of trailing \'s for consistency. * Drop the newline at the end of the instruction. * Indent the if condition correctly. ___res is always of type arm_smccc_res (declared in __declare_arg_0()), so drop the typeof(). * Drop arm_smccc_1_0_smc() as it has no users. No functional change. Signed-off-by: Andrew Cooper --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers --- xen/arch/arm/include/asm/smccc.h | 45 ++++++++++++++++---------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 832157f43734..5fe54013ac83 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -56,6 +56,8 @@ =20 #ifndef __ASSEMBLER__ =20 +#include + extern uint32_t smccc_ver; =20 /* Check if this is fast call. */ @@ -115,24 +117,24 @@ struct arm_smccc_res { * This is manual register scheduling for the asm() statement, and any oth= er * logic to evaluate may clobber the already-scheduled registers. */ -#define __declare_arg_0(a0, res) \ - auto __a0 =3D (uint32_t)(a0); \ - struct arm_smccc_res *___res =3D (res); \ +#define __declare_arg_0(a0, res) \ + auto __a0 =3D (uint32_t)(a0); \ + struct arm_smccc_res *___res =3D (res); \ register unsigned long arg0 ASM_REG(0) =3D __a0 =20 -#define __declare_arg_1(a0, a1, res) \ - auto __a1 =3D (a1); \ - __declare_arg_0(a0, res); \ +#define __declare_arg_1(a0, a1, res) \ + auto __a1 =3D (a1); \ + __declare_arg_0(a0, res); \ register auto arg1 ASM_REG(1) =3D __a1 =20 -#define __declare_arg_2(a0, a1, a2, res) \ - auto __a2 =3D (a2); \ - __declare_arg_1(a0, a1, res); \ +#define __declare_arg_2(a0, a1, a2, res) \ + auto __a2 =3D (a2); \ + __declare_arg_1(a0, a1, res); \ register auto arg2 ASM_REG(2) =3D __a2 =20 -#define __declare_arg_3(a0, a1, a2, a3, res) \ - auto __a3 =3D (a3); \ - __declare_arg_2(a0, a1, a2, res); \ +#define __declare_arg_3(a0, a1, a2, a3, res) \ + auto __a3 =3D (a3); \ + __declare_arg_2(a0, a1, a2, res); \ register auto arg3 ASM_REG(3) =3D __a3 =20 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ @@ -158,12 +160,6 @@ struct arm_smccc_res { #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) =20 -#define ___constraints(count) \ - : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3) \ - : __constraint_read_ ## count \ - : "memory" -#define __constraints(count) ___constraints(count) - /* * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call * @@ -189,10 +185,14 @@ struct arm_smccc_res { register unsigned long r2 ASM_REG(2); \ register unsigned long r3 ASM_REG(3); \ __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ - asm volatile("smc #0\n" \ - __constraints(__count_args(__VA_ARGS__))); \ + asm volatile ( \ + "smc #0" \ + : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3) \ + : PASTE(__constraint_read_, \ + __count_args(__VA_ARGS__)) \ + : "memory" ); \ if ( ___res ) \ - *___res =3D (typeof(*___res)){r0, r1, r2, r3}; \ + *___res =3D (struct arm_smccc_res){ r0, r1, r2, r3 }; \ } while ( 0 ) =20 /* @@ -200,7 +200,6 @@ struct arm_smccc_res { * v1.1. */ #ifdef CONFIG_ARM_32 -#define arm_smccc_1_0_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) #define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) =20 /* Make an SMCCC v1.1 compliant SMC call with guest register state. */ @@ -217,7 +216,7 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) regs->r3 =3D res.a3; } =20 -#else +#else /* CONFIG_ARM_64 */ =20 void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, register_t a3, register_t a4, register_t a5, --=20 2.39.5 From nobody Thu Sep 3 07:04:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48440e094d0sm847709f8f.23.2026.08.31.05.19.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 05:19:55 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788178796; x=1788783596; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=PmiQSMZPixZ6AjqLdv2qezZIur3EMHWcw7A7AXRMY8E=; b=julaYGgfxZvL1vSMT3Zztt5xs75D1qWygTk37pJvgjnbvwCV3ghHQBpTc9CA9vnfth j/zuwFTWOkR1VS+y09VsaxsIZgPEWVWLape0Cs62YVnMcNoTnc/HcwDNCzl76cmNrXkZ 1M56mSG7a/2mYQr5sStM+fRj6hTnEStKE4ETg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788178796; x=1788783596; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=PmiQSMZPixZ6AjqLdv2qezZIur3EMHWcw7A7AXRMY8E=; b=R95OfJvAd5Q9EXumA15aMgA3I8p6z6HnQdzKNpO1VQB8Lb5HxW7Hq91OKadl9Lgwh9 RSjvRME9orIP//cFdRHIP3kReN7gAmu4hCoSr3TeYKEN6JcHwpwhfiQQr/5bxm1oMeP3 ptGrIcG90tQmDgwaQj24270RrZnmEC/wWzD0VRW51sy8kkIte0KzyAAeF9Vsa3TfTLN3 +cCKCqW4l2ejLlzE+yJK4QJY5UB3qoHvlz7YgdQxNvTpi7PSC7vJoiJ7S7SQnwCUWe1S 8K96Kpc2NIKtOju9AHnWTxU5wJ7p2jj1aUiIxOcm1ZwCtjh1qIHgnM1m4jd0JIi3feRj tGzA== X-Gm-Message-State: AFuF++m/gusRMwts54mVA4d61LqhYA/PkHOJfOLX/cfM0dWU/ve0cMCG FZh+f78QpKnUXKlC/738dK/XYIabSm7XDPo18NeCS4/FQbfEZMaIO1vweKHL7X4E7qo3mdJAMHO Ub5Tg X-Gm-Gg: AYBFou3DrYm+wHN0CF1cbTM+cX9WKZdZpXpzidTek62fNW/e8Rn3SLL0ta0prLzhs32 8bUMPvPI3ZJO+GT0mud6IP2TnoRZ2IrWY2AzdMgmexkneZCoe3kSqoCe08fXrtJJXmTol5uV+Z5 xI95DDeE+YiCK79PdYZix3Mr8njZr1esfX2QCR8IJb8W6+ZjeXB8F767odXt1yretXPRYvzxWo+ 7r8HQgP8kGiQjv56lOQmHmX/CoCZlZj+5ThQF6uCTY4omvpnAETBEjM7khRdub4BkIooqsc9Yyw +Dk0QgsYD2uKeGxanXNA2UZLF2/djHSC0pvZFm5bCGZfhFDCSDD2Q0YwhWjyFknthWPGTldwuit q4E5vJ7CSLb5+hL1aesmaLA6s05DDTq8VGXJUR7er2OWZT7C7f48qMxNf/NmzoM2Mp1pPcmI4Pe F9NJ1ZUYq3uq5zvHxU/7r8p3nYceQL7S0TN0iZRt/FY1qfbSlidQvEL3066DBkZ/l7VXsOjvZ5f wyqWkXM76sgZ/83IgbNiAIUUWacr86UOn7aB+A= X-Received: by 2002:a05:6000:38f:b0:484:3315:1a38 with SMTP id ffacd0b85a97d-48433152785mr26443741f8f.28.1788178795509; Mon, 31 Aug 2026 05:19:55 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel , Jan Setje-Eilers Subject: [PATCH 4/6] xen/arm: Rewrite arm_smccc_smc() for arm64 Date: Mon, 31 Aug 2026 13:19:43 +0100 Message-Id: <20260831121944.2908139-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260831121944.2908139-1-andrew.cooper3@citrix.com> References: <20260831121944.2908139-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-bad1c0/1788178796-BC4CB034-8DBD56A9/0/0 X-purgate-type: clean X-purgate-size: 9682 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788178831919154100 Content-Type: text/plain; charset="utf-8" PSCI v1.0 says that x4 thru x17 may be clobbered. PSCI v1.1 says they are strictly preserved unless they contain return values. Xen deals with this by having __arm_smccc_1_0_smc() as an out-of-line function, but this causes awful code generation in arm_smccc_smc(). cpus_have_const_cap() is opaque to the optimiser, so we end up with one bas= ic block doing the reasonably-ok arm_smccc_1_1_smc() code generation and a sec= ond basic block setting up all 8 input registers even when they're not needed, spilling or discarding x8 thru x17, and calling an out-of-line function. Remove __arm_smccc_1_0_smc() entirely, and rewrite arm_smccc_smc() to decla= re x4 thru x17 as clobbered. This fully inlines the SMC, is a single basic block which instructs the compiler to spill or discard the potentially clobbered registers, and only sets up the necessary number of arguments for the call. No functional change. Signed-off-by: Andrew Cooper --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers Bloat-o-meter reports: add/remove: 0/1 grow/shrink: 0/10 up/down: 0/-795 (-795) Function old new delta symbols_sorted_offsets 23832 23824 -8 symbols_names 42962 42943 -19 symbols_addresses 35128 35104 -24 __arm_smccc_1_0_smc 32 - -32 call_psci_cpu_off 144 76 -68 seattle_system_reset 92 16 -76 seattle_system_off 92 16 -76 call_psci_system_reset 112 32 -80 call_psci_system_off 112 32 -80 call_psci_cpu_on 252 124 -128 psci_init 628 424 -204 An alternative way to do this would be to have x8 thru x17 in the clobber l= ist rather than the output list which would reduce the source size, but this fo= rm is more amenable to having PSCI v1.2 worked into it too. --- xen/arch/arm/arm64/smc.S | 16 ------ xen/arch/arm/include/asm/smccc.h | 95 ++++++++++++++++---------------- 2 files changed, 48 insertions(+), 63 deletions(-) diff --git a/xen/arch/arm/arm64/smc.S b/xen/arch/arm/arm64/smc.S index 68b05e8ddd12..65b4eabe4f87 100644 --- a/xen/arch/arm/arm64/smc.S +++ b/xen/arch/arm/arm64/smc.S @@ -13,22 +13,6 @@ * GNU General Public License for more details. */ =20 -/* - * void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, - * register_t a3, register_t a4, register_t a5, - * register_t a6, register_t a7, - * struct arm_smccc_res *res) - */ -FUNC(__arm_smccc_1_0_smc) - smc #0 - ldr x4, [sp] - cbz x4, 1f /* No need to store the result */ - stp x0, x1, [x4, #SMCCC_RES_a0] - stp x2, x3, [x4, #SMCCC_RES_a2] -1: - ret -END(__arm_smccc_1_0_smc) - /* * void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args, * struct arm_smccc_1_2_regs *res) diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 5fe54013ac83..8920c54b09a6 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -16,9 +16,6 @@ #ifndef __ASM_ARM_SMCCC_H__ #define __ASM_ARM_SMCCC_H__ =20 -#include -#include - #define SMCCC_VERSION_MAJOR_SHIFT 16 #define SMCCC_VERSION_MINOR_MASK \ ((1U << SMCCC_VERSION_MAJOR_SHIFT) - 1) @@ -57,6 +54,9 @@ #ifndef __ASSEMBLER__ =20 #include +#include + +#include =20 extern uint32_t smccc_ver; =20 @@ -160,6 +160,8 @@ struct arm_smccc_res { #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) #define __declare_args(count, ...) ___declare_args(count, __VA_ARGS__) =20 +#ifdef CONFIG_ARM_32 + /* * arm_smccc_1_1_smc() - make an SMCCC v1.1 compliant SMC call * @@ -199,7 +201,6 @@ struct arm_smccc_res { * The calling convention for arm32 is the same for both SMCCC v1.0 and * v1.1. */ -#ifdef CONFIG_ARM_32 #define arm_smccc_smc(...) arm_smccc_1_1_smc(__VA_ARGS__) =20 /* Make an SMCCC v1.1 compliant SMC call with guest register state. */ @@ -218,53 +219,53 @@ static inline void arm_smccc_guest_smc(struct cpu_use= r_regs *regs) =20 #else /* CONFIG_ARM_64 */ =20 -void __arm_smccc_1_0_smc(register_t a0, register_t a1, register_t a2, - register_t a3, register_t a4, register_t a5, - register_t a6, register_t a7, - struct arm_smccc_res *res); - -/* Macros to handle variadic parameter for SMCCC v1.0 helper */ -#define __arm_smccc_1_0_smc_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ - __arm_smccc_1_0_smc(a0, a1, a2, a3, a4, a5, a6, a7, res) - -#define __arm_smccc_1_0_smc_6(a0, a1, a2, a3, a4, a5, a6, res) \ - __arm_smccc_1_0_smc_7(a0, a1, a2, a3, a4, a5, a6, 0, res) - -#define __arm_smccc_1_0_smc_5(a0, a1, a2, a3, a4, a5, res) \ - __arm_smccc_1_0_smc_6(a0, a1, a2, a3, a4, a5, 0, res) - -#define __arm_smccc_1_0_smc_4(a0, a1, a2, a3, a4, res) \ - __arm_smccc_1_0_smc_5(a0, a1, a2, a3, a4, 0, res) - -#define __arm_smccc_1_0_smc_3(a0, a1, a2, a3, res) \ - __arm_smccc_1_0_smc_4(a0, a1, a2, a3, 0, res) - -#define __arm_smccc_1_0_smc_2(a0, a1, a2, res) \ - __arm_smccc_1_0_smc_3(a0, a1, a2, 0, res) - -#define __arm_smccc_1_0_smc_1(a0, a1, res) \ - __arm_smccc_1_0_smc_2(a0, a1, 0, res) - -#define __arm_smccc_1_0_smc_0(a0, res) \ - __arm_smccc_1_0_smc_1(a0, 0, res) - -#define ___arm_smccc_1_0_smc_count(count, ...) \ - __arm_smccc_1_0_smc_ ## count(__VA_ARGS__) - -#define __arm_smccc_1_0_smc_count(count, ...) \ - ___arm_smccc_1_0_smc_count(count, __VA_ARGS__) - -#define arm_smccc_1_0_smc(...) = \ - __arm_smccc_1_0_smc_count(__count_args(__VA_ARGS__), __VA_ARGS__) - +/* + * Make an SMCCC call compatible with both PSCI v1.1 and v1.0. + * + * PSCI v1.1 says that x4 through x17 are strictly preserved unless they + * contain return data. PSCI v1.0 says they clobbered. + * + * Xen doesn't make PSCI v1.1 calls which expect more than 4 return regist= ers, + * so imply list x4 through x17 as clobbered. + */ #define arm_smccc_smc(...) \ do { \ - if ( cpus_have_const_cap(ARM_SMCCC_1_1) ) \ - arm_smccc_1_1_smc(__VA_ARGS__); \ - else \ - arm_smccc_1_0_smc(__VA_ARGS__); \ + register unsigned long r0 ASM_REG(0); \ + register unsigned long r1 ASM_REG(1); \ + register unsigned long r2 ASM_REG(2); \ + register unsigned long r3 ASM_REG(3); \ + /* Potentially clobbered in PSCI 1.0 */ \ + register unsigned long c4 ASM_REG(4); \ + register unsigned long c5 ASM_REG(5); \ + register unsigned long c6 ASM_REG(6); \ + register unsigned long c7 ASM_REG(7); \ + register unsigned long c8 ASM_REG(8); \ + register unsigned long c9 ASM_REG(9); \ + register unsigned long c10 ASM_REG(10); \ + register unsigned long c11 ASM_REG(11); \ + register unsigned long c12 ASM_REG(12); \ + register unsigned long c13 ASM_REG(13); \ + register unsigned long c14 ASM_REG(14); \ + register unsigned long c15 ASM_REG(15); \ + register unsigned long c16 ASM_REG(16); \ + register unsigned long c17 ASM_REG(17); \ + __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + asm volatile ( \ + "smc #0" \ + : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3), \ + "=3Dr" (c4), "=3Dr" (c5), "=3Dr" (c6), "=3Dr" (c7), \ + "=3Dr" (c8), "=3Dr" (c9), "=3Dr" (c10), "=3Dr" (c11), \ + "=3Dr" (c12), "=3Dr" (c13), "=3Dr" (c14), "=3Dr" (c15), \ + "=3Dr" (c16), "=3Dr" (c17) \ + : PASTE(__constraint_read_, \ + __count_args(__VA_ARGS__)) \ + : "memory" ); \ + if ( ___res ) \ + *___res =3D (struct arm_smccc_res){ r0, r1, r2, r3 }; \ } while ( 0 ) =20 +#define arm_smccc_1_1_smc(...) arm_smccc_smc(__VA_ARGS__) + /* Make an SMCCC v1.1 compliant SMC call with guest register state. */ static inline void arm_smccc_guest_smc(struct cpu_user_regs *regs) { --=20 2.39.5 From nobody Thu Sep 3 07:04:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48440e094d0sm847709f8f.23.2026.08.31.05.19.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2026 05:19:55 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1788178797; x=1788783597; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=sWHVN1KYguuCvFJ0vjo0Hfd/94qGB/JA1/otXXv1BOY=; b=GSJfM7hUQYWphHpC9rV673wP2ODDBdewaOui6yWsD0CQMYI354BoBKNYzMdt0JPpVP vTlbCrTdN2abFBIuBAE2cZFC1mIULKeHTYqL3pvqvCAYIieW2c2hlQT74MTxxNel2JOt 0x5SDXO6e3HdpBpXg/8MnIZqMb51+lK83Uqxs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1788178797; x=1788783597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=sWHVN1KYguuCvFJ0vjo0Hfd/94qGB/JA1/otXXv1BOY=; b=MaB49NmTwHZuiXVrMXRYveCiVnI/dj7WWkYOc1wIrfOh9iBfiTHhFSj9HytevOQNfB v1t9k8fGtUw7rS5ckxpjkGnZKNlJKuQt9a5CRRiJt3rOTnnrvhq88I72o/BhNSu6s2E9 uYaiMq8pRWx7BN7UezwVS5QyJcjpZocg6M3EblA4EM144i/LWr+plVgUm6qRKHdjPK1M 8bSScCy6MDE0O4ZCtGjF5x7c6egKQGYC/upam2iyodroYhl2kRYSV2nznXrp2IS7JgbU oHrljD8Pb5rYDg0cwfH5/pFK+6YukQRfF5T/+SD5yz4M9lolR+wbMtlhgQdZTUScC02P MvtQ== X-Gm-Message-State: AFuF++kI1jK/0t7kJNbp9h5czEswmRWb3ziirUxuXN57JFM9DYBI9EEG obJZnFBirwd6MnmzHIIu4veUfja0G/rhog5geM/gAqWrXIxXYsUF5mA85ozMYKtbWuOawzaJMBp qzv29 X-Gm-Gg: AYBFou1WtDVtnsZEymZpHeY7VDo70hqiTasoH2/Tf8zl4Dal+4Xextx7E9ij3vfpSok 6CPd/ZvXwz+dtGEgXdkPjb2O4B/R0Cv50/eHfi0WfWJWEg2QVy+Btu8Bv5zni7zmNtD17Pl2sdt i50X8WmzqXmSUUcdBAAzZyfZN+Ajd3xDUMZi5X9gqC+lFRuWhofwWoFwT2BUr2tKcjdsyQM6yYn yhzldFT+kT48f/myptmO2RKpUTuSSqqAxPnSScuQdxX39v1b2KWOMbtEVl6wUAg2HvLW6UcGDdF E8Mkb9lqsWskrlL7EP2bwqHfJ8AEIVRZy+b6u2P1bAWxSQf4Orxx+kS1kTjmfc0uHS/YTqaLVq9 xHKltD63ESThHuEkx/ku7lOnUA71kQPC/IYH+fnTKDtFrMsUsfpE/bAx+FA/8BL2ZLSh1jTbGQ2 m4LfGceDBsRwtD2a+uTIltRJE/zQSUpbzbrS3Eytv9aOrwTPfQ4+ZLZV499wVSItUGWcw55jW9L gyzf1UTT0ngaZTWlcc5jrWRJ4Mu5tSzkLWTmH2DMaSlxw9H6YE= X-Received: by 2002:a05:6000:4a1e:b0:45e:e1a4:c4c3 with SMTP id ffacd0b85a97d-482f79b94f2mr42492389f8f.15.1788178796463; Mon, 31 Aug 2026 05:19:56 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Stefano Stabellini , Julien Grall , Volodymyr Babchuk , Bertrand Marquis , Michal Orzel , Jan Setje-Eilers Subject: [PATCH 5/6] xen/arm: Rewrite arm_smccc_*() to return by value Date: Mon, 31 Aug 2026 13:19:44 +0100 Message-Id: <20260831121944.2908139-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260831121944.2908139-1-andrew.cooper3@citrix.com> References: <20260831121944.2908139-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1788178797-A5EC6AE4-E27D34CC/0/0 X-purgate-type: clean X-purgate-size: 23654 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1788178821867154100 Content-Type: text/plain; charset="utf-8" Use statement expressions to return struct arm_smccc_res which makes the co= de read a lot more normally, and avoids needing to pass in NULL in order to sk= ip return information. More importantly, it removes the local implementation of __count_args() whi= ch is off by two and deeply confusing to try and follow. No functional change. Signed-off-by: Andrew Cooper --- CC: Stefano Stabellini CC: Julien Grall CC: Volodymyr Babchuk CC: Bertrand Marquis CC: Michal Orzel CC: Jan Setje-Eilers Xen compiles identically before and after this change, for both arm32 and a= rm64. --- xen/arch/arm/cpuerrata.c | 18 +++---- xen/arch/arm/include/asm/smccc.h | 87 ++++++++++++++------------------ xen/arch/arm/platforms/exynos5.c | 2 +- xen/arch/arm/platforms/seattle.c | 4 +- xen/arch/arm/psci.c | 17 +++---- xen/arch/arm/tee/optee.c | 47 +++++++++-------- xen/arch/arm/traps.c | 4 +- 7 files changed, 84 insertions(+), 95 deletions(-) diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c index 3a32183618dc..35ad98d29d14 100644 --- a/xen/arch/arm/cpuerrata.c +++ b/xen/arch/arm/cpuerrata.c @@ -179,8 +179,8 @@ static int enable_smccc_arch_workaround_1(void *data) if ( smccc_ver < SMCCC_VERSION(1, 1) ) goto warn; =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, - ARM_SMCCC_ARCH_WORKAROUND_1_FID, &res); + res =3D arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_1_FID); /* The return value is in the lower 32-bits. */ if ( (int)res.a0 < 0 ) goto warn; @@ -256,8 +256,8 @@ static int enable_spectre_bhb_workaround(void *data) if ( smccc_ver < SMCCC_VERSION(1, 1) ) goto warn; =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, - ARM_SMCCC_ARCH_WORKAROUND_3_FID, &res); + res =3D arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_3_FID); /* The return value is in the lower 32-bits. */ if ( (int)res.a0 < 0 ) { @@ -398,8 +398,8 @@ static bool has_ssbd_mitigation(const struct arm_cpu_ca= pabilities *entry) if ( smccc_ver < SMCCC_VERSION(1, 1) ) return false; =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, - ARM_SMCCC_ARCH_WORKAROUND_2_FID, &res); + res =3D arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FID, + ARM_SMCCC_ARCH_WORKAROUND_2_FID); =20 switch ( (int)res.a0 ) { @@ -429,7 +429,7 @@ static bool has_ssbd_mitigation(const struct arm_cpu_ca= pabilities *entry) case ARM_SSBD_FORCE_DISABLE: printk_once("%s disabled from command-line\n", entry->desc); =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0); required =3D false; break; =20 @@ -437,7 +437,7 @@ static bool has_ssbd_mitigation(const struct arm_cpu_ca= pabilities *entry) if ( required ) { this_cpu(ssbd_callback_required) =3D 1; - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1); } =20 break; @@ -445,7 +445,7 @@ static bool has_ssbd_mitigation(const struct arm_cpu_ca= pabilities *entry) case ARM_SSBD_FORCE_ENABLE: printk_once("%s forced from command-line\n", entry->desc); =20 - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1); required =3D true; break; =20 diff --git a/xen/arch/arm/include/asm/smccc.h b/xen/arch/arm/include/asm/sm= ccc.h index 8920c54b09a6..ebed2ff7c7d2 100644 --- a/xen/arch/arm/include/asm/smccc.h +++ b/xen/arch/arm/include/asm/smccc.h @@ -95,20 +95,14 @@ struct arm_smccc_res { unsigned long a3; }; =20 -/* SMCCC v1.1 implementation madness follows */ -#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x - -#define __count_args(...) \ - ___count_args(__VA_ARGS__, 7, 6, 5, 4, 3, 2, 1, 0) - -#define __constraint_read_0 "r" (arg0) -#define __constraint_read_1 __constraint_read_0, "r" (arg1) -#define __constraint_read_2 __constraint_read_1, "r" (arg2) -#define __constraint_read_3 __constraint_read_2, "r" (arg3) -#define __constraint_read_4 __constraint_read_3, "r" (arg4) -#define __constraint_read_5 __constraint_read_4, "r" (arg5) -#define __constraint_read_6 __constraint_read_5, "r" (arg6) -#define __constraint_read_7 __constraint_read_6, "r" (arg7) +#define __constraint_read_1 "r" (arg0) +#define __constraint_read_2 __constraint_read_1, "r" (arg1) +#define __constraint_read_3 __constraint_read_2, "r" (arg2) +#define __constraint_read_4 __constraint_read_3, "r" (arg3) +#define __constraint_read_5 __constraint_read_4, "r" (arg4) +#define __constraint_read_6 __constraint_read_5, "r" (arg5) +#define __constraint_read_7 __constraint_read_6, "r" (arg6) +#define __constraint_read_8 __constraint_read_7, "r" (arg7) =20 /* * Macro arguments MUST be evaluated before being assigned to a register @@ -117,44 +111,43 @@ struct arm_smccc_res { * This is manual register scheduling for the asm() statement, and any oth= er * logic to evaluate may clobber the already-scheduled registers. */ -#define __declare_arg_0(a0, res) \ +#define __declare_arg_1(a0) \ auto __a0 =3D (uint32_t)(a0); \ - struct arm_smccc_res *___res =3D (res); \ register unsigned long arg0 ASM_REG(0) =3D __a0 =20 -#define __declare_arg_1(a0, a1, res) \ +#define __declare_arg_2(a0, a1) \ auto __a1 =3D (a1); \ - __declare_arg_0(a0, res); \ + __declare_arg_1(a0); \ register auto arg1 ASM_REG(1) =3D __a1 =20 -#define __declare_arg_2(a0, a1, a2, res) \ +#define __declare_arg_3(a0, a1, a2) \ auto __a2 =3D (a2); \ - __declare_arg_1(a0, a1, res); \ + __declare_arg_2(a0, a1); \ register auto arg2 ASM_REG(2) =3D __a2 =20 -#define __declare_arg_3(a0, a1, a2, a3, res) \ +#define __declare_arg_4(a0, a1, a2, a3) \ auto __a3 =3D (a3); \ - __declare_arg_2(a0, a1, a2, res); \ + __declare_arg_3(a0, a1, a2); \ register auto arg3 ASM_REG(3) =3D __a3 =20 -#define __declare_arg_4(a0, a1, a2, a3, a4, res) \ +#define __declare_arg_5(a0, a1, a2, a3, a4) \ auto __a4 =3D (a4); \ - __declare_arg_3(a0, a1, a2, a3, res); \ + __declare_arg_4(a0, a1, a2, a3); \ register auto arg4 ASM_REG(4) =3D __a4 =20 -#define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ +#define __declare_arg_6(a0, a1, a2, a3, a4, a5) \ auto __a5 =3D (a5); \ - __declare_arg_4(a0, a1, a2, a3, a4, res); \ + __declare_arg_5(a0, a1, a2, a3, a4); \ register auto arg5 ASM_REG(5) =3D __a5 =20 -#define __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res) \ - auto __a6 =3D (a6); \ - __declare_arg_5(a0, a1, a2, a3, a4, a5, res); \ +#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6) \ + auto __a6 =3D (a6); \ + __declare_arg_6(a0, a1, a2, a3, a4, a5); \ register auto arg6 ASM_REG(6) =3D __a6 =20 -#define __declare_arg_7(a0, a1, a2, a3, a4, a5, a6, a7, res) \ - auto __a7 =3D (a7); \ - __declare_arg_6(a0, a1, a2, a3, a4, a5, a6, res); \ +#define __declare_arg_8(a0, a1, a2, a3, a4, a5, a6, a7) \ + auto __a7 =3D (a7); \ + __declare_arg_7(a0, a1, a2, a3, a4, a5, a6); \ register auto arg7 ASM_REG(7) =3D __a7 =20 #define ___declare_args(count, ...) __declare_arg_ ## count(__VA_ARGS__) @@ -181,21 +174,20 @@ struct arm_smccc_res { * makes it stick. */ #define arm_smccc_1_1_smc(...) \ - do { \ + ({ \ register unsigned long r0 ASM_REG(0); \ register unsigned long r1 ASM_REG(1); \ register unsigned long r2 ASM_REG(2); \ register unsigned long r3 ASM_REG(3); \ - __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + __declare_args(count_args(__VA_ARGS__), __VA_ARGS__); \ asm volatile ( \ "smc #0" \ : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3) \ : PASTE(__constraint_read_, \ - __count_args(__VA_ARGS__)) \ + count_args(__VA_ARGS__)) \ : "memory" ); \ - if ( ___res ) \ - *___res =3D (struct arm_smccc_res){ r0, r1, r2, r3 }; \ - } while ( 0 ) + (struct arm_smccc_res){ r0, r1, r2, r3 }; \ + }) =20 /* * The calling convention for arm32 is the same for both SMCCC v1.0 and @@ -208,8 +200,8 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) { struct arm_smccc_res res; =20 - arm_smccc_1_1_smc(regs->r0, regs->r1, regs->r2, regs->r3, - regs->r4, regs->r5, regs->r6, regs->r7, &res); + res =3D arm_smccc_1_1_smc(regs->r0, regs->r1, regs->r2, regs->r3, + regs->r4, regs->r5, regs->r6, regs->r7); =20 regs->r0 =3D res.a0; regs->r1 =3D res.a1; @@ -229,7 +221,7 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) * so imply list x4 through x17 as clobbered. */ #define arm_smccc_smc(...) \ - do { \ + ({ \ register unsigned long r0 ASM_REG(0); \ register unsigned long r1 ASM_REG(1); \ register unsigned long r2 ASM_REG(2); \ @@ -249,7 +241,7 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) register unsigned long c15 ASM_REG(15); \ register unsigned long c16 ASM_REG(16); \ register unsigned long c17 ASM_REG(17); \ - __declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \ + __declare_args(count_args(__VA_ARGS__), __VA_ARGS__); \ asm volatile ( \ "smc #0" \ : "=3Dr" (r0), "=3Dr" (r1), "=3Dr" (r2), "=3Dr" (r3), \ @@ -258,11 +250,10 @@ static inline void arm_smccc_guest_smc(struct cpu_use= r_regs *regs) "=3Dr" (c12), "=3Dr" (c13), "=3Dr" (c14), "=3Dr" (c15), \ "=3Dr" (c16), "=3Dr" (c17) \ : PASTE(__constraint_read_, \ - __count_args(__VA_ARGS__)) \ + count_args(__VA_ARGS__)) \ : "memory" ); \ - if ( ___res ) \ - *___res =3D (struct arm_smccc_res){ r0, r1, r2, r3 }; \ - } while ( 0 ) + (struct arm_smccc_res){ r0, r1, r2, r3 }; \ + }) =20 #define arm_smccc_1_1_smc(...) arm_smccc_smc(__VA_ARGS__) =20 @@ -271,8 +262,8 @@ static inline void arm_smccc_guest_smc(struct cpu_user_= regs *regs) { struct arm_smccc_res res; =20 - arm_smccc_1_1_smc(regs->x0, regs->x1, regs->x2, regs->x3, - regs->x4, regs->x5, regs->x6, regs->x7, &res); + res =3D arm_smccc_1_1_smc(regs->x0, regs->x1, regs->x2, regs->x3, + regs->x4, regs->x5, regs->x6, regs->x7); =20 regs->x0 =3D res.a0; regs->x1 =3D res.a1; diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exyn= os5.c index f7c09520675e..f08d50c1fe38 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -249,7 +249,7 @@ static int exynos5_cpu_up(int cpu) iounmap(power); =20 if ( secure_firmware ) - arm_smccc_smc(SMC_CMD_CPU1BOOT, cpu, NULL); + arm_smccc_smc(SMC_CMD_CPU1BOOT, cpu); =20 return cpu_up_send_sgi(cpu); } diff --git a/xen/arch/arm/platforms/seattle.c b/xen/arch/arm/platforms/seat= tle.c index 64cc1868c24b..dfa5cf4265c0 100644 --- a/xen/arch/arm/platforms/seattle.c +++ b/xen/arch/arm/platforms/seattle.c @@ -33,12 +33,12 @@ static const char * const seattle_dt_compat[] __initcon= st =3D */ static void seattle_system_reset(void) { - arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET, NULL); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET); } =20 static void seattle_system_off(void) { - arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF, NULL); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF); } =20 PLATFORM_START(seattle, "SEATTLE") diff --git a/xen/arch/arm/psci.c b/xen/arch/arm/psci.c index b6860a776031..634d0d7467cf 100644 --- a/xen/arch/arm/psci.c +++ b/xen/arch/arm/psci.c @@ -41,8 +41,8 @@ int call_psci_cpu_on(int cpu) { struct arm_smccc_res res; =20 - arm_smccc_smc(psci_cpu_on_nr, cpu_logical_map(cpu), __pa(init_secondar= y), - &res); + res =3D arm_smccc_smc(psci_cpu_on_nr, cpu_logical_map(cpu), + __pa(init_secondary)); =20 return PSCI_RET(res); } @@ -54,7 +54,7 @@ void call_psci_cpu_off(void) struct arm_smccc_res res; =20 /* If successfull the PSCI cpu_off call doesn't return */ - arm_smccc_smc(PSCI_0_2_FN32_CPU_OFF, &res); + res =3D arm_smccc_smc(PSCI_0_2_FN32_CPU_OFF); panic("PSCI cpu off failed for CPU%d err=3D%d\n", smp_processor_id= (), PSCI_RET(res)); } @@ -63,13 +63,13 @@ void call_psci_cpu_off(void) void call_psci_system_off(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF, NULL); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_OFF); } =20 void call_psci_system_reset(void) { if ( psci_ver > PSCI_VERSION(0, 1) ) - arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET, NULL); + arm_smccc_smc(PSCI_0_2_FN32_SYSTEM_RESET); } =20 static int __init psci_features(uint32_t psci_func_id) @@ -79,7 +79,7 @@ static int __init psci_features(uint32_t psci_func_id) if ( psci_ver < PSCI_VERSION(1, 0) ) return PSCI_NOT_SUPPORTED; =20 - arm_smccc_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id, &res); + res =3D arm_smccc_smc(PSCI_1_0_FN32_PSCI_FEATURES, psci_func_id); =20 return PSCI_RET(res); } @@ -116,9 +116,8 @@ static void __init psci_init_smccc(void) =20 if ( psci_features(ARM_SMCCC_VERSION_FID) !=3D PSCI_NOT_SUPPORTED ) { - struct arm_smccc_res res; + struct arm_smccc_res res =3D arm_smccc_smc(ARM_SMCCC_VERSION_FID); =20 - arm_smccc_smc(ARM_SMCCC_VERSION_FID, &res); if ( PSCI_RET(res) !=3D ARM_SMCCC_NOT_SUPPORTED ) smccc_ver =3D PSCI_RET(res); } @@ -191,7 +190,7 @@ static int __init psci_init_0_2(void) } } =20 - arm_smccc_smc(PSCI_0_2_FN32_PSCI_VERSION, &res); + res =3D arm_smccc_smc(PSCI_0_2_FN32_PSCI_VERSION); psci_ver =3D PSCI_RET(res); =20 /* For the moment, we only support PSCI 0.2 and PSCI 1.x */ diff --git a/xen/arch/arm/tee/optee.c b/xen/arch/arm/tee/optee.c index 3d2633237074..e38223d49801 100644 --- a/xen/arch/arm/tee/optee.c +++ b/xen/arch/arm/tee/optee.c @@ -178,7 +178,7 @@ static bool optee_probe(void) return false; =20 /* Check UID */ - arm_smccc_smc(ARM_SMCCC_CALL_UID_FID(TRUSTED_OS_END), &resp); + resp =3D arm_smccc_smc(ARM_SMCCC_CALL_UID_FID(TRUSTED_OS_END)); =20 if ( (uint32_t)resp.a0 !=3D OPTEE_MSG_UID_0 || (uint32_t)resp.a1 !=3D OPTEE_MSG_UID_1 || @@ -209,7 +209,7 @@ static bool optee_probe(void) * call. It will return OPTEE_SMC_RETURN_UNKNOWN_FUNCTION if * OP-TEE have no virtualization support enabled. */ - arm_smccc_smc(OPTEE_SMC_VM_DESTROYED, 0, 0, 0, 0, 0, 0, 0, &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_VM_DESTROYED, 0, 0, 0, 0, 0, 0, 0); if ( resp.a0 =3D=3D OPTEE_SMC_RETURN_UNKNOWN_FUNCTION ) return false; =20 @@ -243,8 +243,8 @@ static int optee_domain_init(struct domain *d) * * a7 should be 0, so we can't skip last 6 parameters of arm_smccc_smc= () */ - arm_smccc_smc(OPTEE_SMC_VM_CREATED, OPTEE_CLIENT_ID(d), 0, 0, 0, 0, 0,= 0, - &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_VM_CREATED, OPTEE_CLIENT_ID(d), + 0, 0, 0, 0, 0, 0); if ( resp.a0 !=3D OPTEE_SMC_RETURN_OK ) { printk(XENLOG_WARNING "%pd: Unable to create OPTEE client: rc =3D = 0x%X\n", @@ -681,8 +681,8 @@ static int optee_relinquish_resources(struct domain *d) * * a7 should be 0, so we can't skip last 6 parameters of arm_smccc_smc= () */ - arm_smccc_smc(OPTEE_SMC_VM_DESTROYED, OPTEE_CLIENT_ID(d), 0, 0, 0, 0, = 0, 0, - &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_VM_DESTROYED, OPTEE_CLIENT_ID(d), + 0, 0, 0, 0, 0, 0); =20 ASSERT(!spin_is_locked(&ctx->lock)); ASSERT(!atomic_read(&ctx->call_count)); @@ -1171,15 +1171,14 @@ static void do_call_with_arg(struct optee_domain *c= tx, { struct arm_smccc_res res; =20 - arm_smccc_smc(a0, a1, a2, a3, a4, a5, 0, OPTEE_CLIENT_ID(current->doma= in), - &res); + res =3D arm_smccc_smc(a0, a1, a2, a3, a4, a5, 0, OPTEE_CLIENT_ID(curre= nt->domain)); =20 if ( OPTEE_SMC_RETURN_IS_RPC(res.a0) ) { while ( handle_rpc_return(ctx, &res, regs, call) =3D=3D -ERESTART= ) { - arm_smccc_smc(res.a0, res.a1, res.a2, res.a3, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &res); + res =3D arm_smccc_smc(res.a0, res.a1, res.a2, res.a3, 0, 0, 0, + OPTEE_CLIENT_ID(current->domain)); =20 if ( !OPTEE_SMC_RETURN_IS_RPC(res.a0) ) break; @@ -1619,8 +1618,8 @@ static void handle_exchange_capabilities(struct cpu_u= ser_regs *regs) caps =3D get_user_reg(regs, 1); caps &=3D OPTEE_KNOWN_NSEC_CAPS; =20 - arm_smccc_smc(OPTEE_SMC_EXCHANGE_CAPABILITIES, caps, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_EXCHANGE_CAPABILITIES, caps, 0, 0, 0,= 0, 0, + OPTEE_CLIENT_ID(current->domain)); if ( resp.a0 !=3D OPTEE_SMC_RETURN_OK ) { set_user_reg(regs, 0, resp.a0); return; @@ -1664,8 +1663,8 @@ static bool optee_handle_call(struct cpu_user_regs *r= egs) return true; =20 case OPTEE_SMC_CALLS_UID: - arm_smccc_smc(OPTEE_SMC_CALLS_UID, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_CALLS_UID, 0, 0, 0, 0, 0, 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); set_user_reg(regs, 1, resp.a1); set_user_reg(regs, 2, resp.a2); @@ -1673,15 +1672,15 @@ static bool optee_handle_call(struct cpu_user_regs = *regs) return true; =20 case OPTEE_SMC_CALLS_REVISION: - arm_smccc_smc(OPTEE_SMC_CALLS_REVISION, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_CALLS_REVISION, 0, 0, 0, 0, 0, 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); set_user_reg(regs, 1, resp.a1); return true; =20 case OPTEE_SMC_CALL_GET_OS_UUID: - arm_smccc_smc(OPTEE_SMC_CALL_GET_OS_UUID, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain),&resp); + resp =3D arm_smccc_smc(OPTEE_SMC_CALL_GET_OS_UUID, 0, 0, 0, 0, 0, = 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); set_user_reg(regs, 1, resp.a1); set_user_reg(regs, 2, resp.a2); @@ -1689,21 +1688,21 @@ static bool optee_handle_call(struct cpu_user_regs = *regs) return true; =20 case OPTEE_SMC_CALL_GET_OS_REVISION: - arm_smccc_smc(OPTEE_SMC_CALL_GET_OS_REVISION, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_CALL_GET_OS_REVISION, 0, 0, 0, 0,= 0, 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); set_user_reg(regs, 1, resp.a1); return true; =20 case OPTEE_SMC_ENABLE_SHM_CACHE: - arm_smccc_smc(OPTEE_SMC_ENABLE_SHM_CACHE, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_ENABLE_SHM_CACHE, 0, 0, 0, 0, 0, = 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); return true; =20 case OPTEE_SMC_DISABLE_SHM_CACHE: - arm_smccc_smc(OPTEE_SMC_DISABLE_SHM_CACHE, 0, 0, 0, 0, 0, 0, - OPTEE_CLIENT_ID(current->domain), &resp); + resp =3D arm_smccc_smc(OPTEE_SMC_DISABLE_SHM_CACHE, 0, 0, 0, 0, 0,= 0, + OPTEE_CLIENT_ID(current->domain)); set_user_reg(regs, 0, resp.a0); if ( resp.a0 =3D=3D OPTEE_SMC_RETURN_OK ) { free_shm_rpc(ctx, regpair_to_uint64(resp.a1, resp.a2)); diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 625d229396bb..6a5dcef2aa87 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1991,7 +1991,7 @@ void asmlinkage enter_hypervisor_from_guest_preirq(vo= id) =20 /* If the guest has disabled the workaround, bring it back on. */ if ( needs_ssbd_flip(v) ) - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 1); } =20 /* @@ -2334,7 +2334,7 @@ void asmlinkage leave_hypervisor_to_guest(void) * If the guest wants it disabled, so be it... */ if ( needs_ssbd_flip(current) ) - arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0, NULL); + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_2_FID, 0); } =20 /* --=20 2.39.5