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[125.227.154.99]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3954d2de41dsm6247737a91.5.2026.08.18.08.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2026 08:40:16 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787067618; x=1787672418; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=qIBzYOD0MBsGKdeHT2126j/ybS3L8h3qOs9csVaO/Z0=; b=Qbl1HeTYz5doLhXBg2Fjwj38ys/m6aHNM9YRwluNaD4MCOWo6PyLPXC791A+gR2WQ7 YoxXckjp0Aa5+8Y0iA5HpDLxKiU6we/Iuc8GWZg8xcSFy4tn/1G32kv9CfKx8HWNC+pa ePTX1TRn3u6pJTSLdDXL4MPef2oo0CIkxo/4Sy/ugaXnWzds/FOk6EXkqEX4Wc9rKnNu xdfWz7+VMoAT+/6sInNHe+80yGRSGYMslF5FewSuHINbWZlmfwzFN4i5zfDBrjp01qXX DOX5Hi7YtU1XXN6xOJGw+wCsi5FVC6gnrJXklb9akH9SZ6cutEX2pdFS406gVjYDTttQ sKPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787067618; x=1787672418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=qIBzYOD0MBsGKdeHT2126j/ybS3L8h3qOs9csVaO/Z0=; b=E8+0BM/GxdSXq4B2BV2K/IPrYR7JvKI0bDWBWdX+W8lvTRCgmWN8fpSCQpOzrol7sI izQRDeZJz9yoiISExNgM3YuB6GgnhsIHNPkQxKP+N7PviZLK/tpFk3rMaMm6h3UDngcw s8ZZSS5qZlpTb8ONPiwpSOkLfY5LwCwaOLikxkqGmKnbL85UFo39tGLODCKgpPZPF2T1 bZLpfLuLv/aiyRX4x4iwkN7v8+QhKUdrshbXGRl0C/bzvmJ0zB5lcmY6iySA+Sjrc/SF 8v1XzB3UEEKMqp/mW0KozbSXtIMCAA7jR4gMtO79XK7OkCgBERYdKic4/6RFTMRKU8GQ 7wEw== X-Gm-Message-State: AOJu0YxHAMtX9wNy6WRScsVj5PcXCKJQiJ2c0ods0LU2YMaTZiVFyfuD Guot0YrtLSFoDMTVF8cLV4Rz0Lg2OLJsn43+uTeDFjWMFaz62P5ptBbqaP5d6qRb X-Gm-Gg: AR+sD12r0bGirbkkLv6avB2GhZHhhVjKgVNvYNcxJ91f+kPq9Umr3vDmMxJOMcAeLvc FuQbeSNMaa4iy7lplb1gkkqTdM+9y1j+n06pJzo2tyiN2PO9hqym/FkJQ83vLZsNzI+bkP2i3eE HyxASwZk9AHWRKlPucycwdLvXr+iMwLoUkNWf3awmZ+qbVJc9dkWeGNxE2JbeivEWESya8TmCKf W+bxPnmWNvba8sEAmbi9q0JRrYu3YXbu19vHz+D5erdibpqKBZ4kpp9AB/3Prjc/ECdiOQCDQKJ n3uQ1aJiSCPaJEQ6+zKQwW+d4y6utW9CD6BjY9v/3O2UPi7lziIFWNOu1ZFd+HFn9rCUwczXKLQ oTDjKORcime61Tbtw7HAQGCdAuHXT2q2vG6Yfnahh6CJjFOaVAMXO8V4zxosC/HQWrOLQ9kF85s 27OmWvAeY3wYwaoArFCNrIADY49ETFeiLah3CAMv3mtAzf2ivtI/k4JG57PpLDemTMMP1O7cUZf U1U98R9E3DZtKn97/R/pyCg6WNxbXsR X-Received: by 2002:a17:90a:6089:b0:395:4de4:92c7 with SMTP id 98e67ed59e1d1-3954de49a5fmr10840161a91.3.1787067617869; Tue, 18 Aug 2026 08:40:17 -0700 (PDT) From: Wig Cheng To: xen-devel@lists.xenproject.org Cc: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , John Ernberg , Peng Fan , Wig Cheng Subject: [PATCH v3 1/4] xen/char: add classic i.MX UART driver Date: Tue, 18 Aug 2026 23:39:43 +0800 Message-ID: <20260818153946.1635464-2-onlywig@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260818153946.1635464-1-onlywig@gmail.com> References: <20260818153946.1635464-1-onlywig@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1787067620-F7ABF2A1-F9429C21/0/0 X-purgate-type: clean X-purgate-size: 11658 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787067638967158500 Content-Type: text/plain; charset="utf-8" Add a console driver for the classic i.MX UART IP ("fsl,imx6q-uart" compatible), used as the console UART on the i.MX8M family. Baudrate and pin configuration are inherited from the bootloader; the driver only enables the transmitter/receiver and wires up the RX/TX interrupts, mirroring the existing imx-lpuart driver. The i.MX8M family's UART IP differs from the LPUART used on i.MX8QM/8QXP, so a separate driver is needed. Signed-off-by: Wig Cheng Reviewed-by: Michal Orzel --- Changes in v3: - Add imx-uart.c to the Arm MAINTAINERS section so it falls under Arm maintainership. - Gate serial_tx_interrupt() on TRDYEN: USR1_TRDY is a raw status bit, set independently of whether the TX interrupt is enabled. - Print the IRQ number with %u (it is unsigned). MAINTAINERS | 1 + xen/arch/arm/include/asm/imx-uart.h | 57 +++++++ xen/drivers/char/Kconfig | 8 + xen/drivers/char/Makefile | 1 + xen/drivers/char/imx-uart.c | 233 ++++++++++++++++++++++++++++ 5 files changed, 300 insertions(+) create mode 100644 xen/arch/arm/include/asm/imx-uart.h create mode 100644 xen/drivers/char/imx-uart.c diff --git a/MAINTAINERS b/MAINTAINERS index ed0ffa608f..4dd97ffcad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -269,6 +269,7 @@ F: xen/arch/arm/ F: xen/drivers/char/cadence-uart.c F: xen/drivers/char/exynos4210-uart.c F: xen/drivers/char/imx-lpuart.c +F: xen/drivers/char/imx-uart.c F: xen/drivers/char/meson-uart.c F: xen/drivers/char/mvebu-uart.c F: xen/drivers/char/omap-uart.c diff --git a/xen/arch/arm/include/asm/imx-uart.h b/xen/arch/arm/include/asm= /imx-uart.h new file mode 100644 index 0000000000..a3892020e6 --- /dev/null +++ b/xen/arch/arm/include/asm/imx-uart.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Register definitions for the classic i.MX UART IP + * ("fsl,imx6q-uart" compatible), used as the console UART on the + * i.MX8M family. + * + * Register layout taken from Linux drivers/tty/serial/imx.c. + * + * Copyright 2026 Open-EP (E-Paper) Community + */ + +#ifndef ASM_IMX_UART_H +#define ASM_IMX_UART_H + +#include + +#define URXD0 0x00 /* Receiver Register */ +#define URTX0 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UTS 0xb4 /* Test Register */ + +#define URXD_RX_DATA 0xff + +#define UCR1_UARTEN BIT(0, U) /* UART enable */ +#define UCR1_ATDMAEN BIT(2, U) /* Aging DMA timer enable */ +#define UCR1_TXDMAEN BIT(3, U) /* Transmitter ready DMA enable */ +#define UCR1_TXMPTYEN BIT(6, U) /* Transmitter empty interrupt enable = */ +#define UCR1_RXDMAEN BIT(8, U) /* Receiver ready DMA enable */ +#define UCR1_RRDYEN BIT(9, U) /* Receiver ready interrupt enable */ +#define UCR1_TRDYEN BIT(13, U) /* Transmitter ready interrupt enable = */ + +#define UCR2_SRST BIT(0, U) /* 0 =3D issue software reset */ +#define UCR2_RXEN BIT(1, U) /* Receiver enable */ +#define UCR2_TXEN BIT(2, U) /* Transmitter enable */ + +#define USR1_TRDY BIT(13, U) /* Transmitter ready */ + +#define USR2_RDR BIT(0, U) /* Receive data ready */ +#define USR2_ORE BIT(1, U) /* Overrun error */ + +#define UTS_TXFULL BIT(4, U) /* TX FIFO full */ +#define UTS_RXEMPTY BIT(5, U) /* RX FIFO empty */ +#define UTS_TXEMPTY BIT(6, U) /* TX FIFO empty */ + +#endif /* ASM_IMX_UART_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index 8e49a52c73..f237c0220d 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -30,6 +30,14 @@ config HAS_IMX_LPUART help This selects the i.MX LPUART. If you have i.MX8QM based board, say Y. =20 +config HAS_IMX_UART + bool "i.MX UART driver" + default y + depends on ARM_64 + help + This selects the classic i.MX UART. If you have an i.MX8M family + based board, say Y. + config HAS_MVEBU bool "Marvell MVEBU UART driver" default y diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile index 8cbbffdca8..039f566926 100644 --- a/xen/drivers/char/Makefile +++ b/xen/drivers/char/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_HAS_SCIF) +=3D scif-uart.o obj-$(CONFIG_HAS_EHCI) +=3D ehci-dbgp.o obj-$(CONFIG_XHCI) +=3D xhci-dbc.o obj-$(CONFIG_HAS_IMX_LPUART) +=3D imx-lpuart.o +obj-$(CONFIG_HAS_IMX_UART) +=3D imx-uart.o obj-$(CONFIG_HAS_LINFLEX) +=3D linflex-uart.o obj-$(CONFIG_GENERIC_UART_INIT) +=3D uart-init.o obj-y +=3D serial.o diff --git a/xen/drivers/char/imx-uart.c b/xen/drivers/char/imx-uart.c new file mode 100644 index 0000000000..2dc531a84e --- /dev/null +++ b/xen/drivers/char/imx-uart.c @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Driver for the classic i.MX UART IP ("fsl,imx6q-uart"), used as the + * console UART on the i.MX8M family (e.g. i.MX8MP). + * + * Baudrate and pin configuration are inherited from the bootloader. + * + * Copyright 2026 Open-EP (E-Paper) Community + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define imx_uart_read(uart, off) readl((uart)->regs + (off)) +#define imx_uart_write(uart, off, val) writel((val), (uart)->regs + (off)) + +static struct imx_uart { + uint32_t irq; + char __iomem *regs; + struct irqaction irqaction; + struct vuart_info vuart; +} imx8m_com; + +static void imx_uart_interrupt(int irq, void *data) +{ + struct serial_port *port =3D data; + struct imx_uart *uart =3D port->uart; + + if ( imx_uart_read(uart, USR2) & USR2_RDR ) + serial_rx_interrupt(port); + + /* + * USR1_TRDY is a raw status bit, set whenever the transmitter has + * room regardless of whether the TX interrupt is enabled. Only treat + * it as a TX interrupt when TRDYEN is set, otherwise an RX-only + * interrupt would spuriously enter serial_tx_interrupt(). + */ + if ( (imx_uart_read(uart, USR1) & USR1_TRDY) && + (imx_uart_read(uart, UCR1) & UCR1_TRDYEN) ) + serial_tx_interrupt(port); +} + +static void __init imx_uart_init_preirq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t ucr1, ucr2; + + /* + * Reuse the bootloader settings; only enable the UART and both + * directions. The console uses UCR1 interrupts (RRDYEN/TRDYEN) + * exclusively, so just clear UCR1's interrupt and DMA enables. + */ + ucr1 =3D imx_uart_read(uart, UCR1); + ucr1 &=3D ~(UCR1_RRDYEN | UCR1_TRDYEN | UCR1_TXMPTYEN | UCR1_RXDMAEN | + UCR1_TXDMAEN | UCR1_ATDMAEN); + ucr1 |=3D UCR1_UARTEN; + imx_uart_write(uart, UCR1, ucr1); + + ucr2 =3D imx_uart_read(uart, UCR2); + ucr2 |=3D UCR2_SRST | UCR2_RXEN | UCR2_TXEN; + imx_uart_write(uart, UCR2, ucr2); +} + +static void __init imx_uart_init_postirq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t ucr1; + + uart->irqaction.handler =3D imx_uart_interrupt; + uart->irqaction.name =3D "imx_uart"; + uart->irqaction.dev_id =3D port; + + if ( setup_irq(uart->irq, 0, &uart->irqaction) !=3D 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocate imx_uart IRQ %u\n", uart->= irq); + return; + } + + /* Enable the receiver ready interrupt */ + ucr1 =3D imx_uart_read(uart, UCR1); + ucr1 |=3D UCR1_RRDYEN; + imx_uart_write(uart, UCR1, ucr1); +} + +static int imx_uart_tx_ready(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + + return !(imx_uart_read(uart, UTS) & UTS_TXFULL); +} + +static void imx_uart_putc(struct serial_port *port, char c) +{ + struct imx_uart *uart =3D port->uart; + + while ( imx_uart_read(uart, UTS) & UTS_TXFULL ) + cpu_relax(); + + imx_uart_write(uart, URTX0, c); +} + +static int imx_uart_getc(struct serial_port *port, char *pc) +{ + struct imx_uart *uart =3D port->uart; + + if ( !(imx_uart_read(uart, USR2) & USR2_RDR) ) + return 0; + + *pc =3D imx_uart_read(uart, URXD0) & URXD_RX_DATA; + + if ( imx_uart_read(uart, USR2) & USR2_ORE ) + imx_uart_write(uart, USR2, USR2_ORE); + + return 1; +} + +static int __init imx_uart_irq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + + return ((uart->irq > 0) ? uart->irq : -1); +} + +static const struct vuart_info *imx_uart_vuart_info(struct serial_port *po= rt) +{ + struct imx_uart *uart =3D port->uart; + + return &uart->vuart; +} + +static void imx_uart_start_tx(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t ucr1; + + ucr1 =3D imx_uart_read(uart, UCR1); + imx_uart_write(uart, UCR1, ucr1 | UCR1_TRDYEN); +} + +static void imx_uart_stop_tx(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t ucr1; + + ucr1 =3D imx_uart_read(uart, UCR1); + imx_uart_write(uart, UCR1, ucr1 & ~UCR1_TRDYEN); +} + +static struct uart_driver __read_mostly imx_uart_driver =3D { + .init_preirq =3D imx_uart_init_preirq, + .init_postirq =3D imx_uart_init_postirq, + .tx_ready =3D imx_uart_tx_ready, + .putc =3D imx_uart_putc, + .getc =3D imx_uart_getc, + .irq =3D imx_uart_irq, + .start_tx =3D imx_uart_start_tx, + .stop_tx =3D imx_uart_stop_tx, + .vuart_info =3D imx_uart_vuart_info, +}; + +static int __init imx_uart_init(struct dt_device_node *dev, const void *da= ta) +{ + const char *config =3D data; + struct imx_uart *uart; + int res; + paddr_t addr, size; + + if ( strcmp(config, "") ) + printk("WARNING: UART configuration is not supported\n"); + + uart =3D &imx8m_com; + + res =3D dt_device_get_paddr(dev, 0, &addr, &size); + if ( res ) + { + printk("imx-uart: Unable to retrieve the base address of the UART\= n"); + return res; + } + + res =3D platform_get_irq(dev, 0); + if ( res < 0 ) + { + printk("imx-uart: Unable to retrieve the IRQ\n"); + return -EINVAL; + } + uart->irq =3D res; + + uart->regs =3D ioremap_nocache(addr, size); + if ( !uart->regs ) + { + printk("imx-uart: Unable to map the UART memory\n"); + return -ENOMEM; + } + + uart->vuart.base_addr =3D addr; + uart->vuart.size =3D size; + uart->vuart.data_off =3D URTX0; + uart->vuart.status_off =3D UTS; + uart->vuart.status =3D UTS_TXEMPTY | UTS_RXEMPTY; + + /* Register with generic serial driver */ + serial_register_uart(SERHND_DTUART, &imx_uart_driver, uart); + + dt_device_set_used_by(dev, DOMID_XEN); + + return 0; +} + +static const struct dt_device_match imx_uart_dt_compat[] __initconst =3D +{ + DT_MATCH_COMPATIBLE("fsl,imx6q-uart"), + { /* sentinel */ }, +}; + +DT_DEVICE_START(imx_uart, "i.MX UART", DEVICE_SERIAL) + .dt_match =3D imx_uart_dt_compat, + .init =3D imx_uart_init, +DT_DEVICE_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.43.0 From nobody Thu Sep 24 20:50:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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The UART is expected to be fully initialized by the bootloader. Signed-off-by: Wig Cheng Reviewed-by: Michal Orzel --- Changes in v3: - No code changes; picked up Michal's Reviewed-by. xen/arch/arm/Kconfig.debug | 12 +++++++++ xen/arch/arm/arm64/debug-imx-uart.inc | 37 +++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 xen/arch/arm/arm64/debug-imx-uart.inc diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index 5a03b220ac..63a34b813a 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -44,6 +44,14 @@ choice Say Y here if you wish the early printk to direct their output to a i.MX LPUART. =20 + config EARLY_UART_CHOICE_IMX_UART + select EARLY_UART_IMX_UART + depends on ARM_64 + bool "Early printk via i.MX UART" + help + Say Y here if you wish the early printk to direct their + output to the classic i.MX UART (i.MX8M family). + config EARLY_UART_CHOICE_LINFLEX select EARLY_UART_LINFLEX depends on ARM_64 @@ -97,6 +105,9 @@ config EARLY_UART_EXYNOS4210 config EARLY_UART_IMX_LPUART select EARLY_PRINTK bool +config EARLY_UART_IMX_UART + select EARLY_PRINTK + bool config EARLY_UART_LINFLEX select EARLY_PRINTK bool @@ -185,6 +196,7 @@ config EARLY_PRINTK_INC default "debug-cadence.inc" if EARLY_UART_CADENCE default "debug-exynos4210.inc" if EARLY_UART_EXYNOS4210 default "debug-imx-lpuart.inc" if EARLY_UART_IMX_LPUART + default "debug-imx-uart.inc" if EARLY_UART_IMX_UART default "debug-linflex.inc" if EARLY_UART_LINFLEX default "debug-meson.inc" if EARLY_UART_MESON default "debug-mvebu.inc" if EARLY_UART_MVEBU diff --git a/xen/arch/arm/arm64/debug-imx-uart.inc b/xen/arch/arm/arm64/deb= ug-imx-uart.inc new file mode 100644 index 0000000000..19b1679020 --- /dev/null +++ b/xen/arch/arm/arm64/debug-imx-uart.inc @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Early printk for the classic i.MX UART IP (i.MX8M family). + * The UART is expected to be fully initialized by the bootloader. + * + * Copyright 2026 Open-EP (E-Paper) Community + */ + +#include + +/* + * Wait for the UART to be ready to transmit + * xb: register which contains the UART base address + * c: scratch register + */ +.macro early_uart_ready xb, c +1: + ldr w\c, [\xb, #UTS] /* <- Test register */ + tst w\c, #UTS_TXFULL /* Check TX FIFO full bit */ + b.ne 1b /* Wait until there is room */ +.endm + +/* + * UART transmit character + * xb: register which contains the UART base address + * wt: register which contains the character to transmit + */ +.macro early_uart_transmit xb, wt + str \wt, [\xb, #URTX0] /* -> Transmitter register */ +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ --=20 2.43.0 From nobody Thu Sep 24 20:50:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[125.227.154.99]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3954d2de41dsm6247737a91.5.2026.08.18.08.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2026 08:40:24 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787067626; x=1787672426; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=M9gYmqB9sm85nt1WIzPntBQ829u0LTMSjCyLS2s6yWc=; b=dR2SSz3uPUK3epUlw4KJb0txon1RPqOlQUxOV94V0pu+SPsMRYYZsWHeB2RcYIeOJl OarhFesP8EIvV0D2uK5nABveVpEO5wbzicaraEMwXP54O4DfqNFqzk6JqfIcgFPMdB1Q w9pG2HLJ6f9eR9wrJmxjIbpB+UbAvuXnZGbUZkDldL3KaKsngd4MU6I1Mnfe+E/KIxQv N8/g4dyq/266eM8UTsIsqQTCrImsTvTQsahSd5gTBQ/yeCwRgLpvXzLUpv4lPir7gJ0n gneUQsDjJZE7QUPnB+qJZITQS5LslBpVybeE7SzT71GwT645OlAfqhpzVgqqoMMHH0J2 R0gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787067626; x=1787672426; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=M9gYmqB9sm85nt1WIzPntBQ829u0LTMSjCyLS2s6yWc=; b=I0Ri7HXebCxlAkQaJ6XxdUU5aiv+y2leuy9s+XAV9H9fQRLK3+Cp3N/DpyRlVMzgEw 6YowfrqlditWrGDFIyRkeO0GUb6q00JJtf4mYdHeUvjIUhgOiQin4+L2aNu2M3t+7RaV RIyRQbuMuci4tnjAijr3Te8kT89LY4DDzfk+i9LbsvTBrjpT+9i0OISBgPN2LgbWynIS 4OHFfncXrTwrTNTNy7mXFeGIddwVBw7iAZbN8Vce3jQfczzwk2xz73Q+bvxZhUFeLXgY bxCqjDBMLr0AtpLtN+pWd2mGCL0jYhpvDYlx2yA8cisyCY5B8K0c3dlQOtO6m6qZzB3j Frig== X-Gm-Message-State: AOJu0YxgreaHsqxw4TN7MmyvFMzi/mvCK0GAXxV45ocWo/C5vlfTM7LS Bwf3GK1tJBlB6kPvGK7a+jFoiffYT+jntzJW4Kbn9inZc3yAEMMxl4rPYaomdZdc X-Gm-Gg: AR+sD13E61YbFfM8rkpASrknx9yxniQHeWwvgR1Q0oBubOAqEccQSl8tX43liCaX707 tS1VxExfb6Y4OhYK1nBl7vzM1EyEYHZSi4rtQNL81u0Lp14Li2LdSWpq+8x/AQr7NNZjbc6iEE1 9U9W3BMxvEGkxhhGKl/MHvmJL2Ke3yNagCRLYYT0WqHofHyt753OITq2RyVqDanUcLuoyjthXkn uGZM7M7/Xr5Z55VcrqYsnhGF6mNX5fsBfW4pjZG3tKZt1dA0gNh7+XBICQpAOkYNlb+9isbVtw6 v8l9iC+8v3cCWktSlJOD4q1w/IT21NCNDaeVJ+w6tLXVo2MCkttHlGkVKus3q0XBWZE6O/056dF ByTTz7xB1iWNCCTyQfeIm06akfBp7KZ1JXk73uuik0vwYnCr326yCwlQHZfNKz1p4ucNpyDBQBI pD8ImkzDEWMV7pJ8dpUF0ZMXPF5KvIEtsC5WitYNDHWAaY4SNAD873LfvTU36GaBaaVsVpKv6VF 8ICoIwNpaibm0mD+8lD/gHGMsvrvXk4jxkmdkN1JsU= X-Received: by 2002:a17:90b:5707:b0:38f:5801:dc0e with SMTP id 98e67ed59e1d1-3933e61bee2mr39142719a91.15.1787067625672; Tue, 18 Aug 2026 08:40:25 -0700 (PDT) From: Wig Cheng To: xen-devel@lists.xenproject.org Cc: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , John Ernberg , Peng Fan , Wig Cheng Subject: [PATCH v3 3/4] xen/arm: add i.MX8M platform support Date: Tue, 18 Aug 2026 23:39:45 +0800 Message-ID: <20260818153946.1635464-4-onlywig@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260818153946.1635464-1-onlywig@gmail.com> References: <20260818153946.1635464-1-onlywig@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ebf023/1787067627-510DDB50-329D83F9/0/0 X-purgate-type: clean X-purgate-size: 6665 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787067647099158500 Content-Type: text/plain; charset="utf-8" Add platform glue for the NXP i.MX8M family (i.MX8MP/MQ/MM/MN). When Linux is used as dom0 a number of drivers make SiP SMC calls into TF-A to manage hardware: GPC power domains, SRC (M-core remoteproc), SoC info and NoC QoS. There is no public specification for these calls; the function IDs and their subfunctions are taken from the vendor kernel call sites. Forward only the specific subfunctions the hardware domain issues, following the whitelist model of the i.MX8QM platform. Where a service has a fixed set of subfunctions (GPC, SRC, NoC) they are filtered, and the SoC info call is a read-only query. CPU and DRAM frequency scaling are denied because the hardware domain cannot make an informed decision about resources shared with the other domains, and any unknown function ID is rejected. Signed-off-by: Wig Cheng Reviewed-by: Michal Orzel --- Changes in v3: - Include for get/set_user_reg(). - Add a description for the CPUFREQ function id. - Drop the unused SRC M4_START and NoC LCDIF subfunction macros. - Order the switch cases by function id. - Deny DDR DVFS as well, for the same reason CPU frequency scaling is denied: the hardware domain cannot make an informed decision about DRAM shared with the other domains. Previously it was forwarded. - Return false directly on a denied subfunction instead of goto plus a redundant printk (vsmccc_handle_call() already logs the rejection). xen/arch/arm/platforms/Makefile | 1 + xen/arch/arm/platforms/imx8m.c | 139 ++++++++++++++++++++++++++++++++ 2 files changed, 140 insertions(+) create mode 100644 xen/arch/arm/platforms/imx8m.c diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makef= ile index bec6e55d1f..cdf936c50d 100644 --- a/xen/arch/arm/platforms/Makefile +++ b/xen/arch/arm/platforms/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_ALL_PLAT) +=3D sunxi.o obj-$(CONFIG_ALL64_PLAT) +=3D thunderx.o obj-$(CONFIG_ALL64_PLAT) +=3D xgene-storm.o obj-$(CONFIG_ALL64_PLAT) +=3D brcm-raspberry-pi.o +obj-$(CONFIG_ALL64_PLAT) +=3D imx8m.o obj-$(CONFIG_ALL64_PLAT) +=3D imx8qm.o obj-$(CONFIG_MPSOC_PLATFORM) +=3D xilinx-zynqmp.o obj-$(CONFIG_MPSOC_PLATFORM) +=3D xilinx-zynqmp-eemi.o diff --git a/xen/arch/arm/platforms/imx8m.c b/xen/arch/arm/platforms/imx8m.c new file mode 100644 index 0000000000..0aceed9d43 --- /dev/null +++ b/xen/arch/arm/platforms/imx8m.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * i.MX 8M family setup + * + * Copyright 2026 Open-EP (E-Paper) Community + */ + +#include +#include +#include +#include + +static const char * const imx8m_dt_compat[] __initconst =3D +{ + "fsl,imx8mp", + "fsl,imx8mq", + "fsl,imx8mm", + "fsl,imx8mn", + NULL +}; + +#define IMX_SIP_FID(fid) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_64, \ + ARM_SMCCC_OWNER_SIP, \ + (fid)) + +/* + * SiP SMC function IDs used by the i.MX8M Linux drivers. There is no + * public specification for these; the IDs and their subfunctions are + * extracted from the vendor kernel call sites (see drivers/soc/imx, + * drivers/devfreq, drivers/remoteproc). + */ +#define IMX_SIP_F_GPC 0x0 /* GPC power-domain control */ +#define IMX_SIP_F_CPUFREQ 0x1 /* CPU frequency scaling */ +#define IMX_SIP_F_DDR_DVFS 0x4 /* DRAM frequency scaling */ +#define IMX_SIP_F_SRC 0x5 /* SRC: M-core remoteproc start/stop */ +#define IMX_SIP_F_SOC_INFO 0x6 /* read-only SoC info query */ +#define IMX_SIP_F_NOC 0x8 /* NoC QoS priority setup */ + +#define IMX_SIP_GPC_SF_PM_DOMAIN 0x03 + +#define IMX_SIP_SRC_SF_M4_STOP 0x02 + +#define IMX_SIP_NOC_SF_PRIORITY 0x01 + +static bool imx8m_smc(struct cpu_user_regs *regs) +{ + uint32_t function_id =3D get_user_reg(regs, 0); + uint32_t subfunction_id =3D get_user_reg(regs, 1); + struct arm_smccc_res res; + + if ( !cpus_have_const_cap(ARM_SMCCC_1_1) ) + { + printk_once(XENLOG_WARNING + "imx8m: smc: no SMCCC 1.1 support. Disabling firmware = calls\n"); + + return false; + } + + /* Only the hardware domain may use the SiP calls */ + if ( !is_hardware_domain(current->domain) ) + { + gprintk(XENLOG_WARNING, "imx8m: smc: No access\n"); + return false; + } + + /* + * Forward only the subfunctions the dom0 kernel actually issues. All + * of these manage hardware that belongs to the hardware domain (power + * domains, M-core, NoC) or are read-only queries. + */ + switch ( function_id ) + { + case IMX_SIP_FID(IMX_SIP_F_GPC): + if ( subfunction_id !=3D IMX_SIP_GPC_SF_PM_DOMAIN ) + return false; + break; + + /* + * CPU and DRAM frequency scaling: the hardware domain does not see the + * whole system and cannot make an informed decision about resources + * shared with the other domains, so deny both (CPU frequency scaling + * is denied on the i.MX8QM platform for the same reason). + */ + case IMX_SIP_FID(IMX_SIP_F_CPUFREQ): + case IMX_SIP_FID(IMX_SIP_F_DDR_DVFS): + return false; + + case IMX_SIP_FID(IMX_SIP_F_SRC): + if ( subfunction_id > IMX_SIP_SRC_SF_M4_STOP ) + return false; + break; + + case IMX_SIP_FID(IMX_SIP_F_SOC_INFO): + break; + + case IMX_SIP_FID(IMX_SIP_F_NOC): + if ( subfunction_id > IMX_SIP_NOC_SF_PRIORITY ) + return false; + break; + + default: + gprintk(XENLOG_WARNING, "imx8m: smc: Unknown function id %x\n", + function_id); + return false; + } + + arm_smccc_1_1_smc(function_id, + subfunction_id, + get_user_reg(regs, 2), + get_user_reg(regs, 3), + get_user_reg(regs, 4), + get_user_reg(regs, 5), + get_user_reg(regs, 6), + get_user_reg(regs, 7), + &res); + + set_user_reg(regs, 0, res.a0); + set_user_reg(regs, 1, res.a1); + set_user_reg(regs, 2, res.a2); + set_user_reg(regs, 3, res.a3); + + return true; +} + +PLATFORM_START(imx8m, "i.MX 8M") + .compatible =3D imx8m_dt_compat, + .smc =3D imx8m_smc, +PLATFORM_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.43.0 From nobody Thu Sep 24 20:50:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1787067649; cv=none; d=zohomail.com; s=zohoarc; b=QYlTa0nD3UPHuM0zzVvhYAJsHwDRaigypdS5XQg1G502cUrjCYjJz9NZUGa/bpwlUoygIXPcvnZiPb5RiwTF/i1Lwlsil7bQH0rzhaBbAZtlcCHgoRmEnrmP5oRmVRz245g45SJF+2HuUSEHfYSu2ju70rEr44tPp0/LYO+6H0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1787067649; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5GnPo4KAZWnrGy/rpIMN59vgyD7cezvUOyXwJsPUekw=; b=Pck0P0iphFE9Mg0Mx9kClQYc62EAl1JT34/8Kc2y46Xzbr8M7yGyHiRnVRxVS+/rygbPietmRJ4Xam6bJRLld1yiB6xWz7BtrVeR6liLbZzqaLZ0E75yyjxlXzD+nQvXjRlm+7u8KoJ9YV94gTklKqFqtp0QF9VYZ9abh3W19Qk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1787067649557265.23928572620525; Tue, 18 Aug 2026 08:40:49 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1394302.1633163 (Exim 4.92) (envelope-from ) id 1wwLvW-00068E-UU; Tue, 18 Aug 2026 15:40:34 +0000 Received: by outflank-mailman (output) from mailman id 1394302.1633163; Tue, 18 Aug 2026 15:40:34 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wwLvW-000684-PZ; Tue, 18 Aug 2026 15:40:34 +0000 Received: by outflank-mailman (input) for mailman id 1394302; Tue, 18 Aug 2026 15:40:33 +0000 Received: from mx.expurgate.net ([194.145.224.20]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wwLvV-00063D-1C for xen-devel@lists.xenproject.org; Tue, 18 Aug 2026 15:40:33 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wwLvU-00DoR5-DT for xen-devel@lists.xenproject.org; Tue, 18 Aug 2026 17:40:32 +0200 Received: from [10.42.69.7] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 6a847ce0-2eae-0a2a0a5409dd-0a2a4507d21e-32 for ; Tue, 18 Aug 2026 17:40:32 +0200 Received: from [209.85.216.43] (helo=mail-pj1-f43.google.com) by tlsNG-ef75cf.mxtls.expurgate.net with ESMTPS (eXpurgate 4.57.1) (envelope-from ) id 6a847cee-b4ea-0a2a45070019-d155d82be94f-3 for ; Tue, 18 Aug 2026 17:40:32 +0200 Received: by mail-pj1-f43.google.com with SMTP id 98e67ed59e1d1-383b4a3755fso63725a91.3 for ; Tue, 18 Aug 2026 08:40:31 -0700 (PDT) Received: from wig-Precision-3660.. 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[125.227.154.99]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3954d2de41dsm6247737a91.5.2026.08.18.08.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Aug 2026 08:40:29 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787067630; x=1787672430; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=5GnPo4KAZWnrGy/rpIMN59vgyD7cezvUOyXwJsPUekw=; b=TXRObutIKkDq+zX4W/Ur8hm45LMqy5RLh7/gpWiwRdiGelEuYMETc9Ku4dttf3WUqj +1U86ezQcjFtr6RDUA4eUTK/mpe62ZkewXSc0jb8NLy26pSeIzVf6N7vqFhZcE2UoNqf dsmREfpe/P4Q3ap2DptagKSBAZhvKmZ/HSVWViGlZ7ZtuwPJplq1b0cNMjZhnzAa3reA sejHJHbyVe7mbgqPuzzaBnkkPha3BcD7bQ+yaK0E0CmWGdngBdwm6HxCJMASUTyKNIU4 GnoTXge/nVK/UMeuHCcXCHvkRz+1di0V0Lgm9m3gh9JxY+C1GYcJf9jjfj/up2VyIPvi aViA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787067630; x=1787672430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=5GnPo4KAZWnrGy/rpIMN59vgyD7cezvUOyXwJsPUekw=; b=FTj8yy7ORDVXw/xwYgdscP6TVCT4vEDiDy57mk4lmVnQ0GA26Wwi+2vynqt7z/1grI c3eYz7ZwQbxNtG9Z4K7MvwSnqA7kMF234RlWWGB/jj1aZ3ipi6BKcbbwwBYfqIHblAEc gKOJKj+sdhWFS3O4ihfoY2un/jD3i3nzgExJ+kb2bCyvBVNQ630wla88Uf/Nm3zaRRaz BpQ6dKERhk9hI+PFTgpmb4vxCAzeVNNl+CDl7ubv0jcm8ujHh4+SUc4Lh6bSGnuR9FG8 oAXsCVzXp1EdS/hXSOO9DdlvP7v217be+5W8emVSy28qXuw+/tH+i5lNrlx/jseJISCj ySMA== X-Gm-Message-State: AOJu0YxKHFSYSt3hnuAybrW4ioCmrACCSWneG7X6e6O5yvCzr/JWY3Ul axIXGucwTHYJAbWFYWlcPjbENSbzF6VuFeVMs8MAfadI7y5fpjqPhj/1wbW+BcaW X-Gm-Gg: AR+sD11/c9cZuBqiKtmaUCUQzxgLfJbO3us7D3D1RKfzJg392KHJv6PmG+1m5VziYmF hOqD2UTCZfXCpZfUroYrgJSX0q8SzbjA9lNA6CFk7pFAEI9IL/gtPjncDjQ3DWCQEmkAjWRcYJn P0zymbWkz8Ct0wuZD/2VeQn3lkxP75APNbzYLp30obzuMzWK4ckjVV0JEtMo6TNiPtEkYOlvgXQ W+yiGsINFIeuAScffbAhfkgcnFTtu+qbPbNfJK5e5MQh9/R8Oe1SQ8CchazTw58kNGle67YQGKK NWbcowFBIr7OHPZHSbxl4GjBQ9HiAtu3TU0mOgyPO1jJHdx9tJDdcpw7+WJWBd270aU4KXK/Q4K DtaoYrVJTgTfy+kk5HEiGMYzckdYD38Cg+kJa5DukMZ97wzy7wik48iOaKcaassLfbs2Txy1P/3 EL+phHaLzXnPmPior23B65a9sk61unDiPhs3tzHhLte42IE51rswPUhMFcNCh4VkaMe8NWZEkhE XsbtkzBZEbfhpL+0hJ3OwqrMcDV4x+b X-Received: by 2002:a17:90a:ec83:b0:381:e74f:8a6a with SMTP id 98e67ed59e1d1-3933b8c1041mr39437789a91.16.1787067629975; Tue, 18 Aug 2026 08:40:29 -0700 (PDT) From: Wig Cheng To: xen-devel@lists.xenproject.org Cc: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , John Ernberg , Peng Fan , Wig Cheng Subject: [PATCH v3 4/4] MAINTAINERS: add myself as reviewer of i.MX8M related patches Date: Tue, 18 Aug 2026 23:39:46 +0800 Message-ID: <20260818153946.1635464-5-onlywig@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260818153946.1635464-1-onlywig@gmail.com> References: <20260818153946.1635464-1-onlywig@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1787067632-34CCFAE4-583081B3/0/0 X-purgate-type: clean X-purgate-size: 867 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787067651147158500 Content-Type: text/plain; charset="utf-8" I wrote the i.MX8M platform and UART support and can help review patches touching these areas. Signed-off-by: Wig Cheng Reviewed-by: Michal Orzel --- Changes in v3: - No changes; picked up Michal's Reviewed-by. MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4dd97ffcad..c60afc93a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -365,6 +365,13 @@ F: tools/misc/xenhypfs.c F: xen/common/hypfs.c F: xen/include/xen/hypfs.h =20 +IMX8M SUPPORT +R: Wig Cheng +F: xen/arch/arm/arm64/debug-imx-uart.inc +F: xen/arch/arm/include/asm/imx-uart.h +F: xen/arch/arm/platforms/imx8m.c +F: xen/drivers/char/imx-uart.c + IMX8QM/QXP SUPPORT R: John Ernberg F: xen/arch/arm/platforms/imx8qm.c --=20 2.43.0