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[125.227.154.99]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3954d3b40basm4333605a91.14.2026.08.17.19.52.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 19:52:44 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787021565; x=1787626365; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=eNEbZb8d3EIW7+AuEqsJziYT7kLVDhA14GbIEAzFYfE=; b=gveSBXEbaN/WdbiPoDk7RRstyviiHje+GPK79+yTJWrQQHRShm3tVicpvkY6VrwpnQ fr5nFjM8nhL5FkVheLc5pl9NCJ/Vdzfe8vpTt8R1KLG8mayOX+v2dqzf/Tl+3XqHJFub Ne3w0u46Zhno/Jy99Jz2QLZCmeKkfWmlMc45XMI4hFH7zxWmLOuwBUlHxhpR2CP+l7MM 1R0Ckb8zrOPTIq5aXxZIUVh9XkjFpLHkZKNojbS20WVSx5iCg1dTvJCPzU82mPXOLjB4 1doJTYO+FrOoo5X64v0eVVZolUePB1r7grYBg45uUCLjhjaT2q/PufOzcPwSRwDwXWcX upMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787021565; x=1787626365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=eNEbZb8d3EIW7+AuEqsJziYT7kLVDhA14GbIEAzFYfE=; b=BRTxyngJDAk7iGugh2ISTEux4S+TbSZPQFQRus2i9Mf/1asd8gqzuXpK2QKSHv07uU skhTFLsgYduV5ySBMR5MyCOrmDQXYnnGcZPlua+KyfWFifbzcszRAUl54TQ9Gl2Bn6G5 saXXijbTxoIfDtEJ+ne+gjwJlu5wdZDgE8Iu+B1JgNOjWFzZkrddRqYajuW73sxggBWu DcVDVRUQmC+1V68h7QK6xUtnhAsXzxWfT0rsca/oPAIA+IZzBijQjD1LcH/79rqwXRU1 C1Nkhh1/jnvlFnCFVyuDBCVgXyyI+K/sZMKmRGDdN5p6y2xbkCTNbgjhSj2ZuaSv+Gj6 Cyww== X-Gm-Message-State: AOJu0YwxZYikkbIgO96HQdOznXHCJCI9/gvUkFox3FBjDUxEImCUbApU X7heRKsuw3z+NwstHkFjNw+R58yU+fi0mFOmVI4FH0Km41Cx3/mMEmkfgWg8/y19 X-Gm-Gg: AR+sD11lzCEtMsgr0JwS9D2GEaz17Y3OwaMgZqyW7O/qhuCmY2M8VjHWVQMg6ZfIjVO N91Ry/jTJkb4mllfT9BI6dHFrNK+VpUqiyqDJJqBeRZ7hYbuPLaprYI9VD1N8m8XGPDIqzNNEJG w/SmMM95u4TCO5DPENlGYqoaWgXnJ99y5arZ3UxtRJwEmberQnKhb6Yf8kCtUIDU5Njk5lGAK4s EA/xo/vTdE7Mgp65AZJU2KajsPbM656uXAsL0Xv1WViylp6HxqtjlEnDgPY3asP3a5wKOAhltHC Z2zgXjcYDoMVwNXSIYv1Y0k/a/WJB0vmwdzxoQdM/Jgw1vPn0oexJ3gmlQKdiqRTVHlbUPSPz+j zfitDySbps3iEMOFaczqAfDO1nlWh1ZOqPZCgUAo1nN3vuHLhaXZxkn+8jTE00lviTNev+29R8+ LPdus/r3tNzT/OcN5ZiRKmNUtVuUmQKIV0GMRLPv/ch7bkKEmb12RMd9B5y3YkC+1NHdgZZxtEY RIBvEwxS7g3Frr5VaMp2aLbF+9giac3QBR96g== X-Received: by 2002:a17:90b:58e8:b0:385:3ab:fecb with SMTP id 98e67ed59e1d1-39563853b56mr1747770a91.4.1787021565402; Mon, 17 Aug 2026 19:52:45 -0700 (PDT) From: Wig Cheng To: xen-devel@lists.xenproject.org Cc: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , John Ernberg , Peng Fan , Wig Cheng Subject: [PATCH v2 1/4] xen/char: add classic i.MX UART driver Date: Tue, 18 Aug 2026 10:52:21 +0800 Message-ID: <20260818025224.4165503-2-onlywig@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260818025224.4165503-1-onlywig@gmail.com> References: <20260818025224.4165503-1-onlywig@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ef75cf/1787021567-A5CC7AE4-03F6A728/0/0 X-purgate-type: clean X-purgate-size: 10556 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787021604244158500 Content-Type: text/plain; charset="utf-8" Add a console driver for the classic i.MX UART IP ("fsl,imx6q-uart" compatible), used as the console UART on the i.MX8M family. Baudrate and pin configuration are inherited from the bootloader; the driver only enables the transmitter/receiver and wires up the RX/TX interrupts, mirroring the existing imx-lpuart driver. The i.MX8M family's UART IP differs from the LPUART used on i.MX8QM/8QXP, so a separate driver is needed. Signed-off-by: Wig Cheng --- xen/arch/arm/include/asm/imx-uart.h | 57 +++++++ xen/drivers/char/Kconfig | 8 + xen/drivers/char/Makefile | 1 + xen/drivers/char/imx-uart.c | 226 ++++++++++++++++++++++++++++ 4 files changed, 292 insertions(+) create mode 100644 xen/arch/arm/include/asm/imx-uart.h create mode 100644 xen/drivers/char/imx-uart.c diff --git a/xen/arch/arm/include/asm/imx-uart.h b/xen/arch/arm/include/asm= /imx-uart.h new file mode 100644 index 0000000000..a3892020e6 --- /dev/null +++ b/xen/arch/arm/include/asm/imx-uart.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Register definitions for the classic i.MX UART IP + * ("fsl,imx6q-uart" compatible), used as the console UART on the + * i.MX8M family. + * + * Register layout taken from Linux drivers/tty/serial/imx.c. + * + * Copyright 2026 Open-EP (E-Paper) Community + */ + +#ifndef ASM_IMX_UART_H +#define ASM_IMX_UART_H + +#include + +#define URXD0 0x00 /* Receiver Register */ +#define URTX0 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UTS 0xb4 /* Test Register */ + +#define URXD_RX_DATA 0xff + +#define UCR1_UARTEN BIT(0, U) /* UART enable */ +#define UCR1_ATDMAEN BIT(2, U) /* Aging DMA timer enable */ +#define UCR1_TXDMAEN BIT(3, U) /* Transmitter ready DMA enable */ +#define UCR1_TXMPTYEN BIT(6, U) /* Transmitter empty interrupt enable = */ +#define UCR1_RXDMAEN BIT(8, U) /* Receiver ready DMA enable */ +#define UCR1_RRDYEN BIT(9, U) /* Receiver ready interrupt enable */ +#define UCR1_TRDYEN BIT(13, U) /* Transmitter ready interrupt enable = */ + +#define UCR2_SRST BIT(0, U) /* 0 =3D issue software reset */ +#define UCR2_RXEN BIT(1, U) /* Receiver enable */ +#define UCR2_TXEN BIT(2, U) /* Transmitter enable */ + +#define USR1_TRDY BIT(13, U) /* Transmitter ready */ + +#define USR2_RDR BIT(0, U) /* Receive data ready */ +#define USR2_ORE BIT(1, U) /* Overrun error */ + +#define UTS_TXFULL BIT(4, U) /* TX FIFO full */ +#define UTS_RXEMPTY BIT(5, U) /* RX FIFO empty */ +#define UTS_TXEMPTY BIT(6, U) /* TX FIFO empty */ + +#endif /* ASM_IMX_UART_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/drivers/char/Kconfig b/xen/drivers/char/Kconfig index 8e49a52c73..f237c0220d 100644 --- a/xen/drivers/char/Kconfig +++ b/xen/drivers/char/Kconfig @@ -30,6 +30,14 @@ config HAS_IMX_LPUART help This selects the i.MX LPUART. If you have i.MX8QM based board, say Y. =20 +config HAS_IMX_UART + bool "i.MX UART driver" + default y + depends on ARM_64 + help + This selects the classic i.MX UART. If you have an i.MX8M family + based board, say Y. + config HAS_MVEBU bool "Marvell MVEBU UART driver" default y diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile index 8cbbffdca8..039f566926 100644 --- a/xen/drivers/char/Makefile +++ b/xen/drivers/char/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_HAS_SCIF) +=3D scif-uart.o obj-$(CONFIG_HAS_EHCI) +=3D ehci-dbgp.o obj-$(CONFIG_XHCI) +=3D xhci-dbc.o obj-$(CONFIG_HAS_IMX_LPUART) +=3D imx-lpuart.o +obj-$(CONFIG_HAS_IMX_UART) +=3D imx-uart.o obj-$(CONFIG_HAS_LINFLEX) +=3D linflex-uart.o obj-$(CONFIG_GENERIC_UART_INIT) +=3D uart-init.o obj-y +=3D serial.o diff --git a/xen/drivers/char/imx-uart.c b/xen/drivers/char/imx-uart.c new file mode 100644 index 0000000000..fd34b0cd11 --- /dev/null +++ b/xen/drivers/char/imx-uart.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Driver for the classic i.MX UART IP ("fsl,imx6q-uart"), used as the + * console UART on the i.MX8M family (e.g. i.MX8MP). + * + * Baudrate and pin configuration are inherited from the bootloader. + * + * Copyright 2026 Open-EP (E-Paper) Community + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define imx_uart_read(uart, off) readl((uart)->regs + (off)) +#define imx_uart_write(uart, off, val) writel((val), (uart)->regs + (off)) + +static struct imx_uart { + uint32_t irq; + char __iomem *regs; + struct irqaction irqaction; + struct vuart_info vuart; +} imx8m_com; + +static void imx_uart_interrupt(int irq, void *data) +{ + struct serial_port *port =3D data; + struct imx_uart *uart =3D port->uart; + + if ( imx_uart_read(uart, USR2) & USR2_RDR ) + serial_rx_interrupt(port); + + if ( imx_uart_read(uart, USR1) & USR1_TRDY ) + serial_tx_interrupt(port); +} + +static void __init imx_uart_init_preirq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t ucr1, ucr2; + + /* + * Reuse the bootloader settings; only enable the UART and both + * directions. The console uses UCR1 interrupts (RRDYEN/TRDYEN) + * exclusively, so just clear UCR1's interrupt and DMA enables. + */ + ucr1 =3D imx_uart_read(uart, UCR1); + ucr1 &=3D ~(UCR1_RRDYEN | UCR1_TRDYEN | UCR1_TXMPTYEN | UCR1_RXDMAEN | + UCR1_TXDMAEN | UCR1_ATDMAEN); + ucr1 |=3D UCR1_UARTEN; + imx_uart_write(uart, UCR1, ucr1); + + ucr2 =3D imx_uart_read(uart, UCR2); + ucr2 |=3D UCR2_SRST | UCR2_RXEN | UCR2_TXEN; + imx_uart_write(uart, UCR2, ucr2); +} + +static void __init imx_uart_init_postirq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t ucr1; + + uart->irqaction.handler =3D imx_uart_interrupt; + uart->irqaction.name =3D "imx_uart"; + uart->irqaction.dev_id =3D port; + + if ( setup_irq(uart->irq, 0, &uart->irqaction) !=3D 0 ) + { + dprintk(XENLOG_ERR, "Failed to allocate imx_uart IRQ %d\n", uart->= irq); + return; + } + + /* Enable the receiver ready interrupt */ + ucr1 =3D imx_uart_read(uart, UCR1); + ucr1 |=3D UCR1_RRDYEN; + imx_uart_write(uart, UCR1, ucr1); +} + +static int imx_uart_tx_ready(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + + return !(imx_uart_read(uart, UTS) & UTS_TXFULL); +} + +static void imx_uart_putc(struct serial_port *port, char c) +{ + struct imx_uart *uart =3D port->uart; + + while ( imx_uart_read(uart, UTS) & UTS_TXFULL ) + cpu_relax(); + + imx_uart_write(uart, URTX0, c); +} + +static int imx_uart_getc(struct serial_port *port, char *pc) +{ + struct imx_uart *uart =3D port->uart; + + if ( !(imx_uart_read(uart, USR2) & USR2_RDR) ) + return 0; + + *pc =3D imx_uart_read(uart, URXD0) & URXD_RX_DATA; + + if ( imx_uart_read(uart, USR2) & USR2_ORE ) + imx_uart_write(uart, USR2, USR2_ORE); + + return 1; +} + +static int __init imx_uart_irq(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + + return ((uart->irq > 0) ? uart->irq : -1); +} + +static const struct vuart_info *imx_uart_vuart_info(struct serial_port *po= rt) +{ + struct imx_uart *uart =3D port->uart; + + return &uart->vuart; +} + +static void imx_uart_start_tx(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t ucr1; + + ucr1 =3D imx_uart_read(uart, UCR1); + imx_uart_write(uart, UCR1, ucr1 | UCR1_TRDYEN); +} + +static void imx_uart_stop_tx(struct serial_port *port) +{ + struct imx_uart *uart =3D port->uart; + uint32_t ucr1; + + ucr1 =3D imx_uart_read(uart, UCR1); + imx_uart_write(uart, UCR1, ucr1 & ~UCR1_TRDYEN); +} + +static struct uart_driver __read_mostly imx_uart_driver =3D { + .init_preirq =3D imx_uart_init_preirq, + .init_postirq =3D imx_uart_init_postirq, + .tx_ready =3D imx_uart_tx_ready, + .putc =3D imx_uart_putc, + .getc =3D imx_uart_getc, + .irq =3D imx_uart_irq, + .start_tx =3D imx_uart_start_tx, + .stop_tx =3D imx_uart_stop_tx, + .vuart_info =3D imx_uart_vuart_info, +}; + +static int __init imx_uart_init(struct dt_device_node *dev, const void *da= ta) +{ + const char *config =3D data; + struct imx_uart *uart; + int res; + paddr_t addr, size; + + if ( strcmp(config, "") ) + printk("WARNING: UART configuration is not supported\n"); + + uart =3D &imx8m_com; + + res =3D dt_device_get_paddr(dev, 0, &addr, &size); + if ( res ) + { + printk("imx-uart: Unable to retrieve the base address of the UART\= n"); + return res; + } + + res =3D platform_get_irq(dev, 0); + if ( res < 0 ) + { + printk("imx-uart: Unable to retrieve the IRQ\n"); + return -EINVAL; + } + uart->irq =3D res; + + uart->regs =3D ioremap_nocache(addr, size); + if ( !uart->regs ) + { + printk("imx-uart: Unable to map the UART memory\n"); + return -ENOMEM; + } + + uart->vuart.base_addr =3D addr; + uart->vuart.size =3D size; + uart->vuart.data_off =3D URTX0; + uart->vuart.status_off =3D UTS; + uart->vuart.status =3D UTS_TXEMPTY | UTS_RXEMPTY; + + /* Register with generic serial driver */ + serial_register_uart(SERHND_DTUART, &imx_uart_driver, uart); + + dt_device_set_used_by(dev, DOMID_XEN); + + return 0; +} + +static const struct dt_device_match imx_uart_dt_compat[] __initconst =3D +{ + DT_MATCH_COMPATIBLE("fsl,imx6q-uart"), + { /* sentinel */ }, +}; + +DT_DEVICE_START(imx_uart, "i.MX UART", DEVICE_SERIAL) + .dt_match =3D imx_uart_dt_compat, + .init =3D imx_uart_init, +DT_DEVICE_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.43.0 From nobody Thu Sep 24 20:21:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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The UART is expected to be fully initialized by the bootloader. Signed-off-by: Wig Cheng Reviewed-by: Michal Orzel --- xen/arch/arm/Kconfig.debug | 12 +++++++++ xen/arch/arm/arm64/debug-imx-uart.inc | 37 +++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 xen/arch/arm/arm64/debug-imx-uart.inc diff --git a/xen/arch/arm/Kconfig.debug b/xen/arch/arm/Kconfig.debug index 5a03b220ac..63a34b813a 100644 --- a/xen/arch/arm/Kconfig.debug +++ b/xen/arch/arm/Kconfig.debug @@ -44,6 +44,14 @@ choice Say Y here if you wish the early printk to direct their output to a i.MX LPUART. =20 + config EARLY_UART_CHOICE_IMX_UART + select EARLY_UART_IMX_UART + depends on ARM_64 + bool "Early printk via i.MX UART" + help + Say Y here if you wish the early printk to direct their + output to the classic i.MX UART (i.MX8M family). + config EARLY_UART_CHOICE_LINFLEX select EARLY_UART_LINFLEX depends on ARM_64 @@ -97,6 +105,9 @@ config EARLY_UART_EXYNOS4210 config EARLY_UART_IMX_LPUART select EARLY_PRINTK bool +config EARLY_UART_IMX_UART + select EARLY_PRINTK + bool config EARLY_UART_LINFLEX select EARLY_PRINTK bool @@ -185,6 +196,7 @@ config EARLY_PRINTK_INC default "debug-cadence.inc" if EARLY_UART_CADENCE default "debug-exynos4210.inc" if EARLY_UART_EXYNOS4210 default "debug-imx-lpuart.inc" if EARLY_UART_IMX_LPUART + default "debug-imx-uart.inc" if EARLY_UART_IMX_UART default "debug-linflex.inc" if EARLY_UART_LINFLEX default "debug-meson.inc" if EARLY_UART_MESON default "debug-mvebu.inc" if EARLY_UART_MVEBU diff --git a/xen/arch/arm/arm64/debug-imx-uart.inc b/xen/arch/arm/arm64/deb= ug-imx-uart.inc new file mode 100644 index 0000000000..19b1679020 --- /dev/null +++ b/xen/arch/arm/arm64/debug-imx-uart.inc @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Early printk for the classic i.MX UART IP (i.MX8M family). + * The UART is expected to be fully initialized by the bootloader. + * + * Copyright 2026 Open-EP (E-Paper) Community + */ + +#include + +/* + * Wait for the UART to be ready to transmit + * xb: register which contains the UART base address + * c: scratch register + */ +.macro early_uart_ready xb, c +1: + ldr w\c, [\xb, #UTS] /* <- Test register */ + tst w\c, #UTS_TXFULL /* Check TX FIFO full bit */ + b.ne 1b /* Wait until there is room */ +.endm + +/* + * UART transmit character + * xb: register which contains the UART base address + * wt: register which contains the character to transmit + */ +.macro early_uart_transmit xb, wt + str \wt, [\xb, #URTX0] /* -> Transmitter register */ +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ --=20 2.43.0 From nobody Thu Sep 24 20:21:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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When Linux is used as dom0 a number of drivers make SiP SMC calls into TF-A to manage hardware: GPC power domains, DDR frequency scaling, SRC (M-core remoteproc), SoC info and NoC QoS. There is no public specification for these calls; the function IDs and their subfunctions are taken from the vendor kernel call sites. Forward only the specific subfunctions the hardware domain issues, following the whitelist model of the i.MX8QM platform. Where a service has a fixed set of subfunctions (GPC, SRC, NoC) they are filtered; DDR DVFS is left at service level because its reg1 is a frequency setpoint rather than a fixed subfunction id, and the SoC info call is a read-only query. CPU frequency scaling is denied because the hardware domain cannot make an informed decision, and any unknown function ID is rejected. Signed-off-by: Wig Cheng --- xen/arch/arm/platforms/Makefile | 1 + xen/arch/arm/platforms/imx8m.c | 152 ++++++++++++++++++++++++++++++++ 2 files changed, 153 insertions(+) create mode 100644 xen/arch/arm/platforms/imx8m.c diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makef= ile index bec6e55d1f..cdf936c50d 100644 --- a/xen/arch/arm/platforms/Makefile +++ b/xen/arch/arm/platforms/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_ALL_PLAT) +=3D sunxi.o obj-$(CONFIG_ALL64_PLAT) +=3D thunderx.o obj-$(CONFIG_ALL64_PLAT) +=3D xgene-storm.o obj-$(CONFIG_ALL64_PLAT) +=3D brcm-raspberry-pi.o +obj-$(CONFIG_ALL64_PLAT) +=3D imx8m.o obj-$(CONFIG_ALL64_PLAT) +=3D imx8qm.o obj-$(CONFIG_MPSOC_PLATFORM) +=3D xilinx-zynqmp.o obj-$(CONFIG_MPSOC_PLATFORM) +=3D xilinx-zynqmp-eemi.o diff --git a/xen/arch/arm/platforms/imx8m.c b/xen/arch/arm/platforms/imx8m.c new file mode 100644 index 0000000000..fcf01298d8 --- /dev/null +++ b/xen/arch/arm/platforms/imx8m.c @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * i.MX 8M family setup + * + * Copyright 2026 Open-EP (E-Paper) Community + */ + +#include +#include +#include + +static const char * const imx8m_dt_compat[] __initconst =3D +{ + "fsl,imx8mp", + "fsl,imx8mq", + "fsl,imx8mm", + "fsl,imx8mn", + NULL +}; + +#define IMX_SIP_FID(fid) \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_CONV_64, \ + ARM_SMCCC_OWNER_SIP, \ + (fid)) + +/* + * SiP SMC function IDs used by the i.MX8M Linux drivers. There is no + * public specification for these; the IDs and their subfunctions are + * extracted from the vendor kernel call sites (see drivers/soc/imx, + * drivers/devfreq, drivers/remoteproc). + */ +#define IMX_SIP_F_GPC 0x0 /* GPC power-domain control */ +#define IMX_SIP_F_CPUFREQ 0x1 +#define IMX_SIP_F_DDR_DVFS 0x4 /* DRAM frequency scaling */ +#define IMX_SIP_F_SRC 0x5 /* SRC: M-core remoteproc start/stop */ +#define IMX_SIP_F_SOC_INFO 0x6 /* read-only SoC info query */ +#define IMX_SIP_F_NOC 0x8 /* NoC QoS priority setup */ + +#define IMX_SIP_GPC_SF_PM_DOMAIN 0x03 + +#define IMX_SIP_SRC_SF_M4_START 0x00 +#define IMX_SIP_SRC_SF_M4_STOP 0x02 + +#define IMX_SIP_NOC_SF_LCDIF 0x00 +#define IMX_SIP_NOC_SF_PRIORITY 0x01 + +static bool imx8m_smc(struct cpu_user_regs *regs) +{ + uint32_t function_id =3D get_user_reg(regs, 0); + uint32_t subfunction_id =3D get_user_reg(regs, 1); + struct arm_smccc_res res; + + if ( !cpus_have_const_cap(ARM_SMCCC_1_1) ) + { + printk_once(XENLOG_WARNING + "imx8m: smc: no SMCCC 1.1 support. Disabling firmware = calls\n"); + + return false; + } + + /* Only the hardware domain may use the SiP calls */ + if ( !is_hardware_domain(current->domain) ) + { + gprintk(XENLOG_WARNING, "imx8m: smc: No access\n"); + return false; + } + + /* + * Forward only the subfunctions the dom0 kernel actually issues. All + * of these manage hardware that belongs to the hardware domain (power + * domains, DRAM controller, M-core, NoC) or are read-only queries. + */ + switch ( function_id ) + { + case IMX_SIP_FID(IMX_SIP_F_GPC): + if ( subfunction_id !=3D IMX_SIP_GPC_SF_PM_DOMAIN ) + goto deny_subfunction; + break; + + case IMX_SIP_FID(IMX_SIP_F_SRC): + if ( subfunction_id > IMX_SIP_SRC_SF_M4_STOP ) + goto deny_subfunction; + break; + + case IMX_SIP_FID(IMX_SIP_F_NOC): + if ( subfunction_id > IMX_SIP_NOC_SF_PRIORITY ) + goto deny_subfunction; + break; + + case IMX_SIP_FID(IMX_SIP_F_DDR_DVFS): + /* + * For DDR DVFS reg1 is a frequency setpoint index (or the + * GET_FREQ_COUNT / GET_FREQ_INFO query), not a fixed subfunction + * id, so it is not filtered here. + */ + break; + + case IMX_SIP_FID(IMX_SIP_F_SOC_INFO): + break; + + /* + * CPU frequency scaling: the hardware domain does not see the whole + * system and cannot make an informed decision, so deny it (matches + * the i.MX8QM platform). + */ + case IMX_SIP_FID(IMX_SIP_F_CPUFREQ): + return false; + + default: + gprintk(XENLOG_WARNING, "imx8m: smc: Unknown function id %x\n", + function_id); + return false; + } + + arm_smccc_1_1_smc(function_id, + subfunction_id, + get_user_reg(regs, 2), + get_user_reg(regs, 3), + get_user_reg(regs, 4), + get_user_reg(regs, 5), + get_user_reg(regs, 6), + get_user_reg(regs, 7), + &res); + + set_user_reg(regs, 0, res.a0); + set_user_reg(regs, 1, res.a1); + set_user_reg(regs, 2, res.a2); + set_user_reg(regs, 3, res.a3); + + return true; + + deny_subfunction: + gprintk(XENLOG_WARNING, + "imx8m: smc: function %x: denied subfunction %x\n", + function_id, subfunction_id); + return false; +} + +PLATFORM_START(imx8m, "i.MX 8M") + .compatible =3D imx8m_dt_compat, + .smc =3D imx8m_smc, +PLATFORM_END + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ --=20 2.43.0 From nobody Thu Sep 24 20:21:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[125.227.154.99]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3954d3b40basm4333605a91.14.2026.08.17.19.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2026 19:52:57 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=20251104 header.d=gmail.com header.i="@gmail.com" header.h="Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1787021579; x=1787626379; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=LmPSKrMbhSlQ3VAakH/YeUU+H9erldiN9BSC2cOsGzs=; b=PBD2mBRLaLdWw6vmRafQK40MMX80kHCZi+f/X7sfgFychshAgLi4FH7QR/mmqmj66Q y8x5KYyPakO7u4eLVYMjzDidS2KtogeLzJchpvLKZuPwQrx+zbg4X/yPFbA62SXvMzhg 1S/2wgMFK9+Q42t/G9OJT9ZUr4HFr/mKEuLKhpKRkbwDy67563Lk+FY09mnoVbcXi/R2 N16i5jYKxCjriIbowcb5Wpme+c1AhOwtumMJQvz2nU4iwIIdNswej2+J3nc09Z1FQn7u 8RjGIGf2hzDoGyOomoBgHLfvT9I8fCVgoJpVrcks9Wj4tV1o0AqF7iCQWi7aXXT3ltZG HOdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787021579; x=1787626379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=LmPSKrMbhSlQ3VAakH/YeUU+H9erldiN9BSC2cOsGzs=; b=TxWVB11TgKzbosmqQ+BJU0kU7K/ZMsajCZCzwmS6GAsvMjuPwopv95H99RN2MWF4Y6 dYMlgc+iD2W8d32xae8pKyCj2vjGNV5sn0KJD07XZCIr2jvLY/bjAtUKN6T+eITPX/Lp 5LndtmxeQP+50ihw2/7f/bYNxzDi3MH2SIMwtAFr+GApB6tWXNcMPBqgu7UatBXigy54 n5NU7HiPFb5n7ebti1OB00s8T6zp8LK0fQWgp8roHdhB2QambEvkJfFg5Mzus2GFTLyQ NkT1LYIe1JEm4YkbmG+ACUVq2O4lzncuUONmjRI7fQ5ZeTsVUxRxhn5JG4y2UPgiGeZI OOxg== X-Gm-Message-State: AOJu0YyaZ4Q13TXcTPvrNm2lGwwspQj72l+OLvu1T+F0LLfgKiy2Yaui qz4CCesYpAWpWclSqut5U73f1GHIl5WoX+y7fgHHlZkka0RbdXzAQmkTo93r8BB9 X-Gm-Gg: AR+sD12wtHXhJaDWh6VN4FeoA32v8aNoZj4SmtnsZNZ+gqF1MXM2Up/gUsy2uZH2rGu yxK80yzzrF/Yt3pJ6PGJrWVHrOaUtchB7QrzqAsTD8AaynnCyiuP0P+mJQM1RsWMsJ6SV/VjuN7 7nHUSAPt+POsYUIDxek3ZtMlIAtCKAF0I3U4WMwGmIQSZHINLqLph4oWg/NV8Ym9jaXGN6evPBR 2+bzXtS3ayTyo7bREIwvwlz4D709V54ESO7ZcUWCp8D5u5D2sSExY9JMW+AQbWruZkn14PLsIJS MB76rGpQkUY+ErrtJu+dOgbnl834mmxQhTW0rbltgpSbHTKZh5zyRnKYOy5XtJuhEHX1TyakVHn bqGF2EPPzpFjnHWJjh0U1hVFQ8fi8qdcrGciraI1kczm2ysl81LlqFJpKRTAo/Xs9ZkRzevq5fr 578c8jGAVVStnU0q/O7XyazqRpqBpGSAPJ2bQIOr4qhsW/eegC9lJQcurRR0kP6WMeu2BKvMbQT n5wAgbtQJxQ9PY3OfdXYYIKqaItfVIs X-Received: by 2002:a17:90b:224e:b0:38e:6a44:671b with SMTP id 98e67ed59e1d1-3933b506db9mr25497993a91.0.1787021578702; Mon, 17 Aug 2026 19:52:58 -0700 (PDT) From: Wig Cheng To: xen-devel@lists.xenproject.org Cc: Michal Orzel , Stefano Stabellini , Julien Grall , Bertrand Marquis , Volodymyr Babchuk , John Ernberg , Peng Fan , Wig Cheng Subject: [PATCH v2 4/4] MAINTAINERS: add myself as reviewer of i.MX8M related patches Date: Tue, 18 Aug 2026 10:52:24 +0800 Message-ID: <20260818025224.4165503-5-onlywig@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260818025224.4165503-1-onlywig@gmail.com> References: <20260818025224.4165503-1-onlywig@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-d62444/1787021580-1FE68757-D59D1D7C/0/0 X-purgate-type: clean X-purgate-size: 752 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1787021606155158500 Content-Type: text/plain; charset="utf-8" I wrote the i.MX8M platform and UART support and can help review patches touching these areas. Signed-off-by: Wig Cheng Reviewed-by: Michal Orzel --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ed0ffa608f..0434377fe1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -364,6 +364,13 @@ F: tools/misc/xenhypfs.c F: xen/common/hypfs.c F: xen/include/xen/hypfs.h =20 +IMX8M SUPPORT +R: Wig Cheng +F: xen/arch/arm/arm64/debug-imx-uart.inc +F: xen/arch/arm/include/asm/imx-uart.h +F: xen/arch/arm/platforms/imx8m.c +F: xen/drivers/char/imx-uart.c + IMX8QM/QXP SUPPORT R: John Ernberg F: xen/arch/arm/platforms/imx8qm.c --=20 2.43.0