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[78.146.248.75]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49987779a11sm3878065e9.2.2026.08.13.10.43.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Aug 2026 10:43:22 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1786643003; x=1787247803; darn=lists.xenproject.org; h=content-transfer-encoding:content-type:mime-version:message-id:date :subject:cc:to:from:from:to:cc:subject:date:message-id:reply-to :content-type; bh=7YMFuJMms+V3nzbvUzla9kD+AeHM+vlytqXfkk0/IRs=; b=Zdfm+8MQF0VEja0J3JPBRLP8vf1Qj30g76YIFjvgGsFpxI5moMUB+g3gfBpscY7hmN CBppsr+F77WAo9Z3uCHVjpBbtweomRBFPBwYt6s6CGPi4Dyw3P/sLjsXfdbkGDF+cKVY haWlMpSVyUZJRpHwKJVw3j+HlCyRU8flHbZKs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1786643003; x=1787247803; h=content-transfer-encoding:content-type:mime-version:message-id:date :subject:cc:to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to:content-type; bh=7YMFuJMms+V3nzbvUzla9kD+AeHM+vlytqXfkk0/IRs=; b=k4Bpycur29aBBnrpns/kcAU+csF+YQ95LUPP5wDKhpK4Z+oZdz0i62GLeHKGQjYp3B xoSch1lx5EhmWMdKyRdPGLXJgfL17pRId1vHNApgGvmXCi6CPTi1XwVyEFiGNxuVi8mb /Mc1kE4FnHN3+8WTvuTItjMJWv5xAIrhjVrm+nWES/njDwC7PvWhhokTniElHu41v7p6 oGpxfTEjfVg9S3WIQlgaxn080bZcHqPovsCejfXkvMYrT0zoFxt2cTn7nBXHh0u6ExIL 5eNaEyKPFqHUmeGB3bcODZRY0/Ro6MhUr0Y9kt4ylGZykHFfSMdXAofSlH2oguw8jEAn FJLw== X-Gm-Message-State: AOJu0YyD39PthZlPNWyXq3v/uwLw5tBqH+1yWYagAxqd3coOsY5X4DPR oqpvDc72QHh8Q7YkMovQc5y+/bBSLFwPVrtrZ9xjjfH1IK1FjPYjEnpyPBhjeUH59yFT5VasLZu /bAIE/94= X-Gm-Gg: AR+sD1128hn85A26n/QkOMAkbBsEvO4wJMtJn/w2ZMkffDFkaF/MAKloMXraMVAT5bC sMlsztVGXWmSiBYzwy88pCbBySOLUAdDueQWrWrV9RBfzi03VlG+61lV6ciSbbwJ7tz67Yw7fYv FvqyjZzluIBEZvYSEz6sCCROpoLb2ZEi4mEZwQlfivwZZOYjT9rYjAnAztRAlTwEhnMnbmu3BPP JuMvBde8JiYFr4hGAd4GAGC+hoev1/siit6hPQA0QvBOYLzFrXDCvVfpgKJ39z+vxHzSNltNfXD CCTtoLrlhCHsMbNPsyiM3WAPe5IZi4yl9qR2pMLZnjRw1dAYue8nKJRHIz5JvNRtgSv1C+buqB0 gNPIeufu+lb6Na7KxPnjO/sUB1mgsw4XsgQrpDrHTa6ULxRnNPKHjmKlD4NG+73WkdUaMrEj+p7 6z5d0ECS3qrDrtypMpVcR0fuzh6isLYH6WDPKPnE429h4MGWoIIeO2BLQyo+kP18dhEy5isXWdX deWIcERsAMMVWfqtIyy6wINkdkrKyZSdXSTWmU= X-Received: by 2002:a05:600c:1d89:b0:499:726a:117c with SMTP id 5b1f17b1804b1-499879bf7d0mr780895e9.19.1786643002850; Thu, 13 Aug 2026 10:43:22 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [PATCH] x86/nmi: Fix mis-classification of watchdog NMIs Date: Thu, 13 Aug 2026 18:43:19 +0100 Message-Id: <20260813174319.1682009-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1786643003-F70B22A1-D099A82B/0/0 X-purgate-type: clean X-purgate-size: 3211 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1786643028618158500 It used to be the case that cpu_data[] inherited the BSP's cpuid_level until the AP had calculated it itself. Following the rework, cpuid_level has a placeholder 1 until it is caluclated propely. setup_apic_nmi_watchdog() happens to be called on the BSP after SMP bringup, meaning that the first call is on CPU1. It is also positioned in the window where cpu_data[] is garbage. As a result, setup_p6_watchdog()'s one-time calculation of the performance counter width falls back into Pentium compatibility mode assuming 32bit counters. This causes a watchdog NMI which is delayed a little (e.g. from = an SMI), to appear as if it hadn't overflowed, and therefore be (mis)classifed= as not a watchdog NMI. On systems where unknown NMIs are treated as fatal, th= is results in a spurious crash. Switch setup_p6_watchdog() to use boot_cpu_data.cpuid_level, which is how t= his is checked almost everywhere else. core2_vpmu_init() used the same pattern to look at leaf 0xa. Despite being init code and only running on the BSP, {boot,current}_cpu_data are different objects, so switch it over to checking boot_cpu_data.cpuid_level too. Fixes: 7126b7f806d5 ("x86/CPU: re-work populating of cpu_data[]") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Teddy Astie Found on a system where: [root@box ~]# time xen-ucode ./blob real 0m9.166s user 0m0.001s sys 0m9.165s is changing several expectations, and spurious crashes from mis-classified watchdog NMIs is just one part of the problem. I hate this fix, but it's the only thing which I consider remotely safe to backport. Recent attempts to alter CPUID ordering have 0 success at being bug-free. I have not investigated what else was broken by the cpu_data[] change, owing to a lack of time on my part. I would be amazed if this is the only thing. --- xen/arch/x86/cpu/vpmu_intel.c | 2 +- xen/arch/x86/nmi.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index ed9f62b9366d..af6cb0a85cdd 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -896,7 +896,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) unsigned int version =3D 0; unsigned int i; =20 - if ( current_cpu_data.cpuid_level >=3D 0xa ) + if ( bsp_cpu_data.cpuid_level >=3D 0xa ) version =3D MASK_EXTR(cpuid_eax(0xa), PMU_VERSION_MASK); =20 switch ( version ) diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index 91f95fe6d080..ec85516609b0 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -321,7 +321,7 @@ static void setup_p6_watchdog(unsigned counter) { unsigned int evntsel; =20 - if ( !nmi_p6_event_width && current_cpu_data.cpuid_level >=3D 0xa ) + if ( !nmi_p6_event_width && boot_cpu_data.cpuid_level >=3D 0xa ) nmi_p6_event_width =3D MASK_EXTR(cpuid_eax(0xa), P6_EVENT_WIDTH_MA= SK); if ( !nmi_p6_event_width ) nmi_p6_event_width =3D P6_EVENT_WIDTH_MIN; --=20 2.39.5