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AHgh+RrLYLgL9ESakyj5CZCuWRQ995Lii1QhVLGVwbR4CB7M1A9DWIIago0RWoz3gNsmPF36YLRZSQXXfj4=@lists.xenproject.org X-Gm-Message-State: AOJu0YysDo6Y9Z8pw9wMpQw+qnck42nc+ZdbVbArX7jONWwCm14O+GIr vQFkmRZ1zZYhYv19C9zGqQ24hqlINTTNCBzsPVxSZYWgRAfE3C9WU5Lx+JrcN0B4lwLWSMTextw KkRimug== X-Received: from pglr15.prod.google.com ([2002:a63:514f:0:b0:c9a:7d72:c316]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:2d0c:b0:84e:2382:f4f0 with SMTP id d2e1a72fcca58-84f2dfc8ed4mr19812672b3a.4.1786059387185; Thu, 06 Aug 2026 16:36:27 -0700 (PDT) Reply-To: Sean Christopherson Date: Thu, 6 Aug 2026 16:35:20 -0700 In-Reply-To: <20260806233609.212337-1-seanjc@google.com> Mime-Version: 1.0 References: <20260806233609.212337-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.679.g6767b8d81c-goog Message-ID: <20260806233609.212337-4-seanjc@google.com> Subject: [PATCH v6 03/51] x86/tsc: Ensure that TSC recalibration doesn't run if TSC frequency is known From: Sean Christopherson To: Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , Paolo Bonzini , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Ajay Kaher , Alexey Makhalov , Jan Kiszka , Dave Hansen , Andy Lutomirski , Peter Zijlstra , Juergen Gross , Daniel Lezcano , Thomas Gleixner , John Stultz Cc: Vitaly Kuznetsov , Broadcom internal kernel review list , Boris Ostrovsky , Stephen Boyd , Miroslav Lichvar , x86@kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Michael Kelley , Tom Lendacky , Nikunj A Dadhania , David Woodhouse , David Woodhouse , Thomas Gleixner X-purgate-ID: tlsNG-33051d/1786059389-764FC4E9-10560814/0/0 X-purgate-type: clean X-purgate-size: 1414 X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1786059429471158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When attempting TSC recalibration post-boot, which is only done for ancient CPUS (P4 and K7) on SMP=3Dn kernels, assert that the TSC frequency isn't known (explicitly provided by hardware) by way of MSR or CPUID, and bail if the impossible happens. In practice, recalibration and TSC_KNOWN_FREQ are mutually exclusive, as TSC_KNOWN_FREQ will only be set when running on hardware that was released decades after recalibration was obsoleted, but but it's hard to see that, especially when looking at just the TSC code. Note, the WARN can likely be tripped by running in a virtual machine and concocting an impossible CPU model, e.g. by combining a P4 signature with CPUID 0x15. This is working as intended, as such a virtual CPU model is wildly out-of-spec and is not supported. Signed-off-by: Sean Christopherson --- arch/x86/kernel/tsc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 4392fddd616e..bc4348585194 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -930,6 +930,9 @@ void recalibrate_cpu_khz(void) if (!boot_cpu_has(X86_FEATURE_TSC)) return; =20 + if (WARN_ON_ONCE(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ))) + return; + cpu_khz =3D x86_platform.calibrate_cpu(); tsc_khz =3D x86_platform.calibrate_tsc(); if (tsc_khz =3D=3D 0) --=20 2.55.0.679.g6767b8d81c-goog