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Drop them. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Teddy Astie --- xen/arch/x86/include/asm/apic.h | 2 -- xen/arch/x86/nmi.c | 50 --------------------------------- 2 files changed, 52 deletions(-) diff --git a/xen/arch/x86/include/asm/apic.h b/xen/arch/x86/include/asm/api= c.h index 918f1cee3567..f30d57ad22c5 100644 --- a/xen/arch/x86/include/asm/apic.h +++ b/xen/arch/x86/include/asm/apic.h @@ -174,8 +174,6 @@ extern void setup_boot_APIC_clock (void); extern void setup_secondary_APIC_clock (void); extern void setup_apic_nmi_watchdog (void); extern void disable_lapic_nmi_watchdog(void); -extern int reserve_lapic_nmi(void); -extern void release_lapic_nmi(void); extern void self_nmi(void); extern void disable_timer_nmi_watchdog(void); extern void enable_timer_nmi_watchdog(void); diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index 91f95fe6d080..616bfdbc9029 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -89,20 +89,6 @@ static int __init cf_check parse_watchdog_timeout(const = char *s) } custom_param("watchdog_timeout", parse_watchdog_timeout); =20 -/* - * lapic_nmi_owner tracks the ownership of the lapic NMI hardware: - * - it may be reserved by some other driver, or not - * - when not reserved by some other driver, it may be used for - * the NMI watchdog, or not - * - * This is maintained separately from nmi_active because the NMI - * watchdog may also be driven from the I/O APIC timer. - */ -static DEFINE_SPINLOCK(lapic_nmi_owner_lock); -static unsigned int lapic_nmi_owner; -#define LAPIC_NMI_WATCHDOG (1<<0) -#define LAPIC_NMI_RESERVED (1<<1) - /* nmi_active: * +1: the lapic NMI watchdog is active, but can be disabled * 0: the lapic NMI watchdog has not been set up, and cannot @@ -239,41 +225,6 @@ void disable_lapic_nmi_watchdog(void) nmi_watchdog =3D NMI_NONE; } =20 -static void enable_lapic_nmi_watchdog(void) -{ - if (nmi_active < 0) { - nmi_watchdog =3D NMI_LOCAL_APIC; - setup_apic_nmi_watchdog(); - } -} - -int reserve_lapic_nmi(void) -{ - unsigned int old_owner; - - spin_lock(&lapic_nmi_owner_lock); - old_owner =3D lapic_nmi_owner; - lapic_nmi_owner |=3D LAPIC_NMI_RESERVED; - spin_unlock(&lapic_nmi_owner_lock); - if (old_owner & LAPIC_NMI_RESERVED) - return -EBUSY; - if (old_owner & LAPIC_NMI_WATCHDOG) - disable_lapic_nmi_watchdog(); - return 0; -} - -void release_lapic_nmi(void) -{ - unsigned int new_owner; - - spin_lock(&lapic_nmi_owner_lock); - new_owner =3D lapic_nmi_owner & ~LAPIC_NMI_RESERVED; - lapic_nmi_owner =3D new_owner; - spin_unlock(&lapic_nmi_owner_lock); - if (new_owner & LAPIC_NMI_WATCHDOG) - enable_lapic_nmi_watchdog(); -} - /* * Activate the NMI watchdog via the local APIC. * Original code written by Keith Owens. @@ -417,7 +368,6 @@ void setup_apic_nmi_watchdog(void) return; } =20 - lapic_nmi_owner =3D LAPIC_NMI_WATCHDOG; nmi_active =3D 1; } =20 --=20 2.34.1 From nobody Thu Aug 13 09:18:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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([157.231.70.114]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fec23e533sm8779762f8f.28.2026.08.05.05.45.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 05:45:28 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1785933930; x=1786538730; darn=lists.xenproject.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=v6YeRlTNauFBLjWJsxycUzL7eVgOm6WLxLhWDN+HbJU=; b=udEnqSmqzEKqr30c4WmlY74xN4zW4hVH132pJbsRK5cQxSgnZQ3id160fqebHx0u47 Q3aUIK2M/9K7BIAq0WaqexGzvJIndbZmgT4r950aqI6LPVXsjnQpBYv6gfmbR/WUuBoi U9wDyGy8aZwl0H5cHFYCFWkjHEGXGeGkRBAXw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785933930; x=1786538730; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=v6YeRlTNauFBLjWJsxycUzL7eVgOm6WLxLhWDN+HbJU=; b=Y4LDSHYLhIxfj/E9MIV1aWqmKaMbL08f21Ay/TrYhC/cMVfYkxc0xMRqQn+k3t6vt2 5ounHtrVloUKoVIipdkpXwD52hbNYGu8XlKfjtaBZ4/rWNMAKpgwFmf6i8/6rQyXATxU fTuAD6BaI2SWLW5Ea6dXOhkIGqq2IqKDjImBPel3xzGvZJy8kFJd/IJ8od03rrdH3Tbq 5KXU5yRXnmo/xnww080+2OO2SCkKWy6fQWKIL/Ra4We52UcW/y55eaVIiSqO81NQmd5V LCWxnXxA6Zp7qaJQjMUdVU8QqNQkF6+OBTrwIDxMS/Lo8EcxynZyjqR//j9I+4J5pY62 3v9Q== X-Gm-Message-State: AOJu0YwU+WyBslh4iuS2yFY1uyk+EO4ujKVGFvEfuFMBFYHbbisAsdtt eeE4ytLnx/1C4RwODLahD1Pl4E9WADQrXYzYVR1eTkNX/c2tZxFiPuaz9dG2O/631HPAZMUzXia rg4NZ X-Gm-Gg: AR+sD10nAmiW4lY6lAbh5+HMlc3NmmardfZISMYoMAwSTx5K4XCw2QwGtkbdu07x5pO BvLawlNIt8sLBWc4iGsv2ErOhQ4bmScIp33gwS1pQtjbpaH8vFRgnlwS6VPJZ4k8HoxsPSA5j43 +8tGEyXDWlaIjnRRr8VP68a6PmJZOpGrAgW+BcgupnjehLH0tXdZx3aHxjyHiC5XdN/BdeIw4XY SAcCYYcZ9eXybsXhu6Dq4iHy8Jo9cLYWS90GR1GG+HiDyX6gLCj27/4bpgRztNEoPBBq5mtt1By 03NJ0B5nB0IKe/amiLZZDUmQ/IHxS3QuEhxtqUQ7Cletsqy7uLbc6/aLjlj9Jqpo1rPHekGT4CE QMd//Y5fJORqemRv2j6RKRwbj6eN3kScjOJqRKnYAsLV7v+vM5+fhHzJPRm+aHu1YfmmOqSQD9T 5vnU/trDav2pySsEBU76UfjCXvOAPgzRgf35rHEbx8DYLAMxp6IMsNUA211R7bLGIZ9DOedTeZ X-Received: by 2002:a05:6000:250b:b0:47f:7fe0:a287 with SMTP id ffacd0b85a97d-47fec4e739dmr11551387f8f.2.1785933929270; Wed, 05 Aug 2026 05:45:29 -0700 (PDT) From: Andrew Cooper To: xen-devel@lists.xenproject.org Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [PATCH 2/5] x86/nmi: Drop K7_NMI_EVENT Date: Wed, 5 Aug 2026 13:45:22 +0100 Message-Id: <20260805124525.105457-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260805124525.105457-1-andrew.cooper3@citrix.com> References: <20260805124525.105457-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c1860d/1785933930-CC77387B-DFBF17D8/0/0 X-purgate-type: clean X-purgate-size: 1393 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1785933953973158500 This name is misleading. It's not possible to configure NMI or not from the event select register; t= hat comes from the APIC configuration for performance events. This name is "the thing we want to count for the NMI watchdog", but that's clearer to follow when it simply names the event. Drop the indirection. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Teddy Astie --- xen/arch/x86/nmi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index 616bfdbc9029..113e672c4f15 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -102,7 +102,6 @@ static int nmi_active; #define K7_EVNTSEL_OS (1 << 17) #define K7_EVNTSEL_USR (1 << 16) #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76 -#define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING #define K7_EVENT_WIDTH 32 =20 #define P6_EVNTSEL0_ENABLE (1 << 22) @@ -259,7 +258,7 @@ static void setup_k7_watchdog(void) evntsel =3D K7_EVNTSEL_INT | K7_EVNTSEL_OS | K7_EVNTSEL_USR - | K7_NMI_EVENT; + | K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING; =20 wrmsrns(MSR_K7_EVNTSEL0, evntsel); write_watchdog_counter("K7_PERFCTR0"); --=20 2.34.1 From nobody Thu Aug 13 09:18:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1785933950; cv=none; d=zohomail.com; s=zohoarc; b=ChwcJc7Z96vocJfJ8qDDRmvlSUq+sAnfYY8Hv151LvjtsF88h0JxFI+hDpTtOxyY44VGHrwhyZWsm61gS0DRZsvc1tH2/+/Ou2KYfTojIwmi53T52LSdjS2fr8uWecTR/U7IFJftnmaGNOMKuFHVj6ETJU9AXgtYtnRowFHSkko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1785933950; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lqsAtBET9oa8FmQopb1o6zNaXAFCZR7+pOGZSxtba0c=; b=TIoaMwBm+i+sbuzFJiuVBtAhzcaNN96On7VDXQ0dPNvW0Oci/8NX4u02wHfRjYoiUMq9gAVG8aS8W80y/xWbNyOQC79SvrQTVSVlsMKUvrkKg2Y9vWNUDsPM5IL7UCIQpY3VEyDUQHGryVc+sytSzyKcC/tJV4af8MkZIxpueDw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 178593395044836.34626298301612; Wed, 5 Aug 2026 05:45:50 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1383392.1626684 (Exim 4.92) (envelope-from ) id 1wrb01-0004tX-0G; Wed, 05 Aug 2026 12:45:33 +0000 Received: by outflank-mailman (output) from mailman id 1383392.1626684; Wed, 05 Aug 2026 12:45:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wrb00-0004si-Pi; Wed, 05 Aug 2026 12:45:32 +0000 Received: by outflank-mailman (input) for mailman id 1383392; Wed, 05 Aug 2026 12:45:32 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wrazz-0004pu-Sy for xen-devel@lists.xenproject.org; Wed, 05 Aug 2026 12:45:32 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wrazz-004adb-9X for xen-devel@lists.xenproject.org; Wed, 05 Aug 2026 14:45:31 +0200 Received: from [10.42.69.9] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 6a73306b-2eae-0a2a0a5409dd-0a2a4509ba4e-0 for ; Wed, 05 Aug 2026 14:45:31 +0200 Received: from [209.85.221.52] (helo=mail-wr1-f52.google.com) by tlsNG-bad1c0.mxtls.expurgate.net with ESMTPS (eXpurgate 4.57.1) (envelope-from ) id 6a73306b-be1a-0a2a45090019-d155dd34c8a3-3 for ; Wed, 05 Aug 2026 14:45:31 +0200 Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-47f9ab7ee38so496183f8f.2 for ; Wed, 05 Aug 2026 05:45:31 -0700 (PDT) Received: from andrew-laptop.. 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Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Teddy Astie --- xen/arch/x86/nmi.c | 54 ++++++++++++++++++++++++---------------------- 1 file changed, 28 insertions(+), 26 deletions(-) diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index 113e672c4f15..d9d07870a333 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -13,26 +13,25 @@ * Mikael Pettersson : PM converted to driver model. Disable/enable API. */ =20 +#include +#include +#include #include +#include +#include #include #include #include -#include -#include -#include #include -#include #include -#include +#include #include -#include + +#include #include -#include -#include #include +#include #include -#include -#include =20 unsigned int nmi_watchdog =3D NMI_NONE; static unsigned int nmi_hz =3D HZ; @@ -124,10 +123,10 @@ static int nmi_active; #define P4_CCCR_REQUIRED (3<<16) #define P4_CCCR_ESCR_SELECT(N) ((N)<<13) #define P4_CCCR_ENABLE (1<<12) -/*=20 +/* * Set up IQ_PERFCTR0 to behave like a clock, by having IQ_CCCR0 filter * CRU_ESCR0 (with any non-null event selector) through a complemented - * max threshold. [IA32-Vol3, Section 14.9.9]=20 + * max threshold. [IA32-Vol3, Section 14.9.9] */ #define P4_NMI_CRU_ESCR0 P4_ESCR_EVENT_SELECT(0x3F) #define P4_NMI_IQ_CCCR0 \ @@ -182,7 +181,7 @@ void __init check_nmi_watchdog(void) * There's a limit to how slow we can go because writing the perfctr * MSRs only sets the low 32 bits, with the top 8 bits sign-extended * from those, so it's not possible to set up a delay larger than - * 2^31 cycles and smaller than (2^40 - 2^31) cycles.=20 + * 2^31 cycles and smaller than (2^40 - 2^31) cycles. * (Intel SDM, section 18.22.2) */ if ( nmi_watchdog =3D=3D NMI_LOCAL_APIC ) @@ -199,8 +198,9 @@ static void cf_check nmi_timer_fn(void *unused) =20 void disable_lapic_nmi_watchdog(void) { - if (nmi_active <=3D 0) + if ( nmi_active <=3D 0 ) return; + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_AMD: @@ -231,9 +231,7 @@ void disable_lapic_nmi_watchdog(void) =20 static void clear_msr_range(unsigned int base, unsigned int n) { - unsigned int i; - - for (i =3D 0; i < n; i++) + for ( unsigned int i =3D 0; i < n; i++ ) wrmsrns(base + i, 0); } =20 @@ -302,7 +300,7 @@ static void setup_p4_watchdog(void) uint64_t misc_enable; =20 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); - if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL)) + if ( !(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL) ) return; =20 nmi_perfctr_msr =3D MSR_P4_IQ_PERFCTR0; @@ -310,15 +308,18 @@ static void setup_p4_watchdog(void) if ( boot_cpu_data.x86_num_siblings =3D=3D 2 ) nmi_p4_cccr_val |=3D P4_CCCR_OVF_PMI1; =20 - if (!(misc_enable & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) + if ( !(misc_enable & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL) ) clear_msr_range(0x3F1, 2); /* MSR 0x3F0 seems to have a default value of 0xFC00, but current docs doesn't fully define it, so leave it alone for now. */ - if (boot_cpu_data.model >=3D 0x3) { + if ( boot_cpu_data.model >=3D 0x3 ) + { /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */ clear_msr_range(0x3A0, 26); clear_msr_range(0x3BC, 3); - } else { + } + else + { clear_msr_range(0x3A0, 31); } clear_msr_range(0x3C0, 6); @@ -393,7 +394,7 @@ static int cf_check cpu_nmi_callback( } =20 static struct notifier_block cpu_nmi_nfb =3D { - .notifier_call =3D cpu_nmi_callback + .notifier_call =3D cpu_nmi_callback, }; =20 static DEFINE_PER_CPU(unsigned int, last_irq_sums); @@ -444,15 +445,15 @@ bool nmi_watchdog_tick(const struct cpu_user_regs *re= gs) * before doing the oops ... */ this_cpu(alert_counter)++; - if ( this_cpu(alert_counter) =3D=3D opt_watchdog_timeout*nmi_hz ) + if ( this_cpu(alert_counter) =3D=3D opt_watchdog_timeout * nmi_hz ) { console_force_unlock(); printk("Watchdog timer detects that CPU%d is stuck!\n", smp_processor_id()); fatal_trap(regs, 1); } - }=20 - else=20 + } + else { this_cpu(last_irq_sums) =3D sum; this_cpu(alert_counter) =3D 0; @@ -512,7 +513,8 @@ bool nmi_watchdog_tick(const struct cpu_user_regs *regs) void self_nmi(void) { unsigned long flags; - u32 id =3D get_apic_id(); + uint32_t id =3D get_apic_id(); + local_irq_save(flags); apic_wait_icr_idle(); apic_icr_write(APIC_DM_NMI | APIC_DEST_PHYSICAL, id); --=20 2.34.1 From nobody Thu Aug 13 09:18:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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([157.231.70.114]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fec23e533sm8779762f8f.28.2026.08.05.05.45.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 05:45:30 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1785933931; x=1786538731; darn=lists.xenproject.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=gfNjW9ZQ4iFlwv+IcWbWGLC4if7o3p4HypcYr/O3FIo=; b=j4nb/rXoyPeZIvZcycFCLsHvSo8ggmdJdpITXFhun2a5v9dRXpGQL2A2NxMpt/Qn9W N9DLKzOUBQGYqdEE0d/RBGvr+IdX5cRyX4JwviLRX//uP6X2mAImuJL4uEdM9DacYhmx XGI/pVoUGgaquKL0xrLMyEb+v9fwwHbBDiNVg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785933931; x=1786538731; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=gfNjW9ZQ4iFlwv+IcWbWGLC4if7o3p4HypcYr/O3FIo=; b=KAoo6+Itq4TOJ3gJ1u/KPPUvk3VoVb0WIEwo26IBBbdVMjxYynCETrq355IcRPAv92 m90Q2eoyN8ocmGP7B5dN9LDnxrmiLmnE23SpRS861PxVpEhIxeK16eYOr8xY4BbLcHCK JyoUPu0I6R7hvgn1h+JmVMp/5I+RSVloiPb4r0w4JwZy/z8SR7MP8lnD38XJ+Lnupjvh jllPq5dlqa5NVSFuZuLe02EN6og76q0WfxdLxbArI3dxF8YWU0hTotsjIeJjIKhlNfoY ahI2ZIB2undMe6id1YknLLYL5aoa8xvbf+ioE2Vxcz16itmxUUtkxwEBoS7Ma/iogEZy CrGw== X-Gm-Message-State: AOJu0YzxChSpPl1v8167gI4X0BFzEttrU8RrgizWsRzoOwKksnCOTrFh GjpEwHQYB1dc3kszCEww7HYLOsVhgDnqHvTemu3x2mde9pDrJ8XEtMp6Jaz8sFdHXa0xk+F7x5p rpJ8ceRk= X-Gm-Gg: AR+sD11RTdq1lVtRH1x9Xv3nE+TKTYDE2TMO+qn8fN8Suu0x6FMo9e6FrS2cXxcyV3E IZn3Oo9t2vqsRaOF9w+sXJKW43ahJG4vEErGwhvPdy4Sdinp0JqRr3R5FZtB3DJ78PyStXUbXyz FcWZeRNr86g37stLirw5D5nU6IheuOX06SBgi32cv1rLp5+rF/4PsIzVvNuc82Zuh+0F28J2SBf ESyBeXHbVrN2Jr9TtiFcf1IyCICI21XApbZX9gkRzXzyw1N9kltRZwATr05qL67HleERFyGQwaB qX/K01OdPLBODhN9VnhFAcHTpSpwWD+WPBA+Kn/zcDKoDjmMLV9I5gYaRyFRgRDt8bd2AscoscW eChd1+tBDQG9tvUXKlq5xuJMV272afE3UcZ4BlAt6f4TlArRJ1ULKmI96oJkLbBKkfq8eGEXSKD b51I31Tfn2PRc5Wubai2vNgKBTUR+l09RBNcXEfNZonzq0JPu1LeaxligIaDXg8MORwNZnsxLD X-Received: by 2002:adf:f311:0:b0:46e:7f72:b6fe with SMTP id ffacd0b85a97d-47fec523d07mr8462161f8f.19.1785933931038; Wed, 05 Aug 2026 05:45:31 -0700 (PDT) From: Andrew Cooper To: xen-devel@lists.xenproject.org Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [PATCH 4/5] x86/nmi: Check MSR_MISC_ENABLE for all Intel platforms Date: Wed, 5 Aug 2026 13:45:24 +0100 Message-Id: <20260805124525.105457-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260805124525.105457-1-andrew.cooper3@citrix.com> References: <20260805124525.105457-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1785933931-F1EAB2AC-CB6B44DA/0/0 X-purgate-type: clean X-purgate-size: 2470 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1785933957992158500 Right now it's only checked in setup_p4_watchdog(), and not in setup_p6_watchdog(). Perform the check in the common Intel path in setup_apic_nmi_watchdog(), and pass misc_enable as a parameter into setup_p4_watchdog() to aoid reading it twice. Fixes: 0dfba864fbff ("NMI watchdog support in Xen.") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Teddy Astie I presume this bug went unnoticed because watchdog is off-by-default. --- xen/arch/x86/nmi.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index d9d07870a333..a8b0d79c7cf2 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -295,14 +295,8 @@ static void setup_p6_watchdog(unsigned counter) wrmsrns(MSR_P6_EVNTSEL(0), evntsel); } =20 -static void setup_p4_watchdog(void) +static void setup_p4_watchdog(uint64_t misc_enable) { - uint64_t misc_enable; - - rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); - if ( !(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL) ) - return; - nmi_perfctr_msr =3D MSR_P4_IQ_PERFCTR0; nmi_p4_cccr_val =3D P4_NMI_IQ_CCCR0; if ( boot_cpu_data.x86_num_siblings =3D=3D 2 ) @@ -337,6 +331,8 @@ static void setup_p4_watchdog(void) =20 void setup_apic_nmi_watchdog(void) { + uint64_t misc; + if ( nmi_watchdog =3D=3D NMI_NONE ) return; =20 @@ -347,6 +343,14 @@ void setup_apic_nmi_watchdog(void) break; =20 case X86_VENDOR_INTEL: + misc =3D rdmsr(MSR_IA32_MISC_ENABLE); + + if ( !(misc & MSR_IA32_MISC_ENABLE_PERF_AVAIL) ) + { + printk(XENLOG_WARNING "Intel Perfmon unavailable\n"); + goto disable; + } + switch ( boot_cpu_data.family ) { case 6: @@ -355,7 +359,7 @@ void setup_apic_nmi_watchdog(void) : CORE_EVENT_CPU_CLOCKS_NOT_HALTED); break; case 15: - setup_p4_watchdog(); + setup_p4_watchdog(misc); break; } break; @@ -363,6 +367,7 @@ void setup_apic_nmi_watchdog(void) =20 if ( nmi_perfctr_msr =3D=3D 0 ) { + disable: printk(XENLOG_WARNING "Failed to configure NMI watchdog\n"); nmi_watchdog =3D NMI_NONE; return; --=20 2.34.1 From nobody Thu Aug 13 09:18:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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([157.231.70.114]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fec23e533sm8779762f8f.28.2026.08.05.05.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 05:45:31 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1785933933; x=1786538733; darn=lists.xenproject.org; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to:content-type; bh=7770vZRJ4ZFGBtmI51IRg/58qd/H6KqbB1Rxt63P7kE=; b=s304l9ZBXdbG+N90oKjzRFvQmwbyWj3DNzRlz0DMfQbu+SGg5uNeROz1Di0mbsY17P vzz95s/g3mC+b3eZBevM6NbnAueDYHVD5vbpn3vpL604j6HPOUEkKcnLpDCFG3axPKX0 csPDP/lj3vVfRWdOjn/OCrnA/+e73FIOvxqx8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785933933; x=1786538733; h=content-transfer-encoding:content-type:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=7770vZRJ4ZFGBtmI51IRg/58qd/H6KqbB1Rxt63P7kE=; b=a7imZzMVvmwPOexWyxoOz0rHNwS9BLKu+veWRkWG7G1eARk7SU//48VTHsYwKbHH+A 6V2mHK/2oqR+jdoF4iWylfT8hv5Edg7Jpwby73eQkiONGtAImG/LDpvW9F3hH4lkTiJ8 xpaIqs86XASxUh6SSO92QVxi9lHtH6xEbt5r/t7i5JcRIeo3TwyzhUPr66DzjpvqTBIE 6BNoScfRnOcUA5cV2dc1u/1YUJJMnKh2hcip8vAXOdh/sVnxiEtS0o38FVucuk0tz2Zs wv3ef8byUYeX5oUWaxgJj/+floIaj7TSOcijjwDScjLoE5KK5Hv4LoNrSlxyOo+3jjGF AU1g== X-Gm-Message-State: AOJu0Yw3Ijxhg/Lzd+iWM9d+nAvYfjS4Hvk7lZEjq92VlGxyfC5VVEc3 fLrqO5OqB8na8Rbq6FpJ9dD6fhBpRSOCdB1i4s7A+PEC0Jzh16Bex4hVLqeXQFwFq4Ohq+ZxyON AzyP8 X-Gm-Gg: AR+sD12+Wl6Yke9FX6SLwmYr8qt7TjYkamDLyS5rbrZS6SEksDSHIfFFB3Xw/cuHAVG ZNepcxHS2p2q11MoNs3Gsrrl97Kpo9xMnZ+jLwdscRLd4MQIHpa9yxI5JHl+LGHW38uuqWiUvm2 PN801DMn40+kUuI1e40W3RuVPM5qr9q+Nas6zN0jsH/Bc3MWLNbvlpTCI54BgC4shRx1puLlJWP ueaKfmYZuVmixwg/jnLFXzrE55mqPTryWoqNKU4RmhjML5JYpvkbEyLhJbntAmHiIcHC5ou5cCB wNCPTxl3xlsBRKPHgHju7JMywDdFGOOAHRAzrkXWW8vVByRUXm8mbB5VmPSznBvSBEzoqLQGF7d m5pZwvD8sm2uSX0DanNh5HlhBL2vpjQbsHjEFJ92af7qYAjXPap7IGOwEx8zOnfx+EhG1YZ+qlW wbqf/QIJzSZT5zbslif80pjdfbP7WcKHeif9lg+t4nPRCLthTg5oW8j0g7T5Azr9QEt6K6Twr2 X-Received: by 2002:a05:6000:25ca:b0:47f:9568:ebf0 with SMTP id ffacd0b85a97d-47fec52786bmr10833838f8f.23.1785933932021; Wed, 05 Aug 2026 05:45:32 -0700 (PDT) From: Andrew Cooper To: xen-devel@lists.xenproject.org Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie Subject: [PATCH 5/5] x86/nmi: Don't configure EvtSel repeatedly Date: Wed, 5 Aug 2026 13:45:25 +0100 Message-Id: <20260805124525.105457-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260805124525.105457-1-andrew.cooper3@citrix.com> References: <20260805124525.105457-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1785933933-F38BC2AC-84BF9D56/0/0 X-purgate-type: clean X-purgate-size: 3266 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1785933954094158500 In both setup_{k7,p6}_watchdog(), EvtSel0 is first zeroed, then written with everything but the enable bit, then written with the enable bit. setup_p4_watchdog() is slightly more complicated, owing to what appears to be a bug introduced by commit 2a2bd8de16b6 ("Clean up NMI watchdog handler."), which causes a second bit to be temporarily different too. The middle of the three writes is useless in all cases. Drop it. While doing this, rename the 'counter' parameter for setup_p6_watchdog(). It is the event which is passed in; the counter is always counter 0. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Teddy Astie --- xen/arch/x86/nmi.c | 29 +++++++---------------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index a8b0d79c7cf2..a697486b834d 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -246,29 +246,20 @@ static inline void write_watchdog_counter(const char = *descr) =20 static void setup_k7_watchdog(void) { - unsigned int evntsel; - nmi_perfctr_msr =3D MSR_K7_PERFCTR0; =20 clear_msr_range(MSR_K7_EVNTSEL0, 4); clear_msr_range(MSR_K7_PERFCTR0, 4); =20 - evntsel =3D K7_EVNTSEL_INT - | K7_EVNTSEL_OS - | K7_EVNTSEL_USR - | K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING; - - wrmsrns(MSR_K7_EVNTSEL0, evntsel); write_watchdog_counter("K7_PERFCTR0"); apic_write(APIC_LVTPC, APIC_DM_NMI); - evntsel |=3D K7_EVNTSEL_ENABLE; - wrmsrns(MSR_K7_EVNTSEL0, evntsel); + wrmsrns(MSR_K7_EVNTSEL0, + K7_EVNTSEL_ENABLE | K7_EVNTSEL_INT | K7_EVNTSEL_OS | + K7_EVNTSEL_USR | K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING); } =20 -static void setup_p6_watchdog(unsigned counter) +static void setup_p6_watchdog(unsigned int event) { - unsigned int evntsel; - if ( !nmi_p6_event_width && current_cpu_data.cpuid_level >=3D 0xa ) nmi_p6_event_width =3D MASK_EXTR(cpuid_eax(0xa), P6_EVENT_WIDTH_MA= SK); if ( !nmi_p6_event_width ) @@ -283,16 +274,11 @@ static void setup_p6_watchdog(unsigned counter) clear_msr_range(MSR_P6_EVNTSEL(0), 2); clear_msr_range(MSR_P6_PERFCTR(0), 2); =20 - evntsel =3D P6_EVNTSEL_INT - | P6_EVNTSEL_OS - | P6_EVNTSEL_USR - | counter; - - wrmsrns(MSR_P6_EVNTSEL(0), evntsel); write_watchdog_counter("P6_PERFCTR0"); apic_write(APIC_LVTPC, APIC_DM_NMI); - evntsel |=3D P6_EVNTSEL0_ENABLE; - wrmsrns(MSR_P6_EVNTSEL(0), evntsel); + wrmsrns(MSR_P6_EVNTSEL(0), + P6_EVNTSEL0_ENABLE | P6_EVNTSEL_INT | P6_EVNTSEL_OS | + P6_EVNTSEL_USR | event); } =20 static void setup_p4_watchdog(uint64_t misc_enable) @@ -323,7 +309,6 @@ static void setup_p4_watchdog(uint64_t misc_enable) clear_msr_range(MSR_P4_BPU_PERFCTR0, 18); =20 wrmsrl(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0); - wrmsrl(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE); write_watchdog_counter("P4_IQ_COUNTER0"); apic_write(APIC_LVTPC, APIC_DM_NMI); wrmsrl(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val); --=20 2.34.1