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Sun, 26 Jul 2026 12:43:42 -0700 (PDT) X-Received: by 2002:a05:6a21:918c:b0:3bf:6c08:fb85 with SMTP id adf61e73a8af0-3c67e0e92fdmr5593377637.53.1785095022117; Sun, 26 Jul 2026 12:43:42 -0700 (PDT) From: Ze Huang Date: Mon, 27 Jul 2026 03:42:32 +0800 Subject: [PATCH v3 1/2] drm/imx/lcdc: avoid duplicate clk_per enable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260727-drm-simple-kms-removal-v3-1-de36e534f7a1@oss.qualcomm.com> References: <20260727-drm-simple-kms-removal-v3-0-de36e534f7a1@oss.qualcomm.com> In-Reply-To: <20260727-drm-simple-kms-removal-v3-0-de36e534f7a1@oss.qualcomm.com> To: Alexey Brodkin , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Joel Stanley , Andrew Jeffery , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Linus Walleij , Hans de Goede , Alex Lanzano , Oleksandr Andrushchenko , Philipp Zabel , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Marian Cichy Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, Ze Huang X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785095005; l=1575; i=ze.huang@oss.qualcomm.com; s=20260716; h=from:subject:message-id; bh=0iliuiHXJ6h0/St/QGB8FSTuTPg/hKE4ZxbThjkpOEk=; b=nuCUHzR6KH+1G4beZzHutnnOVPquBUhtAMv7nYpAmPcJwkzLDxQbdplnG0zdIkeIj2bMf6cbt akZOj/szyIRD7rXgAh5kCjmvJ221hnITo+m6kuUDxyG75FWxOXTdMnr X-Developer-Key: i=ze.huang@oss.qualcomm.com; a=ed25519; pk=8uGhlZHInA8NXq7G6u/g59qEcwXwuMRI7nBSnT/ijtY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI2MDIwMCBTYWx0ZWRfX4/8l2aa5QjUr dxmOB+Qlp4rV1hMjYbwrKqbOxPXijqepwtE/EXcdb+qpQnp/5EoTda9RL48Qs3bvvqJYGLq91T8 kEkcqg2Iw2cOxhvlIf5wcNA+S3yXOjncC61aqeQRDRsPzXbQOiigCvFk7LsAT6wQ35A8RW2+uQh ED/xzePky9xDR6swiwyMgUGh2WV37a28L4kvuQ2CsciRtThs+T0nBm/BN99odpwCCWqNd4lK/JI j8TQMZW8yg39EJ50POBhWYgalxlkfNIiTVxCMl99WhdRB1pq3TdgyUetEpKAcpefxjU8xbLepYV 2PT6ldCUTNRABfL0K601lBIM4vCxATgwXGz6hGaADPUUMeVYomzOIWbXufCbN+P+vRQmfAoMf8t SIUlTX/xaWWG30oAtcFi09OpPdJ/8L4X5wmIAvzlNo5jpktYJ/4UW9OMJSVz0r/wknGgjPqp8hS oYazRZOTG1FyMhIUUZA== X-Proofpoint-GUID: Mt1kufhGEag4dx8SwNf79keAGnqlhn9v X-Authority-Analysis: v=2.4 cv=S77pBosP c=1 sm=1 tr=0 ts=6a66636f cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=xnl2VaEmiNnR3tlLptkA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: Mt1kufhGEag4dx8SwNf79keAGnqlhn9v X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI2MDIwMCBTYWx0ZWRfX5orI6Ew8FXNg oQ16x0maacREbvArjCnjyyV+ma7UKz5OjhOKBOkFNH8YWAAbnm5w2U8xrbaCpBqLxWzlfNmr3mM bTq2Esx4XAzp0fAU0zZn/jlkDrtYngY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-26_05,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607260200 X-purgate-ID: tlsNG-d25034/1785095025-02CDBA5B-36A3C34A/0/0 X-purgate-type: clean X-purgate-size: 1577 X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1785095075464158500 The simple-KMS helper calls the pipe update after enabling the CRTC. On an enable commit, imx_lcdc_pipe_enable() already programs the mode and enables clk_per. The following pipe update sees the plane move from no CRTC to the active CRTC, treats it as a mode update, and calls imx_lcdc_update_hw_registers() again. That second call has no old CRTC state to disable clk_per first, but it enables clk_per again at the end. The disable path only drops one reference, leaving clk_per enabled after each on/off cycle. Skip the register update from the pipe update path when the CRTC already needs a modeset. The enable path has already programmed the hardware for that commit; keep the event handling in pipe update unchanged. Fixes: c87e859cdeb5 ("drm/imx/lcdc: Implement DRM driver for imx25") Signed-off-by: Ze Huang Acked-by: Thomas Zimmermann --- drivers/gpu/drm/imx/lcdc/imx-lcdc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/imx/lcdc/imx-lcdc.c b/drivers/gpu/drm/imx/lcdc= /imx-lcdc.c index f52832b43aca..81024f7d9e96 100644 --- a/drivers/gpu/drm/imx/lcdc/imx-lcdc.c +++ b/drivers/gpu/drm/imx/lcdc/imx-lcdc.c @@ -311,7 +311,8 @@ static void imx_lcdc_pipe_update(struct drm_simple_disp= lay_pipe *pipe, else if (old_crtc !=3D crtc) mode_changed =3D true; =20 - imx_lcdc_update_hw_registers(pipe, old_state, mode_changed); + if (!drm_atomic_crtc_needs_modeset(crtc->state)) + imx_lcdc_update_hw_registers(pipe, old_state, mode_changed); =20 if (event) { crtc->state->event =3D NULL; --=20 2.43.0 From nobody Sat Sep 26 02:02:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Keep no-scaling plane check and GEM framebuffer prepare callback from simple-KMS path. Wire the vblank lifecycle explicitly with CRTC vblank callbacks and drm_crtc_vblank_on()/drm_crtc_vblank_off(). Use the old CRTC state in the disable path for clock unwinding so the clock reference count remains paired with the previous active state. Signed-off-by: Ze Huang --- drivers/gpu/drm/imx/lcdc/imx-lcdc.c | 264 ++++++++++++++++++++++++++------= ---- 1 file changed, 190 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/imx/lcdc/imx-lcdc.c b/drivers/gpu/drm/imx/lcdc= /imx-lcdc.c index 81024f7d9e96..4835f01954f7 100644 --- a/drivers/gpu/drm/imx/lcdc/imx-lcdc.c +++ b/drivers/gpu/drm/imx/lcdc/imx-lcdc.c @@ -2,6 +2,7 @@ // SPDX-FileCopyrightText: 2020 Marian Cichy =20 #include +#include #include #include #include @@ -14,9 +15,9 @@ #include #include #include +#include #include #include -#include #include #include #include @@ -102,7 +103,9 @@ =20 struct imx_lcdc { struct drm_device drm; - struct drm_simple_display_pipe pipe; + struct drm_plane plane; + struct drm_crtc crtc; + struct drm_encoder encoder; struct drm_connector *connector; void __iomem *base; =20 @@ -135,14 +138,15 @@ static unsigned int imx_lcdc_get_format(unsigned int = drm_format) } } =20 -static void imx_lcdc_update_hw_registers(struct drm_simple_display_pipe *p= ipe, - struct drm_plane_state *old_state, +static void imx_lcdc_update_hw_registers(struct drm_crtc *crtc, + struct drm_crtc_state *old_crtc_state, + struct drm_crtc_state *new_crtc_state, + struct drm_plane_state *new_state, bool mode_set) { - struct drm_crtc *crtc =3D &pipe->crtc; - struct drm_plane_state *new_state =3D pipe->plane.state; + struct imx_lcdc *lcdc =3D imx_lcdc_from_drmdev(crtc->dev); + const struct drm_display_mode *mode =3D &new_crtc_state->mode; struct drm_framebuffer *fb =3D new_state->fb; - struct imx_lcdc *lcdc =3D imx_lcdc_from_drmdev(pipe->crtc.dev); u32 lpcr, lvcr, lhcr; u32 framesize; dma_addr_t addr; @@ -155,24 +159,24 @@ static void imx_lcdc_update_hw_registers(struct drm_s= imple_display_pipe *pipe, return; =20 /* Disable PER clock to make register write possible */ - if (old_state && old_state->crtc && old_state->crtc->enabled) + if (old_crtc_state && old_crtc_state->enable) clk_disable_unprepare(lcdc->clk_per); =20 /* Framesize */ - framesize =3D FIELD_PREP(IMX21LCDC_LSR_XMAX, crtc->mode.hdisplay >> 4) | - FIELD_PREP(IMX21LCDC_LSR_YMAX, crtc->mode.vdisplay); + framesize =3D FIELD_PREP(IMX21LCDC_LSR_XMAX, mode->hdisplay >> 4) | + FIELD_PREP(IMX21LCDC_LSR_YMAX, mode->vdisplay); writel(framesize, lcdc->base + IMX21LCDC_LSR); =20 /* HSYNC */ - lhcr =3D FIELD_PREP(IMX21LCDC_LHCR_HFPORCH, crtc->mode.hsync_start - crtc= ->mode.hdisplay - 1) | - FIELD_PREP(IMX21LCDC_LHCR_HWIDTH, crtc->mode.hsync_end - crtc->mode.hsyn= c_start - 1) | - FIELD_PREP(IMX21LCDC_LHCR_HBPORCH, crtc->mode.htotal - crtc->mode.hsync_= end - 3); + lhcr =3D FIELD_PREP(IMX21LCDC_LHCR_HFPORCH, mode->hsync_start - mode->hdi= splay - 1) | + FIELD_PREP(IMX21LCDC_LHCR_HWIDTH, mode->hsync_end - mode->hsync_start - = 1) | + FIELD_PREP(IMX21LCDC_LHCR_HBPORCH, mode->htotal - mode->hsync_end - 3); writel(lhcr, lcdc->base + IMX21LCDC_LHCR); =20 /* VSYNC */ - lvcr =3D FIELD_PREP(IMX21LCDC_LVCR_VFPORCH, crtc->mode.vsync_start - crtc= ->mode.vdisplay) | - FIELD_PREP(IMX21LCDC_LVCR_VWIDTH, crtc->mode.vsync_end - crtc->mode.vsyn= c_start) | - FIELD_PREP(IMX21LCDC_LVCR_VBPORCH, crtc->mode.vtotal - crtc->mode.vsync_= end); + lvcr =3D FIELD_PREP(IMX21LCDC_LVCR_VFPORCH, mode->vsync_start - mode->vdi= splay) | + FIELD_PREP(IMX21LCDC_LVCR_VWIDTH, mode->vsync_end - mode->vsync_start) | + FIELD_PREP(IMX21LCDC_LVCR_VBPORCH, mode->vtotal - mode->vsync_end); writel(lvcr, lcdc->base + IMX21LCDC_LVCR); =20 lpcr =3D readl(lcdc->base + IMX21LCDC_LPCR); @@ -184,19 +188,20 @@ static void imx_lcdc_update_hw_registers(struct drm_s= imple_display_pipe *pipe, writel(new_state->fb->pitches[0] / 4, lcdc->base + IMX21LCDC_LVPWR); =20 /* Enable PER clock */ - if (new_state->crtc->enabled) + if (new_crtc_state->enable) clk_prepare_enable(lcdc->clk_per); } =20 -static void imx_lcdc_pipe_enable(struct drm_simple_display_pipe *pipe, - struct drm_crtc_state *crtc_state, - struct drm_plane_state *plane_state) +static void imx_lcdc_crtc_helper_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) { int ret; int clk_div; int bpp; - struct imx_lcdc *lcdc =3D imx_lcdc_from_drmdev(pipe->crtc.dev); - struct drm_display_mode *mode =3D &pipe->crtc.mode; + struct imx_lcdc *lcdc =3D imx_lcdc_from_drmdev(crtc->dev); + struct drm_crtc_state *cstate =3D drm_atomic_get_new_crtc_state(commit, c= rtc); + struct drm_plane_state *pstate =3D drm_atomic_get_new_plane_state(commit,= &lcdc->plane); + struct drm_display_mode *mode =3D &cstate->mode; struct drm_display_info *disp_info =3D &lcdc->connector->display_info; const int hsync_pol =3D (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : 1; const int vsync_pol =3D (mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : 1; @@ -207,7 +212,7 @@ static void imx_lcdc_pipe_enable(struct drm_simple_disp= lay_pipe *pipe, =20 clk_div =3D DIV_ROUND_CLOSEST_ULL(clk_get_rate(lcdc->clk_per), mode->clock * 1000); - bpp =3D imx_lcdc_get_format(plane_state->fb->format->format); + bpp =3D imx_lcdc_get_format(pstate->fb->format->format); =20 writel(FIELD_PREP(IMX21LCDC_LPCR_PCD, clk_div - 1) | FIELD_PREP(IMX21LCDC_LPCR_LPPOL, hsync_pol) | @@ -231,40 +236,46 @@ static void imx_lcdc_pipe_enable(struct drm_simple_di= splay_pipe *pipe, =20 ret =3D clk_prepare_enable(lcdc->clk_ipg); if (ret) { - dev_err(pipe->crtc.dev->dev, "Cannot enable ipg clock: %pe\n", ERR_PTR(r= et)); + dev_err(crtc->dev->dev, "Cannot enable ipg clock: %pe\n", ERR_PTR(ret)); return; } ret =3D clk_prepare_enable(lcdc->clk_ahb); if (ret) { - dev_err(pipe->crtc.dev->dev, "Cannot enable ahb clock: %pe\n", ERR_PTR(r= et)); + dev_err(crtc->dev->dev, "Cannot enable ahb clock: %pe\n", ERR_PTR(ret)); =20 clk_disable_unprepare(lcdc->clk_ipg); =20 return; } =20 - imx_lcdc_update_hw_registers(pipe, NULL, true); + imx_lcdc_update_hw_registers(crtc, NULL, cstate, pstate, true); =20 /* Enable VBLANK Interrupt */ writel(INTR_EOF, lcdc->base + IMX21LCDC_LIER); + + drm_crtc_vblank_on(crtc); } =20 -static void imx_lcdc_pipe_disable(struct drm_simple_display_pipe *pipe) +static void imx_lcdc_crtc_helper_atomic_disable(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) { - struct imx_lcdc *lcdc =3D imx_lcdc_from_drmdev(pipe->crtc.dev); - struct drm_crtc *crtc =3D &lcdc->pipe.crtc; + struct drm_crtc_state *old_crtc_state =3D drm_atomic_get_old_crtc_state(c= ommit, crtc); + struct drm_crtc_state *new_crtc_state =3D drm_atomic_get_new_crtc_state(c= ommit, crtc); + struct imx_lcdc *lcdc =3D imx_lcdc_from_drmdev(crtc->dev); struct drm_pending_vblank_event *event; =20 + drm_crtc_vblank_off(crtc); + clk_disable_unprepare(lcdc->clk_ahb); clk_disable_unprepare(lcdc->clk_ipg); =20 - if (pipe->crtc.enabled) + if (old_crtc_state->enable) clk_disable_unprepare(lcdc->clk_per); =20 spin_lock_irq(&lcdc->drm.event_lock); - event =3D crtc->state->event; + event =3D new_crtc_state->event; if (event) { - crtc->state->event =3D NULL; + new_crtc_state->event =3D NULL; drm_crtc_send_vblank_event(crtc, event); } spin_unlock_irq(&lcdc->drm.event_lock); @@ -273,66 +284,151 @@ static void imx_lcdc_pipe_disable(struct drm_simple_= display_pipe *pipe) writel(0, lcdc->base + IMX21LCDC_LIER); } =20 -static int imx_lcdc_pipe_check(struct drm_simple_display_pipe *pipe, - struct drm_plane_state *plane_state, - struct drm_crtc_state *crtc_state) +static int imx_lcdc_crtc_helper_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) { + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(commi= t, crtc); + struct drm_crtc_state *old_crtc_state =3D drm_atomic_get_old_crtc_state(c= ommit, crtc); const struct drm_display_mode *mode =3D &crtc_state->mode; - const struct drm_display_mode *old_mode =3D &pipe->crtc.state->mode; + const struct drm_display_mode *old_mode =3D &old_crtc_state->mode; + int ret; =20 - if (mode->hdisplay < LCDC_MIN_XRES || mode->hdisplay > LCDC_MAX_XRES || - mode->vdisplay < LCDC_MIN_YRES || mode->vdisplay > LCDC_MAX_YRES || - mode->hdisplay % 0x10) { /* must be multiple of 16 */ - drm_err(pipe->crtc.dev, "unsupported display mode (%u x %u)\n", + if (crtc_state->enable) { + ret =3D drm_atomic_helper_check_crtc_primary_plane(crtc_state); + if (ret) + return ret; + } + + if (crtc_state->enable && + (mode->hdisplay < LCDC_MIN_XRES || mode->hdisplay > LCDC_MAX_XRES || + mode->vdisplay < LCDC_MIN_YRES || mode->vdisplay > LCDC_MAX_YRES || + mode->hdisplay % 0x10)) { /* must be multiple of 16 */ + drm_err(crtc->dev, "unsupported display mode (%u x %u)\n", mode->hdisplay, mode->vdisplay); return -EINVAL; } =20 - crtc_state->mode_changed =3D - old_mode->hdisplay !=3D mode->hdisplay || - old_mode->vdisplay !=3D mode->vdisplay; + if (old_mode->hdisplay !=3D mode->hdisplay || + old_mode->vdisplay !=3D mode->vdisplay) + crtc_state->mode_changed =3D true; =20 - return 0; + return drm_atomic_add_affected_planes(commit, crtc); } =20 -static void imx_lcdc_pipe_update(struct drm_simple_display_pipe *pipe, - struct drm_plane_state *old_state) +static void imx_lcdc_plane_helper_atomic_update(struct drm_plane *plane, + struct drm_atomic_commit *commit) { - struct drm_crtc *crtc =3D &pipe->crtc; - struct drm_pending_vblank_event *event =3D crtc->state->event; - struct drm_plane_state *new_state =3D pipe->plane.state; + struct drm_plane_state *old_state =3D drm_atomic_get_old_plane_state(comm= it, plane); + struct drm_plane_state *new_state =3D drm_atomic_get_new_plane_state(comm= it, plane); + struct drm_crtc *crtc =3D new_state->crtc; + struct drm_crtc_state *old_crtc_state =3D NULL; + struct drm_crtc_state *new_crtc_state; struct drm_framebuffer *fb =3D new_state->fb; struct drm_framebuffer *old_fb =3D old_state->fb; struct drm_crtc *old_crtc =3D old_state->crtc; bool mode_changed =3D false; =20 + if (!fb || !crtc) + return; + + if (old_crtc) + old_crtc_state =3D drm_atomic_get_old_crtc_state(commit, old_crtc); + + new_crtc_state =3D drm_atomic_get_new_crtc_state(commit, crtc); + if (!new_crtc_state) + return; + if (old_fb && old_fb->format !=3D fb->format) mode_changed =3D true; else if (old_crtc !=3D crtc) mode_changed =3D true; =20 - if (!drm_atomic_crtc_needs_modeset(crtc->state)) - imx_lcdc_update_hw_registers(pipe, old_state, mode_changed); + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + imx_lcdc_update_hw_registers(crtc, old_crtc_state, new_crtc_state, + new_state, mode_changed); +} =20 - if (event) { - crtc->state->event =3D NULL; +static int imx_lcdc_plane_helper_atomic_check(struct drm_plane *plane, + struct drm_atomic_commit *commit) +{ + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(co= mmit, plane); + struct drm_crtc_state *crtc_state =3D NULL; + + if (plane_state->crtc) { + crtc_state =3D drm_atomic_get_crtc_state(commit, plane_state->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } =20 - spin_lock_irq(&crtc->dev->event_lock); + return drm_atomic_helper_check_plane_state(plane_state, crtc_state, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, + false, false); +} =20 - if (crtc->state->active && drm_crtc_vblank_get(crtc) =3D=3D 0) - drm_crtc_arm_vblank_event(crtc, event); - else - drm_crtc_send_vblank_event(crtc, event); +static const struct drm_plane_helper_funcs imx_lcdc_plane_helper_funcs =3D= { + .prepare_fb =3D drm_gem_plane_helper_prepare_fb, + .atomic_check =3D imx_lcdc_plane_helper_atomic_check, + .atomic_update =3D imx_lcdc_plane_helper_atomic_update, +}; =20 - spin_unlock_irq(&crtc->dev->event_lock); - } +static const struct drm_plane_funcs imx_lcdc_plane_funcs =3D { + .update_plane =3D drm_atomic_helper_update_plane, + .disable_plane =3D drm_atomic_helper_disable_plane, + .destroy =3D drm_plane_cleanup, + .reset =3D drm_atomic_helper_plane_reset, + .atomic_duplicate_state =3D drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_plane_destroy_state, +}; + +static void imx_lcdc_crtc_helper_atomic_flush(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) +{ + struct drm_crtc_state *new_crtc_state =3D drm_atomic_get_new_crtc_state(c= ommit, crtc); + struct drm_pending_vblank_event *event =3D new_crtc_state->event; + + if (!event) + return; + + new_crtc_state->event =3D NULL; + + spin_lock_irq(&crtc->dev->event_lock); + if (new_crtc_state->active && drm_crtc_vblank_get(crtc) =3D=3D 0) + drm_crtc_arm_vblank_event(crtc, event); + else + drm_crtc_send_vblank_event(crtc, event); + spin_unlock_irq(&crtc->dev->event_lock); } =20 -static const struct drm_simple_display_pipe_funcs imx_lcdc_pipe_funcs =3D { - .enable =3D imx_lcdc_pipe_enable, - .disable =3D imx_lcdc_pipe_disable, - .check =3D imx_lcdc_pipe_check, - .update =3D imx_lcdc_pipe_update, +static const struct drm_crtc_helper_funcs imx_lcdc_crtc_helper_funcs =3D { + .atomic_check =3D imx_lcdc_crtc_helper_atomic_check, + .atomic_enable =3D imx_lcdc_crtc_helper_atomic_enable, + .atomic_disable =3D imx_lcdc_crtc_helper_atomic_disable, + .atomic_flush =3D imx_lcdc_crtc_helper_atomic_flush, +}; + +static int imx_lcdc_crtc_enable_vblank(struct drm_crtc *crtc) +{ + return 0; +} + +static void imx_lcdc_crtc_disable_vblank(struct drm_crtc *crtc) +{ +} + +static const struct drm_crtc_funcs imx_lcdc_crtc_funcs =3D { + .reset =3D drm_atomic_helper_crtc_reset, + .destroy =3D drm_crtc_cleanup, + .set_config =3D drm_atomic_helper_set_config, + .page_flip =3D drm_atomic_helper_page_flip, + .atomic_duplicate_state =3D drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_crtc_destroy_state, + .enable_vblank =3D imx_lcdc_crtc_enable_vblank, + .disable_vblank =3D imx_lcdc_crtc_disable_vblank, +}; + +static const struct drm_encoder_funcs imx_lcdc_encoder_funcs =3D { + .destroy =3D drm_encoder_cleanup, }; =20 static const struct drm_mode_config_funcs imx_lcdc_mode_config_funcs =3D { @@ -370,7 +466,7 @@ MODULE_DEVICE_TABLE(of, imx_lcdc_of_dev_id); static irqreturn_t imx_lcdc_irq_handler(int irq, void *arg) { struct imx_lcdc *lcdc =3D arg; - struct drm_crtc *crtc =3D &lcdc->pipe.crtc; + struct drm_crtc *crtc =3D &lcdc->crtc; unsigned int status; =20 status =3D readl(lcdc->base + IMX21LCDC_LISR); @@ -388,6 +484,9 @@ static int imx_lcdc_probe(struct platform_device *pdev) struct imx_lcdc *lcdc; struct drm_device *drm; struct drm_bridge *bridge; + struct drm_plane *plane; + struct drm_crtc *crtc; + struct drm_encoder *encoder; int irq; int ret; struct device *dev =3D &pdev->dev; @@ -429,23 +528,40 @@ static int imx_lcdc_probe(struct platform_device *pde= v) if (ret) return dev_err_probe(dev, ret, "Cannot initialize mode configuration str= ucture\n"); =20 - /* CRTC, Plane, Encoder */ - ret =3D drm_simple_display_pipe_init(drm, &lcdc->pipe, - &imx_lcdc_pipe_funcs, - imx_lcdc_formats, - ARRAY_SIZE(imx_lcdc_formats), NULL, NULL); + plane =3D &lcdc->plane; + ret =3D drm_universal_plane_init(drm, plane, 0, + &imx_lcdc_plane_funcs, + imx_lcdc_formats, + ARRAY_SIZE(imx_lcdc_formats), + NULL, + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret < 0) + return dev_err_probe(drm->dev, ret, "Cannot initialize primary plane\n"); + drm_plane_helper_add(plane, &imx_lcdc_plane_helper_funcs); + + crtc =3D &lcdc->crtc; + ret =3D drm_crtc_init_with_planes(drm, crtc, plane, NULL, + &imx_lcdc_crtc_funcs, NULL); + if (ret < 0) + return dev_err_probe(drm->dev, ret, "Cannot initialize CRTC\n"); + drm_crtc_helper_add(crtc, &imx_lcdc_crtc_helper_funcs); + + encoder =3D &lcdc->encoder; + ret =3D drm_encoder_init(drm, encoder, &imx_lcdc_encoder_funcs, + DRM_MODE_ENCODER_NONE, NULL); if (ret < 0) - return dev_err_probe(drm->dev, ret, "Cannot setup simple display pipe\n"= ); + return dev_err_probe(drm->dev, ret, "Cannot initialize encoder\n"); + encoder->possible_crtcs =3D drm_crtc_mask(crtc); =20 ret =3D drm_vblank_init(drm, drm->mode_config.num_crtc); if (ret < 0) return dev_err_probe(drm->dev, ret, "Failed to initialize vblank\n"); =20 - ret =3D drm_bridge_attach(&lcdc->pipe.encoder, bridge, NULL, DRM_BRIDGE_A= TTACH_NO_CONNECTOR); + ret =3D drm_bridge_attach(encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CON= NECTOR); if (ret) return dev_err_probe(drm->dev, ret, "Cannot attach bridge\n"); =20 - lcdc->connector =3D drm_bridge_connector_init(drm, &lcdc->pipe.encoder); + lcdc->connector =3D drm_bridge_connector_init(drm, encoder); if (IS_ERR(lcdc->connector)) return dev_err_probe(drm->dev, PTR_ERR(lcdc->connector), "Cannot init br= idge connector\n"); =20 --=20 2.43.0