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a=ed25519-sha256; t=1785095128; l=13083; i=ze.huang@oss.qualcomm.com; s=20260716; h=from:subject:message-id; bh=u7exUdyCprg8S9F0jxX38ipcgKHv/vnrTEoFU9vPkn0=; b=ZZ9Plhe5vhdeps49o98fJZwGYMXe7qfovRpPLQtu3Ndk8ZaA/xZ5h5iF+eVEKTBGql3NdYneD e8qZB80aBZwDC1tqIMZQu2S2jeS6nDQM6Y2Hd/QRPAINQ4pNhlPy2B5 X-Developer-Key: i=ze.huang@oss.qualcomm.com; a=ed25519; pk=8uGhlZHInA8NXq7G6u/g59qEcwXwuMRI7nBSnT/ijtY= X-Authority-Analysis: v=2.4 cv=Jr3Bas4C c=1 sm=1 tr=0 ts=6a6663ea cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=f2ANGF4ctf8G8blR-OgA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI2MDIwMCBTYWx0ZWRfX2dvnC/dk9Jr3 knbRY46gf6DgHWqRZCVUdycQq+g+a4ORVnr+fPMMA0T3ELLJofe4asNaRNokUJIp4BFi14Ggrgd 8EUBhQahCbIYJAOR7262y5fCNR1YsVU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI2MDIwMCBTYWx0ZWRfXywKQqReuKmHK tkE9NlH8numOLQLTcNg/1FsD260kuIfB93CEr7tiCT2gB6/1HWCYnEW4WapljuMJspZWVTPsgLP nnQuwaIqV2G/DiaP9fV6iCrGq947pyVr3lPm5BLhpeLr0s3J5bNtcfklOIYQ3C67nVk0lhXYd6F yA09U2v7txwChbBd6/wLdLPv4Y9pBupZzQ1NZoqx6qkyjbKyOf+eLIt1FnAvMStJIwQQDoQdSsq 81MXtbTlOmiFBZQQkDO2NvBAQiB5dQx0oWYCmQokPMKUGK9/T10p/eXgfdDchKvMeFRKEeadW7K nsq8l1yo9KSmdTihu5wx+WTG/zY+rA06AML2elnqqWDrK6Syp9+Wwb73jVb8GwLOkhibfWGH+Id uUYUgasaswmdYY+NQSUxcNEeuE1h4k094/v3JhJsWFS5creTJ3eGuh2hoa4hGZeatRmlZVUIRb4 xWOrdNKNtJhK+1gw03g== X-Proofpoint-ORIG-GUID: VRCMqVrlbJxXh_ti9MtkMi7glgiwHziF X-Proofpoint-GUID: VRCMqVrlbJxXh_ti9MtkMi7glgiwHziF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-26_05,2026-07-24_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 malwarescore=0 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607260200 X-purgate-ID: tlsNG-bad1c0/1785095149-BCECE034-5D14B0E9/0/0 X-purgate-type: clean X-purgate-size: 13085 X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1785095173816158500 Instantiate the primary plane, CRTC and encoder directly and wire them up with standard atomic helpers. Move the simple-pipe callbacks into explicit plane and CRTC helper callbacks. Use commit-local CRTC and plane state in the CRTC enable path for mode and pixel-format programming. Handle missing remote encoder nodes explicitly and take the CRTC modeset lock while reading CRTC state from debugfs. Signed-off-by: Ze Huang --- Changes in v3: - Use commit-local CRTC and plane state in the CRTC enable path. - Handle missing remote encoder nodes explicitly. - Lock CRTC state access in debugfs. --- drivers/gpu/drm/tiny/arcpgu.c | 201 ++++++++++++++++++++++++++++++++------= ---- 1 file changed, 152 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/tiny/arcpgu.c b/drivers/gpu/drm/tiny/arcpgu.c index c93d61ac0bb7..19a943f5f792 100644 --- a/drivers/gpu/drm/tiny/arcpgu.c +++ b/drivers/gpu/drm/tiny/arcpgu.c @@ -8,6 +8,7 @@ #include =20 #include +#include #include #include #include @@ -17,12 +18,13 @@ #include #include #include +#include #include #include #include #include +#include #include -#include #include #include #include @@ -52,13 +54,16 @@ struct arcpgu_drm_private { struct drm_device drm; void __iomem *regs; struct clk *clk; - struct drm_simple_display_pipe pipe; + struct drm_plane plane; + struct drm_crtc crtc; + struct drm_encoder encoder; struct drm_connector sim_conn; }; =20 -#define dev_to_arcpgu(x) container_of(x, struct arcpgu_drm_private, drm) - -#define pipe_to_arcpgu_priv(x) container_of(x, struct arcpgu_drm_private, = pipe) +static inline struct arcpgu_drm_private *dev_to_arcpgu(struct drm_device *= drm) +{ + return container_of(drm, struct arcpgu_drm_private, drm); +} =20 static inline void arc_pgu_write(struct arcpgu_drm_private *arcpgu, unsigned int reg, u32 value) @@ -115,9 +120,10 @@ static const u32 arc_pgu_supported_formats[] =3D { DRM_FORMAT_ARGB8888, }; =20 -static void arc_pgu_set_pxl_fmt(struct arcpgu_drm_private *arcpgu) +static void arc_pgu_set_pxl_fmt(struct arcpgu_drm_private *arcpgu, + const struct drm_plane_state *plane_state) { - const struct drm_framebuffer *fb =3D arcpgu->pipe.plane.state->fb; + const struct drm_framebuffer *fb =3D plane_state->fb; uint32_t pixel_format =3D fb->format->format; u32 format =3D DRM_FORMAT_INVALID; int i; @@ -139,10 +145,10 @@ static void arc_pgu_set_pxl_fmt(struct arcpgu_drm_pri= vate *arcpgu) arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl); } =20 -static enum drm_mode_status arc_pgu_mode_valid(struct drm_simple_display_p= ipe *pipe, - const struct drm_display_mode *mode) +static enum drm_mode_status arcpgu_crtc_helper_mode_valid(struct drm_crtc = *crtc, + const struct drm_display_mode *mode) { - struct arcpgu_drm_private *arcpgu =3D pipe_to_arcpgu_priv(pipe); + struct arcpgu_drm_private *arcpgu =3D dev_to_arcpgu(crtc->dev); long rate, clk_rate =3D mode->clock * 1000; long diff =3D clk_rate / 200; /* +-0.5% allowed by HDMI spec */ =20 @@ -153,9 +159,11 @@ static enum drm_mode_status arc_pgu_mode_valid(struct = drm_simple_display_pipe *p return MODE_NOCLOCK; } =20 -static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu) +static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu, + struct drm_crtc_state *crtc_state, + struct drm_plane_state *plane_state) { - struct drm_display_mode *m =3D &arcpgu->pipe.crtc.state->adjusted_mode; + struct drm_display_mode *m =3D &crtc_state->adjusted_mode; u32 val; =20 arc_pgu_write(arcpgu, ARCPGU_REG_FMT, @@ -189,18 +197,19 @@ static void arc_pgu_mode_set(struct arcpgu_drm_privat= e *arcpgu) arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0); arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1); =20 - arc_pgu_set_pxl_fmt(arcpgu); + arc_pgu_set_pxl_fmt(arcpgu, plane_state); =20 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000); } =20 -static void arc_pgu_enable(struct drm_simple_display_pipe *pipe, - struct drm_crtc_state *crtc_state, - struct drm_plane_state *plane_state) +static void arcpgu_crtc_helper_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) { - struct arcpgu_drm_private *arcpgu =3D pipe_to_arcpgu_priv(pipe); + struct arcpgu_drm_private *arcpgu =3D dev_to_arcpgu(crtc->dev); + struct drm_plane_state *pstate =3D drm_atomic_get_new_plane_state(commit,= &arcpgu->plane); + struct drm_crtc_state *cstate =3D drm_atomic_get_new_crtc_state(commit, c= rtc); =20 - arc_pgu_mode_set(arcpgu); + arc_pgu_mode_set(arcpgu, cstate, pstate); =20 clk_prepare_enable(arcpgu->clk); arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, @@ -208,9 +217,10 @@ static void arc_pgu_enable(struct drm_simple_display_p= ipe *pipe, ARCPGU_CTRL_ENABLE_MASK); } =20 -static void arc_pgu_disable(struct drm_simple_display_pipe *pipe) +static void arcpgu_crtc_helper_atomic_disable(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) { - struct arcpgu_drm_private *arcpgu =3D pipe_to_arcpgu_priv(pipe); + struct arcpgu_drm_private *arcpgu =3D dev_to_arcpgu(crtc->dev); =20 clk_disable_unprepare(arcpgu->clk); arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, @@ -218,27 +228,21 @@ static void arc_pgu_disable(struct drm_simple_display= _pipe *pipe) ~ARCPGU_CTRL_ENABLE_MASK); } =20 -static void arc_pgu_update(struct drm_simple_display_pipe *pipe, - struct drm_plane_state *state) +static void arcpgu_plane_helper_atomic_update(struct drm_plane *plane, + struct drm_atomic_commit *commit) { + struct drm_plane_state *pstate =3D drm_atomic_get_new_plane_state(commit,= plane); struct arcpgu_drm_private *arcpgu; struct drm_gem_dma_object *gem; =20 - if (!pipe->plane.state->fb) + if (!pstate->fb) return; =20 - arcpgu =3D pipe_to_arcpgu_priv(pipe); - gem =3D drm_fb_dma_get_gem_obj(pipe->plane.state->fb, 0); + arcpgu =3D dev_to_arcpgu(plane->dev); + gem =3D drm_fb_dma_get_gem_obj(pstate->fb, 0); arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->dma_addr); } =20 -static const struct drm_simple_display_pipe_funcs arc_pgu_pipe_funcs =3D { - .update =3D arc_pgu_update, - .mode_valid =3D arc_pgu_mode_valid, - .enable =3D arc_pgu_enable, - .disable =3D arc_pgu_disable, -}; - static const struct drm_mode_config_funcs arcpgu_drm_modecfg_funcs =3D { .fb_create =3D drm_gem_fb_create, .atomic_check =3D drm_atomic_helper_check, @@ -247,6 +251,74 @@ static const struct drm_mode_config_funcs arcpgu_drm_m= odecfg_funcs =3D { =20 DEFINE_DRM_GEM_DMA_FOPS(arcpgu_drm_ops); =20 +static int arcpgu_plane_helper_atomic_check(struct drm_plane *plane, + struct drm_atomic_commit *commit) +{ + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(co= mmit, plane); + struct drm_crtc_state *crtc_state =3D NULL; + + if (plane_state->crtc) { + crtc_state =3D drm_atomic_get_crtc_state(commit, plane_state->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + return drm_atomic_helper_check_plane_state(plane_state, crtc_state, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, + false, false); +} + +static const struct drm_plane_helper_funcs arcpgu_plane_helper_funcs =3D { + .prepare_fb =3D drm_gem_plane_helper_prepare_fb, + .atomic_check =3D arcpgu_plane_helper_atomic_check, + .atomic_update =3D arcpgu_plane_helper_atomic_update, +}; + +static const struct drm_plane_funcs arcpgu_plane_funcs =3D { + .update_plane =3D drm_atomic_helper_update_plane, + .disable_plane =3D drm_atomic_helper_disable_plane, + .destroy =3D drm_plane_cleanup, + .reset =3D drm_atomic_helper_plane_reset, + .atomic_duplicate_state =3D drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_plane_destroy_state, +}; + +static int arcpgu_crtc_helper_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) +{ + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(commi= t, crtc); + int ret; + + if (crtc_state->enable) { + ret =3D drm_atomic_helper_check_crtc_primary_plane(crtc_state); + if (ret) + return ret; + } + + return drm_atomic_add_affected_planes(commit, crtc); +} + +static const struct drm_crtc_helper_funcs arcpgu_crtc_helper_funcs =3D { + .mode_valid =3D arcpgu_crtc_helper_mode_valid, + .atomic_check =3D arcpgu_crtc_helper_atomic_check, + .atomic_enable =3D arcpgu_crtc_helper_atomic_enable, + .atomic_disable =3D arcpgu_crtc_helper_atomic_disable, +}; + +static const struct drm_crtc_funcs arcpgu_crtc_funcs =3D { + .reset =3D drm_atomic_helper_crtc_reset, + .destroy =3D drm_crtc_cleanup, + .set_config =3D drm_atomic_helper_set_config, + .page_flip =3D drm_atomic_helper_page_flip, + .atomic_duplicate_state =3D drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_crtc_destroy_state, +}; + +static const struct drm_encoder_funcs arcpgu_encoder_funcs =3D { + .destroy =3D drm_encoder_cleanup, +}; + static int arcpgu_load(struct arcpgu_drm_private *arcpgu) { struct platform_device *pdev =3D to_platform_device(arcpgu->drm.dev); @@ -254,6 +326,9 @@ static int arcpgu_load(struct arcpgu_drm_private *arcpg= u) struct device_node *endpoint_node =3D NULL; struct drm_connector *connector =3D NULL; struct drm_device *drm =3D &arcpgu->drm; + struct drm_plane *plane; + struct drm_encoder *encoder; + struct drm_crtc *crtc; int ret; =20 arcpgu->clk =3D devm_clk_get(drm->dev, "pxlclk"); @@ -285,6 +360,30 @@ static int arcpgu_load(struct arcpgu_drm_private *arcp= gu) if (dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32))) return -ENODEV; =20 + plane =3D &arcpgu->plane; + ret =3D drm_universal_plane_init(drm, plane, 0, + &arcpgu_plane_funcs, + arc_pgu_supported_formats, + ARRAY_SIZE(arc_pgu_supported_formats), + NULL, + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) + return ret; + drm_plane_helper_add(plane, &arcpgu_plane_helper_funcs); + + crtc =3D &arcpgu->crtc; + ret =3D drm_crtc_init_with_planes(drm, crtc, plane, NULL, + &arcpgu_crtc_funcs, NULL); + if (ret) + return ret; + drm_crtc_helper_add(crtc, &arcpgu_crtc_helper_funcs); + + encoder =3D &arcpgu->encoder; + ret =3D drm_encoder_init(drm, encoder, &arcpgu_encoder_funcs, DRM_MODE_EN= CODER_NONE, NULL); + if (ret) + return ret; + encoder->possible_crtcs =3D drm_crtc_mask(crtc); + /* * There is only one output port inside each device. It is linked with * encoder endpoint. @@ -293,29 +392,26 @@ static int arcpgu_load(struct arcpgu_drm_private *arc= pgu) if (endpoint_node) { encoder_node =3D of_graph_get_remote_port_parent(endpoint_node); of_node_put(endpoint_node); - } else { - connector =3D &arcpgu->sim_conn; - dev_info(drm->dev, "no encoder found. Assumed virtual LCD on simulation = platform\n"); - ret =3D arcpgu_drm_sim_init(drm, connector); - if (ret < 0) - return ret; - } + if (!encoder_node) + return -ENODEV; =20 - ret =3D drm_simple_display_pipe_init(drm, &arcpgu->pipe, &arc_pgu_pipe_fu= ncs, - arc_pgu_supported_formats, - ARRAY_SIZE(arc_pgu_supported_formats), - NULL, connector); - if (ret) - return ret; - - if (encoder_node) { /* Locate drm bridge from the hdmi encoder DT node */ struct drm_bridge *bridge __free(drm_bridge_put) =3D of_drm_find_and_get_bridge(encoder_node); if (!bridge) return -EPROBE_DEFER; =20 - ret =3D drm_simple_display_pipe_attach_bridge(&arcpgu->pipe, bridge); + ret =3D drm_bridge_attach(encoder, bridge, NULL, 0); + if (ret) + return ret; + } else { + connector =3D &arcpgu->sim_conn; + dev_info(drm->dev, "no encoder found. Assumed virtual LCD on simulation = platform\n"); + ret =3D arcpgu_drm_sim_init(drm, connector); + if (ret < 0) + return ret; + + ret =3D drm_connector_attach_encoder(connector, encoder); if (ret) return ret; } @@ -342,7 +438,14 @@ static int arcpgu_show_pxlclock(struct seq_file *m, vo= id *arg) struct drm_device *drm =3D node->minor->dev; struct arcpgu_drm_private *arcpgu =3D dev_to_arcpgu(drm); unsigned long clkrate =3D clk_get_rate(arcpgu->clk); - unsigned long mode_clock =3D arcpgu->pipe.crtc.mode.crtc_clock * 1000; + unsigned long mode_clock; + int ret; + + ret =3D drm_modeset_lock_single_interruptible(&arcpgu->crtc.mutex); + if (ret) + return ret; + mode_clock =3D arcpgu->crtc.state->mode.crtc_clock * 1000; + drm_modeset_unlock(&arcpgu->crtc.mutex); =20 seq_printf(m, "hw : %lu\n", clkrate); seq_printf(m, "mode: %lu\n", mode_clock); --=20 2.43.0 From nobody Tue Aug 25 00:45:24 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Move callbacks to plane and CRTC helpers, and wire vblank handling through drm_crtc_funcs. Move page-flip event handling from plane atomic_update() to CRTC atomic_flush(). Use commit-local CRTC and plane state when programming mode and pixel format in the CRTC enable path. Signed-off-by: Ze Huang --- Changes in v3: - Use commit-local CRTC and plane state in the CRTC enable path. - Make the aspeed container helper static inline. --- drivers/gpu/drm/aspeed/aspeed_gfx.h | 11 +- drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 203 ++++++++++++++++++++++-----= ---- drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 3 +- 3 files changed, 157 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h b/drivers/gpu/drm/aspeed/a= speed_gfx.h index 4e6a442c3886..273528d30b4c 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h @@ -2,7 +2,6 @@ /* Copyright 2018 IBM Corporation */ =20 #include -#include =20 struct aspeed_gfx { struct drm_device drm; @@ -17,10 +16,16 @@ struct aspeed_gfx { u32 throd_val; u32 scan_line_max; =20 - struct drm_simple_display_pipe pipe; + struct drm_plane plane; + struct drm_crtc crtc; + struct drm_encoder encoder; struct drm_connector connector; }; -#define to_aspeed_gfx(x) container_of(x, struct aspeed_gfx, drm) + +static inline struct aspeed_gfx *to_aspeed_gfx(struct drm_device *drm) +{ + return container_of(drm, struct aspeed_gfx, drm); +} =20 int aspeed_gfx_create_pipe(struct drm_device *drm); int aspeed_gfx_create_output(struct drm_device *drm); diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/asp= eed/aspeed_gfx_crtc.c index 7877a57b8e26..e8c9a6040d75 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c @@ -5,6 +5,8 @@ #include #include =20 +#include +#include #include #include #include @@ -12,22 +14,17 @@ #include #include #include -#include #include =20 #include "aspeed_gfx.h" =20 -static struct aspeed_gfx * -drm_pipe_to_aspeed_gfx(struct drm_simple_display_pipe *pipe) +static int aspeed_gfx_set_pixel_fmt(struct aspeed_gfx *priv, + struct drm_plane_state *plane_state, + u32 *bpp) { - return container_of(pipe, struct aspeed_gfx, pipe); -} - -static int aspeed_gfx_set_pixel_fmt(struct aspeed_gfx *priv, u32 *bpp) -{ - struct drm_crtc *crtc =3D &priv->pipe.crtc; + struct drm_crtc *crtc =3D &priv->crtc; struct drm_device *drm =3D crtc->dev; - const u32 format =3D crtc->primary->state->fb->format->format; + const u32 format =3D plane_state->fb->format->format; u32 ctrl1; =20 ctrl1 =3D readl(priv->base + CRT_CTRL1); @@ -77,13 +74,15 @@ static void aspeed_gfx_disable_controller(struct aspeed= _gfx *priv) regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); } =20 -static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) +static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv, + struct drm_crtc_state *crtc_state, + struct drm_plane_state *plane_state) { - struct drm_display_mode *m =3D &priv->pipe.crtc.state->adjusted_mode; + struct drm_display_mode *m =3D &crtc_state->adjusted_mode; u32 ctrl1, d_offset, t_count, bpp; int err; =20 - err =3D aspeed_gfx_set_pixel_fmt(priv, &bpp); + err =3D aspeed_gfx_set_pixel_fmt(priv, plane_state, &bpp); if (err) return; =20 @@ -139,48 +138,35 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspe= ed_gfx *priv) writel(priv->throd_val, priv->base + CRT_THROD); } =20 -static void aspeed_gfx_pipe_enable(struct drm_simple_display_pipe *pipe, - struct drm_crtc_state *crtc_state, - struct drm_plane_state *plane_state) +static void aspeed_gfx_crtc_helper_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) { - struct aspeed_gfx *priv =3D drm_pipe_to_aspeed_gfx(pipe); - struct drm_crtc *crtc =3D &pipe->crtc; + struct aspeed_gfx *priv =3D to_aspeed_gfx(crtc->dev); + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(commi= t, crtc); + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(co= mmit, &priv->plane); =20 - aspeed_gfx_crtc_mode_set_nofb(priv); + aspeed_gfx_crtc_mode_set_nofb(priv, crtc_state, plane_state); aspeed_gfx_enable_controller(priv); drm_crtc_vblank_on(crtc); } =20 -static void aspeed_gfx_pipe_disable(struct drm_simple_display_pipe *pipe) +static void aspeed_gfx_crtc_helper_atomic_disable(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) { - struct aspeed_gfx *priv =3D drm_pipe_to_aspeed_gfx(pipe); - struct drm_crtc *crtc =3D &pipe->crtc; + struct aspeed_gfx *priv =3D to_aspeed_gfx(crtc->dev); =20 drm_crtc_vblank_off(crtc); aspeed_gfx_disable_controller(priv); } =20 -static void aspeed_gfx_pipe_update(struct drm_simple_display_pipe *pipe, - struct drm_plane_state *plane_state) +static void aspeed_gfx_plane_helper_atomic_update(struct drm_plane *plane, + struct drm_atomic_commit *commit) { - struct aspeed_gfx *priv =3D drm_pipe_to_aspeed_gfx(pipe); - struct drm_crtc *crtc =3D &pipe->crtc; - struct drm_framebuffer *fb =3D pipe->plane.state->fb; - struct drm_pending_vblank_event *event; + struct drm_plane_state *new_plane_state =3D drm_atomic_get_new_plane_stat= e(commit, plane); + struct aspeed_gfx *priv =3D to_aspeed_gfx(plane->dev); + struct drm_framebuffer *fb =3D new_plane_state->fb; struct drm_gem_dma_object *gem; =20 - spin_lock_irq(&crtc->dev->event_lock); - event =3D crtc->state->event; - if (event) { - crtc->state->event =3D NULL; - - if (drm_crtc_vblank_get(crtc) =3D=3D 0) - drm_crtc_arm_vblank_event(crtc, event); - else - drm_crtc_send_vblank_event(crtc, event); - } - spin_unlock_irq(&crtc->dev->event_lock); - if (!fb) return; =20 @@ -190,9 +176,9 @@ static void aspeed_gfx_pipe_update(struct drm_simple_di= splay_pipe *pipe, writel(gem->dma_addr, priv->base + CRT_ADDR); } =20 -static int aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe) +static int aspeed_gfx_crtc_enable_vblank(struct drm_crtc *crtc) { - struct aspeed_gfx *priv =3D drm_pipe_to_aspeed_gfx(pipe); + struct aspeed_gfx *priv =3D to_aspeed_gfx(crtc->dev); u32 reg =3D readl(priv->base + CRT_CTRL1); =20 /* Clear pending VBLANK IRQ */ @@ -204,9 +190,9 @@ static int aspeed_gfx_enable_vblank(struct drm_simple_d= isplay_pipe *pipe) return 0; } =20 -static void aspeed_gfx_disable_vblank(struct drm_simple_display_pipe *pipe) +static void aspeed_gfx_crtc_disable_vblank(struct drm_crtc *crtc) { - struct aspeed_gfx *priv =3D drm_pipe_to_aspeed_gfx(pipe); + struct aspeed_gfx *priv =3D to_aspeed_gfx(crtc->dev); u32 reg =3D readl(priv->base + CRT_CTRL1); =20 reg &=3D ~CRT_CTRL_VERTICAL_INTR_EN; @@ -216,12 +202,93 @@ static void aspeed_gfx_disable_vblank(struct drm_simp= le_display_pipe *pipe) writel(reg | CRT_CTRL_VERTICAL_INTR_STS, priv->base + CRT_CTRL1); } =20 -static const struct drm_simple_display_pipe_funcs aspeed_gfx_funcs =3D { - .enable =3D aspeed_gfx_pipe_enable, - .disable =3D aspeed_gfx_pipe_disable, - .update =3D aspeed_gfx_pipe_update, - .enable_vblank =3D aspeed_gfx_enable_vblank, - .disable_vblank =3D aspeed_gfx_disable_vblank, +static int aspeed_gfx_plane_helper_atomic_check(struct drm_plane *plane, + struct drm_atomic_commit *commit) +{ + struct drm_plane_state *plane_state =3D drm_atomic_get_new_plane_state(co= mmit, plane); + struct drm_crtc_state *crtc_state =3D NULL; + + if (plane_state->crtc) { + crtc_state =3D drm_atomic_get_crtc_state(commit, plane_state->crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + return drm_atomic_helper_check_plane_state(plane_state, crtc_state, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, + false, false); +} + +static const struct drm_plane_helper_funcs aspeed_gfx_plane_helper_funcs = =3D { + .prepare_fb =3D drm_gem_plane_helper_prepare_fb, + .atomic_check =3D aspeed_gfx_plane_helper_atomic_check, + .atomic_update =3D aspeed_gfx_plane_helper_atomic_update, +}; + +static const struct drm_plane_funcs aspeed_gfx_plane_funcs =3D { + .update_plane =3D drm_atomic_helper_update_plane, + .disable_plane =3D drm_atomic_helper_disable_plane, + .destroy =3D drm_plane_cleanup, + .reset =3D drm_atomic_helper_plane_reset, + .atomic_duplicate_state =3D drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_plane_destroy_state, +}; + +static int aspeed_gfx_crtc_helper_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) +{ + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(commi= t, crtc); + int ret; + + if (crtc_state->enable) { + ret =3D drm_atomic_helper_check_crtc_primary_plane(crtc_state); + if (ret) + return ret; + } + + return drm_atomic_add_affected_planes(commit, crtc); +} + +static void aspeed_gfx_crtc_helper_atomic_flush(struct drm_crtc *crtc, + struct drm_atomic_commit *commit) +{ + struct drm_crtc_state *new_crtc_state =3D drm_atomic_get_new_crtc_state(c= ommit, crtc); + struct drm_pending_vblank_event *event =3D new_crtc_state->event; + + if (!event) + return; + + new_crtc_state->event =3D NULL; + + spin_lock_irq(&crtc->dev->event_lock); + if (drm_crtc_vblank_get(crtc) =3D=3D 0) + drm_crtc_arm_vblank_event(crtc, event); + else + drm_crtc_send_vblank_event(crtc, event); + spin_unlock_irq(&crtc->dev->event_lock); +} + +static const struct drm_crtc_helper_funcs aspeed_gfx_crtc_helper_funcs =3D= { + .atomic_check =3D aspeed_gfx_crtc_helper_atomic_check, + .atomic_enable =3D aspeed_gfx_crtc_helper_atomic_enable, + .atomic_disable =3D aspeed_gfx_crtc_helper_atomic_disable, + .atomic_flush =3D aspeed_gfx_crtc_helper_atomic_flush, +}; + +static const struct drm_crtc_funcs aspeed_gfx_crtc_funcs =3D { + .reset =3D drm_atomic_helper_crtc_reset, + .destroy =3D drm_crtc_cleanup, + .set_config =3D drm_atomic_helper_set_config, + .page_flip =3D drm_atomic_helper_page_flip, + .atomic_duplicate_state =3D drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_crtc_destroy_state, + .enable_vblank =3D aspeed_gfx_crtc_enable_vblank, + .disable_vblank =3D aspeed_gfx_crtc_disable_vblank, +}; + +static const struct drm_encoder_funcs aspeed_gfx_encoder_funcs =3D { + .destroy =3D drm_encoder_cleanup, }; =20 static const uint32_t aspeed_gfx_formats[] =3D { @@ -232,10 +299,36 @@ static const uint32_t aspeed_gfx_formats[] =3D { int aspeed_gfx_create_pipe(struct drm_device *drm) { struct aspeed_gfx *priv =3D to_aspeed_gfx(drm); + struct drm_plane *plane =3D &priv->plane; + struct drm_crtc *crtc =3D &priv->crtc; + struct drm_encoder *encoder =3D &priv->encoder; + int ret; + + ret =3D drm_universal_plane_init(drm, plane, 0, + &aspeed_gfx_plane_funcs, + aspeed_gfx_formats, + ARRAY_SIZE(aspeed_gfx_formats), + NULL, + DRM_PLANE_TYPE_PRIMARY, NULL); + if (ret) + return ret; + drm_plane_helper_add(plane, &aspeed_gfx_plane_helper_funcs); + + ret =3D drm_crtc_init_with_planes(drm, crtc, plane, NULL, + &aspeed_gfx_crtc_funcs, NULL); + if (ret) + return ret; + drm_crtc_helper_add(crtc, &aspeed_gfx_crtc_helper_funcs); + + ret =3D drm_encoder_init(drm, encoder, &aspeed_gfx_encoder_funcs, + DRM_MODE_ENCODER_NONE, NULL); + if (ret) + return ret; + encoder->possible_crtcs =3D drm_crtc_mask(crtc); + + ret =3D drm_connector_attach_encoder(&priv->connector, encoder); + if (ret) + return ret; =20 - return drm_simple_display_pipe_init(drm, &priv->pipe, &aspeed_gfx_funcs, - aspeed_gfx_formats, - ARRAY_SIZE(aspeed_gfx_formats), - NULL, - &priv->connector); + return 0; } diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspe= ed/aspeed_gfx_drv.c index 46094cca2974..b2d805f0c16d 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include =20 @@ -130,7 +129,7 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void= *data) reg =3D readl(priv->base + CRT_CTRL1); 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Handle pending page-flip events from the CRTC atomic flush path using the commit-local CRTC state, and avoid manual connector/encoder attachment before the connector has been created by the bridge path. Signed-off-by: Ze Huang --- Changes in v3: - Move the one-shot flow start to CRTC atomic_flush(), after pending event handling. - Move the MCDE container helper to the header as static inline. --- drivers/gpu/drm/mcde/mcde_display.c | 248 +++++++++++++++++++++++---------= ---- drivers/gpu/drm/mcde/mcde_drm.h | 12 +- drivers/gpu/drm/mcde/mcde_drv.c | 3 +- 3 files changed, 172 insertions(+), 91 deletions(-) diff --git a/drivers/gpu/drm/mcde/mcde_display.c b/drivers/gpu/drm/mcde/mcd= e_display.c index 257a6e84dd58..50c90cf84a9a 100644 --- a/drivers/gpu/drm/mcde/mcde_display.c +++ b/drivers/gpu/drm/mcde/mcde_display.c @@ -10,6 +10,7 @@ #include #include =20 +#include #include #include #include @@ -18,7 +19,6 @@ #include #include #include -#include #include #include #include