From nobody Mon Aug 24 11:04:02 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65779372B3D for ; Sat, 4 Jul 2026 18:33:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783189993; cv=none; b=U/ZA9x61zIETfRzHXRSS38UsfRSnVnESAlBZckJt2fDF3dW40bQRUh61/g1tJ4+MhKpDcq7G581MmZjXqUpxW9wOsq5apqvWeoWGieWdsphdYF/hwXm7tvSKuuPVmLbPMUwNiS7c33l5xIRNJ3yPx6GmRdHp3CXQgeYvjIrs6Kc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783189993; c=relaxed/simple; bh=UIMnAJmAsHNwzG3sUZoBE/LPKERzVi4sWM5J738IWxI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UzsubDDOA+8tJkffaWEWxqN4Uq2+ZLxv3iuuw8suvCgbNwNRs7Z9SnKzIzu29IduB/0+YyHH7Uqa5M/eNHtobI/Vg++Xiq96/gyspGne35ycpnMTmUkYbu3/lvhBpWtq9QUgilYFlWXN7D+2GykntYnCqR6ORSzTYiGIpM6KvYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=bLvR58BK; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=cGq1P7N/; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="bLvR58BK"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="cGq1P7N/" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 664G8Tlc3294156 for ; Sat, 4 Jul 2026 18:33:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= qeewdBY9B/GoXx4wh8GHCfZpl3Bn2RXn06zKpHrow0s=; b=bLvR58BKlqOhSmYR GWZwh7RAaMqMue255wp2Ux0Os9VOxeZTTKB+ZxPySU6eFiW7ptjT3b3vdgETw6Jd 5I947fjxQJDg/XrP4LXewlGPDfkNLfXj7mTxRKCdL6xeN/5VUZXXu70dBIH6VF4M vEAqNimBJaFsBPVH580f4bNI6/oHvXzoi1q5GHo/74VpLiQfryAKkNpALUWKrKKi lvjTgd7dkMAiZOSDtM3dX1XAgaypnJoWr9VA7uycRiP6EF2yiseN2j1pALBmIuq8 aSzmjLQ8i3hGYowHvMb9Iz2eUDnGL8p6GAbRS+lTM2RvEbLelhiecOA5MlLsGH+5 fsNVbA== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f6txeh993-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 04 Jul 2026 18:33:10 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-847a483ea41so1838145b3a.0 for ; Sat, 04 Jul 2026 11:33:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1783189990; x=1783794790; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qeewdBY9B/GoXx4wh8GHCfZpl3Bn2RXn06zKpHrow0s=; b=cGq1P7N/vvjpSIdfXuy2VrWaMOp4Urpmc5Kwgl87akIvklh8UhDysuhV4oNg/f3oRR 5rklNzoTHLyojwryG2qcDxXhYuzAhsUrOhNRICX1DZJuUMJqLtg+ZqA6HMqHl8r+Sr8Q gYrtDmWNYcNYn9BX7/VrVA6qD/pBY3IFprcrcUIofeNJ6iJu13RBx/3QLNYpAZo2NMGV c+luWM6+KzBvRTlMuZwZayYllNW1R2OKEBg7hFQKu8z5B5Q4179wRMk+xLQsR/cPrIuz Jej380k0uHMGSK/ft7o1w74Jkrnhl6ZxRvBF5ohRyoAa1JCJdm+CHJY4WPurwuKramzV USWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783189990; x=1783794790; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=qeewdBY9B/GoXx4wh8GHCfZpl3Bn2RXn06zKpHrow0s=; b=fQEdhd+wq2LQVw7wEJnmtbzsSkil+JEmkUPaKed2ag6NXJeimFMnSWy2P1pgIejjUk +vqd6MokThI/UpKI/zQ/OYzRxo1x2/5XY+uyoIOMf9tbMbiRYeomnvaowW+I1q+D6Qyz Bse18PEh93CAirmS3xJXH96eMoSKaAEsYzmee9KxDP2wxMFvfO1sAaryExwFGkwGKX52 GMiUBGbVhel6bnyg+JEWQSqeg3NyLZU0qGTIuE7MUO35OCZZYGlXYTMKQHCxWMF6nljP lwi+Rwn1/UMl/rCqvA1KWfpA83tu+o+R1bPfusWIYky2tRI2cgWOVJ7AXqaOJEcyuKQw 9ENQ== X-Forwarded-Encrypted: i=1; AFNElJ9XGph9af81IL+W1+UCdgt6wQTQi5TP410hxfAJcg19HS8e+bxlHFWFQYuyGsx+2OMTiHT5P7BcJXkgQB0=@vger.kernel.org X-Gm-Message-State: AOJu0Yz4Xs1zRScRj6y7wt6b/D1OxRrMEKbzcFLUSqcpdkCwsldZV838 p+igNbECSE0vbGUbhOw0XQ1bYlxWjxPcdF2VOwm8keV3CTJ1dW1SXYYIVLDwWTmalYw6BdaGnlx MR5Lq7YjMCB6aAj9vdUMktzl7SUi/lYx44Kjrbc6OJxliYn2T7/47tje1faB2EqLskJk= X-Gm-Gg: AfdE7cmD6kLOrX0bixjvItgNA3Nmhv9e3zpeio/TxUFa1SSiRFwyE/YUTM44HAvvPcJ S5Ql1vmRRjbq2C9R8iKpqXLC8wZsENZuOIOKkMLUMvA0/Ueoz2Wc2oN7GW+K0g5WLqVoEAoJCHT zKKLSBhrCRIXTF0Le3TbbzXm9n1+K3egLuVCsR+IwyLiXj4vBQnHfAoAWzDrFPnl0+LYz4uEBji jWDf7ZY3ALyR0VwnVpW5m6nliOwnOvqnSSt+YtVqXkzvfAtHVmQ96IeFeoxiQABrxDoEmHI6Oj7 8glRIxQ/rsMeqYBF4e7QkqlW5oiu0BHiYIpRc8120w5P8ndW7Q4DMZ7z2y4caii3jCoLvK8rUjh WKERKXsyDXSuqfaS5Rl1LJ+8= X-Received: by 2002:a05:6a00:2e9f:b0:847:8791:f54f with SMTP id d2e1a72fcca58-847f86eaa41mr3109153b3a.29.1783189989803; Sat, 04 Jul 2026 11:33:09 -0700 (PDT) X-Received: by 2002:a05:6a00:2e9f:b0:847:8791:f54f with SMTP id d2e1a72fcca58-847f86eaa41mr3109120b3a.29.1783189989281; Sat, 04 Jul 2026 11:33:09 -0700 (PDT) Received: from [192.168.1.100] ([151.243.38.149]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-847f6b6057dsm1508437b3a.7.2026.07.04.11.33.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jul 2026 11:33:08 -0700 (PDT) From: Ze Huang Date: Sun, 05 Jul 2026 02:31:14 +0800 Subject: [PATCH 5/9] drm/pl111: replace struct drm_simple_display_pipe with regular atomic helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260705-drm-simple-kms-removal-v1-5-b4e1ca053623@oss.qualcomm.com> References: <20260705-drm-simple-kms-removal-v1-0-b4e1ca053623@oss.qualcomm.com> In-Reply-To: <20260705-drm-simple-kms-removal-v1-0-b4e1ca053623@oss.qualcomm.com> To: Alexey Brodkin , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Joel Stanley , Andrew Jeffery , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Linus Walleij , Hans de Goede , Alex Lanzano , Oleksandr Andrushchenko Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, xen-devel@lists.xenproject.org, Ze Huang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783189912; l=11040; i=ze.huang@oss.qualcomm.com; s=20260704; h=from:subject:message-id; bh=UIMnAJmAsHNwzG3sUZoBE/LPKERzVi4sWM5J738IWxI=; b=RA4hDvGQcIHiHVgB2nIPn7/+tx2Alt8IiBFpU/Uf0g/qT5hFfsIN9rsVXLuWJcPpHLAeWBSzR q+gEaxP+EW5CPiUrPHYeBUiOXsCRtxFFrHUtMoJ7EySIxRCwYIyPTDI X-Developer-Key: i=ze.huang@oss.qualcomm.com; a=ed25519; pk=pSsISLZF2ubEjJRmslsa6Ps4W3yAuPY7yaircQTlQQU= X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA0MDE5MiBTYWx0ZWRfX68vEqG/UeGGn RlvolzK7AjhnzqNLhfv2Spxj7+hrXHzVcJ3dOSEAzGFeN5sEWHB5n9HTsd2yL2LFBW02bWBk3fp iehHNyt6j03KhiBDiZX+DgAFWDV4dno= X-Proofpoint-GUID: -Hdygo56S_4YLimRK7oLG_S4nBn7ZmhA X-Proofpoint-ORIG-GUID: -Hdygo56S_4YLimRK7oLG_S4nBn7ZmhA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA0MDE5MiBTYWx0ZWRfX8nHw9eqgYtQ8 e4h4vldCJyiQtZIpR1e7qrmaRMuVsIECBelyhStjFUlwvfA1d4opjmWOUQvAbiUshz9Hq6y9jgk m8755A8BQH1eG4tO2fHmzwvvpBuN4EF69ANt+4QUar0gxFsXeVrsUK8a1gAGDgwh1OiuQp5b4eO u4tY1Mq+JRqNkE0a/A6Hl752vp1NlAAe7cDBt8SGqPsD2MFdRODYrhc4Sb4G9DpnqnOeLIbz8EA +H0iYfnT156HFaKolSpARcIhDhXARzCW3tJfmq/0AR9d1wwtzHvvVb0UY3NhYmB2KnkruyhcJek dJHCX8TzfT5W1C4/wgcOki/zv/MDaGIWvdkiaNTyuJy7sIA8mssbsVQgSxmTAONa81sgpMMDHOS HU0Dbw7/g/wXaf0otleDPJQ3d3KR4vbqHv5aUbHoKHFTm9SeETyQaWia6YRGLJPwTMlb2Xy/RoW 1U9WhXTeXaHgLCjBlFg== X-Authority-Analysis: v=2.4 cv=HLLz0Itv c=1 sm=1 tr=0 ts=6a4951e6 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=cNux22OjBTKCC6TmznXXXA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=zKtxPG1kur982WRNNmIA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-04_02,2026-07-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 clxscore=1011 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607040192 Replace PL111 simple display pipe with explicit plane, CRTC and encoder objects. Keep existing hardware programming and vblank behavior, and install GEM framebuffer prepare helper explicitly. Signed-off-by: Ze Huang --- drivers/gpu/drm/pl111/pl111_display.c | 174 ++++++++++++++++++++++++++----= ---- drivers/gpu/drm/pl111/pl111_drm.h | 5 +- drivers/gpu/drm/pl111/pl111_drv.c | 3 +- 3 files changed, 136 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/= pl111_display.c index 5d10bc5fdf1f..b1bdd4c9dbe6 100644 --- a/drivers/gpu/drm/pl111/pl111_display.c +++ b/drivers/gpu/drm/pl111/pl111_display.c @@ -15,6 +15,7 @@ #include #include =20 +#include #include #include #include @@ -37,7 +38,7 @@ irqreturn_t pl111_irq(int irq, void *data) return IRQ_NONE; =20 if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) { - drm_crtc_handle_vblank(&priv->pipe.crtc); + drm_crtc_handle_vblank(&priv->crtc); =20 status =3D IRQ_HANDLED; } @@ -49,10 +50,10 @@ irqreturn_t pl111_irq(int irq, void *data) } =20 static enum drm_mode_status -pl111_mode_valid(struct drm_simple_display_pipe *pipe, - const struct drm_display_mode *mode) +pl111_crtc_helper_mode_valid(struct drm_crtc *crtc, + const struct drm_display_mode *mode) { - struct drm_device *drm =3D pipe->crtc.dev; + struct drm_device *drm =3D crtc->dev; struct pl111_drm_dev_private *priv =3D drm->dev_private; u32 cpp =3D DIV_ROUND_UP(priv->variant->fb_depth, 8); u64 bw; @@ -83,13 +84,35 @@ pl111_mode_valid(struct drm_simple_display_pipe *pipe, return MODE_OK; } =20 -static int pl111_display_check(struct drm_simple_display_pipe *pipe, - struct drm_plane_state *pstate, - struct drm_crtc_state *cstate) +static int pl111_plane_helper_atomic_check(struct drm_plane *plane, + struct drm_atomic_commit *state) { - const struct drm_display_mode *mode =3D &cstate->mode; - struct drm_framebuffer *old_fb =3D pipe->plane.state->fb; + struct drm_plane_state *pstate =3D drm_atomic_get_new_plane_state(state, = plane); + struct drm_crtc *crtc =3D pstate->crtc; + struct drm_crtc_state *cstate; + const struct drm_display_mode *mode; + struct drm_framebuffer *old_fb =3D plane->state->fb; struct drm_framebuffer *fb =3D pstate->fb; + int ret; + + if (!crtc) + return 0; + + cstate =3D drm_atomic_get_new_crtc_state(state, crtc); + if (!cstate) + return 0; + + ret =3D drm_atomic_helper_check_plane_state(pstate, cstate, + DRM_PLANE_NO_SCALING, + DRM_PLANE_NO_SCALING, + false, false); + if (ret) + return ret; + + if (!pstate->visible) + return 0; + + mode =3D &cstate->mode; =20 if (mode->hdisplay % 16) return -EINVAL; @@ -117,16 +140,14 @@ static int pl111_display_check(struct drm_simple_disp= lay_pipe *pipe, return 0; } =20 -static void pl111_display_enable(struct drm_simple_display_pipe *pipe, - struct drm_crtc_state *cstate, - struct drm_plane_state *plane_state) +static void pl111_crtc_helper_atomic_enable(struct drm_crtc *crtc, + struct drm_atomic_commit *state) { - struct drm_crtc *crtc =3D &pipe->crtc; - struct drm_plane *plane =3D &pipe->plane; struct drm_device *drm =3D crtc->dev; struct pl111_drm_dev_private *priv =3D drm->dev_private; + struct drm_crtc_state *cstate =3D crtc->state; const struct drm_display_mode *mode =3D &cstate->mode; - struct drm_framebuffer *fb =3D plane->state->fb; + struct drm_framebuffer *fb =3D priv->plane.state->fb; struct drm_connector *connector =3D priv->connector; struct drm_bridge *bridge =3D priv->bridge; bool grayscale =3D false; @@ -355,9 +376,9 @@ static void pl111_display_enable(struct drm_simple_disp= lay_pipe *pipe, drm_crtc_vblank_on(crtc); } =20 -static void pl111_display_disable(struct drm_simple_display_pipe *pipe) +static void pl111_crtc_helper_atomic_disable(struct drm_crtc *crtc, + struct drm_atomic_commit *state) { - struct drm_crtc *crtc =3D &pipe->crtc; struct drm_device *drm =3D crtc->dev; struct pl111_drm_dev_private *priv =3D drm->dev_private; u32 cntl; @@ -387,17 +408,23 @@ static void pl111_display_disable(struct drm_simple_d= isplay_pipe *pipe) clk_disable_unprepare(priv->clk); } =20 -static void pl111_display_update(struct drm_simple_display_pipe *pipe, - struct drm_plane_state *old_pstate) +static void pl111_plane_helper_atomic_update(struct drm_plane *plane, + struct drm_atomic_commit *state) { - struct drm_crtc *crtc =3D &pipe->crtc; - struct drm_device *drm =3D crtc->dev; - struct pl111_drm_dev_private *priv =3D drm->dev_private; - struct drm_pending_vblank_event *event =3D crtc->state->event; - struct drm_plane *plane =3D &pipe->plane; + struct drm_crtc *crtc =3D plane->state->crtc; + struct drm_device *drm; + struct pl111_drm_dev_private *priv; + struct drm_pending_vblank_event *event; struct drm_plane_state *pstate =3D plane->state; struct drm_framebuffer *fb =3D pstate->fb; =20 + if (!crtc) + return; + + drm =3D crtc->dev; + priv =3D drm->dev_private; + event =3D crtc->state->event; + if (fb) { u32 addr =3D drm_fb_dma_get_gem_addr(fb, pstate, 0); =20 @@ -416,9 +443,8 @@ static void pl111_display_update(struct drm_simple_disp= lay_pipe *pipe, } } =20 -static int pl111_display_enable_vblank(struct drm_simple_display_pipe *pip= e) +static int pl111_display_enable_vblank(struct drm_crtc *crtc) { - struct drm_crtc *crtc =3D &pipe->crtc; struct drm_device *drm =3D crtc->dev; struct pl111_drm_dev_private *priv =3D drm->dev_private; =20 @@ -427,21 +453,63 @@ static int pl111_display_enable_vblank(struct drm_sim= ple_display_pipe *pipe) return 0; } =20 -static void pl111_display_disable_vblank(struct drm_simple_display_pipe *p= ipe) +static void pl111_display_disable_vblank(struct drm_crtc *crtc) { - struct drm_crtc *crtc =3D &pipe->crtc; struct drm_device *drm =3D crtc->dev; struct pl111_drm_dev_private *priv =3D drm->dev_private; =20 writel(0, priv->regs + priv->ienb); } =20 -static struct drm_simple_display_pipe_funcs pl111_display_funcs =3D { - .mode_valid =3D pl111_mode_valid, - .check =3D pl111_display_check, - .enable =3D pl111_display_enable, - .disable =3D pl111_display_disable, - .update =3D pl111_display_update, +static int pl111_crtc_helper_atomic_check(struct drm_crtc *crtc, struct dr= m_atomic_commit *state) +{ + struct drm_crtc_state *crtc_state =3D drm_atomic_get_new_crtc_state(state= , crtc); + int ret; + + if (!crtc_state->enable) + goto out; + + ret =3D drm_atomic_helper_check_crtc_primary_plane(crtc_state); + if (ret) + return ret; + +out: + return drm_atomic_add_affected_planes(state, crtc); +} + +static struct drm_crtc_funcs pl111_crtc_funcs =3D { + .reset =3D drm_atomic_helper_crtc_reset, + .destroy =3D drm_crtc_cleanup, + .set_config =3D drm_atomic_helper_set_config, + .page_flip =3D drm_atomic_helper_page_flip, + .atomic_duplicate_state =3D drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_crtc_destroy_state, +}; + +static const struct drm_crtc_helper_funcs pl111_crtc_helper_funcs =3D { + .mode_valid =3D pl111_crtc_helper_mode_valid, + .atomic_check =3D pl111_crtc_helper_atomic_check, + .atomic_enable =3D pl111_crtc_helper_atomic_enable, + .atomic_disable =3D pl111_crtc_helper_atomic_disable, +}; + +static const struct drm_plane_funcs pl111_plane_funcs =3D { + .update_plane =3D drm_atomic_helper_update_plane, + .disable_plane =3D drm_atomic_helper_disable_plane, + .reset =3D drm_atomic_helper_plane_reset, + .destroy =3D drm_plane_cleanup, + .atomic_duplicate_state =3D drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_plane_destroy_state, +}; + +static const struct drm_plane_helper_funcs pl111_plane_helper_funcs =3D { + .prepare_fb =3D drm_gem_plane_helper_prepare_fb, + .atomic_check =3D pl111_plane_helper_atomic_check, + .atomic_update =3D pl111_plane_helper_atomic_update, +}; + +static const struct drm_encoder_funcs pl111_encoder_funcs =3D { + .destroy =3D drm_encoder_cleanup, }; =20 static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate, @@ -583,18 +651,40 @@ int pl111_display_init(struct drm_device *drm) return ret; =20 if (!priv->variant->broken_vblank) { - pl111_display_funcs.enable_vblank =3D pl111_display_enable_vblank; - pl111_display_funcs.disable_vblank =3D pl111_display_disable_vblank; + pl111_crtc_funcs.enable_vblank =3D pl111_display_enable_vblank; + pl111_crtc_funcs.disable_vblank =3D pl111_display_disable_vblank; } =20 - ret =3D drm_simple_display_pipe_init(drm, &priv->pipe, - &pl111_display_funcs, - priv->variant->formats, - priv->variant->nformats, - NULL, - priv->connector); + ret =3D drm_universal_plane_init(drm, &priv->plane, 0, + &pl111_plane_funcs, + priv->variant->formats, + priv->variant->nformats, + NULL, DRM_PLANE_TYPE_PRIMARY, NULL); if (ret) return ret; =20 + drm_plane_helper_add(&priv->plane, &pl111_plane_helper_funcs); + + ret =3D drm_crtc_init_with_planes(drm, &priv->crtc, &priv->plane, + NULL, &pl111_crtc_funcs, NULL); + if (ret) + return ret; + + drm_crtc_helper_add(&priv->crtc, &pl111_crtc_helper_funcs); + + ret =3D drm_encoder_init(drm, &priv->encoder, &pl111_encoder_funcs, + DRM_MODE_ENCODER_NONE, NULL); + if (ret) + return ret; + + priv->encoder.possible_crtcs =3D drm_crtc_mask(&priv->crtc); + + if (priv->connector) { + ret =3D drm_connector_attach_encoder(priv->connector, + &priv->encoder); + if (ret) + return ret; + } + return 0; } diff --git a/drivers/gpu/drm/pl111/pl111_drm.h b/drivers/gpu/drm/pl111/pl11= 1_drm.h index d1fe756444ee..ec92a5a180a8 100644 --- a/drivers/gpu/drm/pl111/pl111_drm.h +++ b/drivers/gpu/drm/pl111/pl111_drm.h @@ -21,7 +21,6 @@ #include #include #include -#include =20 /* * CLCD Controller Internal Register addresses @@ -135,7 +134,9 @@ struct pl111_drm_dev_private { struct drm_connector *connector; struct drm_panel *panel; struct drm_bridge *bridge; - struct drm_simple_display_pipe pipe; + struct drm_plane plane; + struct drm_crtc crtc; + struct drm_encoder encoder; =20 void *regs; u32 memory_bw; diff --git a/drivers/gpu/drm/pl111/pl111_drv.c b/drivers/gpu/drm/pl111/pl11= 1_drv.c index ac7b1d12a0f5..f649c266c33a 100644 --- a/drivers/gpu/drm/pl111/pl111_drv.c +++ b/drivers/gpu/drm/pl111/pl111_drv.c @@ -168,8 +168,7 @@ static int pl111_modeset_init(struct drm_device *dev) goto out_bridge; } =20 - ret =3D drm_simple_display_pipe_attach_bridge(&priv->pipe, - bridge); + ret =3D drm_bridge_attach(&priv->encoder, bridge, NULL, 0); if (ret) return ret; =20 --=20 2.55.0