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Wed, 01 Jul 2026 12:32:28 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 1 Jul 2026 12:31:24 -0700 In-Reply-To: <20260701193212.749551-1-seanjc@google.com> Mime-Version: 1.0 References: <20260701193212.749551-1-seanjc@google.com> X-Mailer: git-send-email 2.55.0.rc0.799.gd6f94ed593-goog Message-ID: <20260701193212.749551-4-seanjc@google.com> Subject: [PATCH v5 03/51] x86/tsc: Ensure that TSC recalibration doesn't run if TSC frequency is known From: Sean Christopherson To: Jonathan Corbet , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, Kiryl Shutsemau , Rick Edgecombe , Sean Christopherson , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Ajay Kaher , Alexey Makhalov , Jan Kiszka , Andy Lutomirski , Peter Zijlstra , Juergen Gross , Daniel Lezcano , John Stultz Cc: Shuah Khan , "H. Peter Anvin" , Vitaly Kuznetsov , Broadcom internal kernel review list , Boris Ostrovsky , Stephen Boyd , linux-doc@vger.kernel.org, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, xen-devel@lists.xenproject.org, Tom Lendacky , Nikunj A Dadhania , David Woodhouse , David Woodhouse , Michael Kelley , Thomas Gleixner X-purgate-ID: tlsNG-ebf023/1782934351-AEB2B1CC-6C7722F5/0/0 X-purgate-type: clean X-purgate-size: 1418 X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1782934374250158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When attempting TSC recalibration post-boot, which is only done for ancient CPUS (P4 and K7) on SMP=3Dn kernels, assert that the TSC frequency isn't known (explicitly provided by hardware) by way of MSR or CPUID, and bail if the impossible happens. In practice, recalibration and TSC_KNOWN_FREQ are mutually exclusive, as TSC_KNOWN_FREQ will only be set when running on hardware that was released decades after recalibration was obsoleted, but but it's hard to see that, especially when looking at just the TSC code. Note, the WARN can likely be tripped by running in a virtual machine and concocting an impossible CPU model, e.g. by combining a P4 signature with CPUID 0x15. This is working as intended, as such a virtual CPU model is wildly out-of-spec and is not supported. Signed-off-by: Sean Christopherson --- arch/x86/kernel/tsc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 4d6a446645c0..4393902c0ddd 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -930,6 +930,9 @@ void recalibrate_cpu_khz(void) if (!boot_cpu_has(X86_FEATURE_TSC)) return; =20 + if (WARN_ON_ONCE(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ))) + return; + cpu_khz =3D x86_platform.calibrate_cpu(); tsc_khz =3D x86_platform.calibrate_tsc(); if (tsc_khz =3D=3D 0) --=20 2.55.0.rc0.799.gd6f94ed593-goog