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[78.146.242.105]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b0e2b4e5sm85731745e9.7.2026.06.02.09.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 09:45:21 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1780418722; x=1781023522; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=U5E49+b+uC/od9SZLoU0uYb9I0eV+tcWYMSLbFGajYw=; b=CBMt8LzQYum3CGxvR+33ka61TFI9rz40PmPQnyFmoTL0o9hcuiLpDY+rllvn40FNpO JZtmZgttndvZEUUGjNg0skziQ0G8c8W1tTRXTGOCgQ2wHb9SZ4OF7J6CfQppldmI5Sl2 KgBizko5PcYXBgm4gX4kztJn6+ooOnhKg2DxY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780418722; x=1781023522; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=U5E49+b+uC/od9SZLoU0uYb9I0eV+tcWYMSLbFGajYw=; b=X09up92uqOElE6IV6KQXY5BpxLKWjDZRkZ2+gSGRrvuaMKWHnABAU+/qd3MmHwdFC3 tjCjvjmw3Ven68pQbQ66qrVyzGv0WGwSXGNsS6NswX/u2vSJ1v+bQJG3pdb9mNxhLFaz lTQ20/84j0qtGPIZ/UQqbL2sL7o88bry5lzMrYH41z4bGnC4Jaiv2S3pBbSdiXHXMnFG Q4GAR6lth3HdlQq9efGQzb11ME/nJlV3OVclxG5Yn6HgEk5LwTiTbAUu5YEYxjQ2wZpr nKPLK8BVcCR36ZdtMhJRK6Wl9Wi2Sgfdc6UM69362PZlBsja/OAhXIIzIVR3oRQiQQnl cgdQ== X-Gm-Message-State: AOJu0YwoY+oZcPSBril7LfNjnOOS1xsnWIiPUUMsH5b0O1W/Od4KQ9QF 7WLR51Hw6B0uHs4Bo4pdDvkvBaOJ8ciELhF1lnLpNo97R1TZgd6+MH5XBgz60Twsi08DkRL/NzU mFjLk X-Gm-Gg: Acq92OGHArNbvp8uo47t70HFFsbB2Uo3W1MsqHqTmvgO0ON6bGhOnJD5etIujViKO15 2W2wR29DYYReUfa0mG5Et4918hZWeSfnOLmuEj+n6yuSyHL64wyVXV9JjQQ1LVtgsN29JSWh7qR o+wKMnWc+daw5aHHAHg8ycF3A4/icMxpKl7Qg0/D09+49Nl1TY3LAJckX0JRArLmxqB1OXSSaIw rmTDq4w1OAXviZLqYfO27azeKgPyZfLTFADy0cDCipXnRJvRYkiv8LpDqbK/zywmI7R9JZw6gbW Qu+wpC6vbz01INlw2aYQ2IrGRZt07Yfov8KjnHSbCtv+bg+07ye6onblUP7ztXigYxkhcb3Rjax 6ccmMgkpXQ0ck4pAjIsc1MA0cF5yY1ny3nmKaRsQGQRzDEc2DTu/MqezPxxKj+tPXv1Be/J6MnF lutKl8KKOCpba8WkwHvsq40LnsbwOrsKKc7hEc8pWiXmUNivU+nt+Yo7+bmtgdZHQr9e/b2WlFW m9cCDptpyvDfbY= X-Received: by 2002:a05:600c:8b27:b0:490:3fa2:1b93 with SMTP id 5b1f17b1804b1-490b5064808mr8729965e9.13.1780418722069; Tue, 02 Jun 2026 09:45:22 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Teddy Astie , Oleksii Kurochko Subject: [PATCH for-4.22] x86/fred: Enable FRED by default on AMD systems Date: Tue, 2 Jun 2026 17:45:19 +0100 Message-Id: <20260602164519.2634144-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1780418722-E1D9D443-66F37A69/10/73395122804 X-purgate-type: spam X-purgate-size: 2389 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1780418753069154100 FRED is now believed to be complete for AMD systems, and has had its tyres kicked by both XenServer and AMD. Enable FRED by default on capable AMD systems (Zen6 and later). Support on Intel is still not yet complete. Leave it as tech preview and n= ot security supported. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Teddy Astie CC: Oleksii Kurochko The issue on Intel is to do with virtualisation of MSR_SPEC_CTRL for PV guests, and is waiting on the resolution of a question I've asked Intel. --- docs/misc/xen-command-line.pandoc | 6 +++--- xen/arch/x86/traps-setup.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index ef3c7371895b..50c119e5b79f 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -1259,12 +1259,12 @@ does not provide `VM_ENTRY_LOAD_GUEST_PAT`. ### fred (x86) > `=3D ` =20 -> Default: `false` +> Default: `true` on AMD, `false` otherwise =20 Flexible Return and Event Delivery is an overhaul of interrupt, exception = and system call handling, fixing many corner cases in the x86 architecture, and -expected in hardware from 2025. Support in Xen is a work in progress and -disabled by default. +expected in hardware from 2026. FRED is fully supported on AMD hardware. +Intel hardware is still tech preview and not security supported. =20 ### gnttab > `=3D List of [ max-ver:, transitive=3D, transfer=3D= ]` diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index ccbd53fd9db0..a79a3b201389 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -22,7 +22,7 @@ unsigned int __ro_after_init ler_msr; static bool __initdata opt_ler; boolean_param("ler", opt_ler); =20 -int8_t __ro_after_init opt_fred =3D 0; +int8_t __ro_after_init opt_fred =3D -1; boolean_param("fred", opt_fred); =20 void nocall entry_PF(void); @@ -392,7 +392,7 @@ void __init traps_init(void) } =20 if ( opt_fred =3D=3D -1 ) - opt_fred =3D !pv_shim; + opt_fred =3D (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) && != pv_shim; =20 if ( opt_fred ) { --=20 2.39.5