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Mon, 18 May 2026 04:46:24 -0700 (PDT) From: =?UTF-8?q?Gabriel=20Quint=C3=A1ns=20Souto?= To: xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, julien@xen.org, bertrand.marquis@arm.com, michal.orzel@amd.com, =?UTF-8?q?Gabriel=20Quint=C3=A1ns=20Souto?= Subject: [PATCH v2] arm: Fix PT_PT table descriptor value and comment Date: Mon, 18 May 2026 13:45:52 +0200 Message-ID: <20260518114552.29687-1-gabi.qs.mail@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <2ef09a6a-f78f-47a5-8ffb-cd03cb51fc1b@amd.com> References: <2ef09a6a-f78f-47a5-8ffb-cd03cb51fc1b@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-33051d/1779104786-3B360938-8F9F34D4/0/0 X-purgate-type: clean X-purgate-size: 2246 X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1779104820387154100 Per ARMv7-A/ARMv8-A ARM, bits [11:2] of table descriptors are ignored by ha= rdware. The original comment incorrectly described block/page descriptor fi= elds (nG, SH, AP, NS, ATTR) which do not exist in the table descriptor form= at. Set PT_PT to 0x403: - Bit 0 (P): Valid bit (required) - Bit 1 (T): Table descriptor type (required) - Bit 10 (AF): Access flag (future-proof for FEAT_HAFT) Hardware ignores bits [11:2] but setting AF prepares for ARMv9's FEAT_HAFT.= Using 0x403 rather than minimal 0x3 provides forward compatibility while a= voiding unnecessary reserved bits. This updates both arm32 and arm64 for consistency. Signed-off-by: Gabriel Quint=C3=A1ns Souto --- Changes in v2: - Apply fix to both arm32 and arm64 - Use 0x403 instead of 0x743 --- xen/arch/arm/arm32/mmu/head.S | 2 +- xen/arch/arm/arm64/mmu/head.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm32/mmu/head.S b/xen/arch/arm/arm32/mmu/head.S index 5032e6c075..cab7be0621 100644 --- a/xen/arch/arm/arm32/mmu/head.S +++ b/xen/arch/arm/arm32/mmu/head.S @@ -8,7 +8,7 @@ #include #include =20 -#define PT_PT 0xf7f /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D1 P=3D1 */ +#define PT_PT 0x403 /* AF=3D1 T=3D1 P=3D1 (bits [11:2] ignored in tabl= e descriptors) */ #define PT_MEM 0xf7d /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D0 P=3D1 */ #define PT_MEM_L3 0xf7f /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D1 P=3D1 */ #define PT_DEV 0xe71 /* nG=3D1 AF=3D1 SH=3D10 AP=3D01 NS=3D1 ATTR=3D100= T=3D0 P=3D1 */ diff --git a/xen/arch/arm/arm64/mmu/head.S b/xen/arch/arm/arm64/mmu/head.S index c3cb262e88..375d703d9b 100644 --- a/xen/arch/arm/arm64/mmu/head.S +++ b/xen/arch/arm/arm64/mmu/head.S @@ -8,7 +8,7 @@ #include #include =20 -#define PT_PT 0x743 /* AF=3D1 RES=3D11 SKL=3D1 IGN=3D0000 T=3D1 P=3D1 = */ +#define PT_PT 0x403 /* AF=3D1 T=3D1 P=3D1 (bits [11:2] ignored in tabl= e descriptors) */ #define PT_MEM 0xf7d /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D0 P=3D1 */ #define PT_MEM_L3 0xf7f /* nG=3D1 AF=3D1 SH=3D11 AP=3D01 NS=3D1 ATTR=3D111= T=3D1 P=3D1 */ #define PT_DEV 0xe71 /* nG=3D1 AF=3D1 SH=3D10 AP=3D01 NS=3D1 ATTR=3D100= T=3D0 P=3D1 */ --=20 2.54.0