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[78.146.242.105]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fd64cead5sm3677305e9.10.2026.05.13.10.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 10:15:55 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=google header.d=citrix.com header.i="@citrix.com" header.h="Content-Transfer-Encoding:MIME-Version:Message-Id:Date:Subject:Cc:To:From" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1778692556; x=1779297356; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=ZdMwvmCM9lXcoLo/b5jCJV7hGyPbWoPml9O23giK69s=; b=HtLiCTmBPC5fa3IJ1IwFvWq/SwQKs6g1VxmfIEl2T9TKBhhbTw3N7/KOFcJVe2rThv k+VWDZ+DoKGTkLjYdONUI9p4erToUIq3r16xaAIYglsuJoqZS7O47nxftTmKtbQm9N+P slOMO+/LOT1/K2DxECWWmnaLB+DGsFycYAyes= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778692556; x=1779297356; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=ZdMwvmCM9lXcoLo/b5jCJV7hGyPbWoPml9O23giK69s=; b=tGApb67jJ8x1oef2hTba+1Noo6EXchu7VtwnvtR04YNQN01IxgfoRlAi0zPMeT7FR1 GfIwu2n+s+r9ejX3guEtd7BjwtolVmAbtZn/ziwy3KMYGsgoEAhzYKEXt2GbpoJix8Pa 9aIXQrT13CgPe6Oy3+YM4OZh+Ph8MI1NlrJM42flH9xowFlVpl+C1aKeqHAYZbhIYaWv ZZwuvd6pg6w8jLLuiCa60m9NtoRLwzjrYJQSwk0TV+14TJzkO4GIfX9yAvo4tItvYgMO Ak3zwGpjGium9ji8jR1mZkzaAne6ybGtLETDZ9TAtViNOE7TFMqhuq2fSg3EDqOHNDBw M+oA== X-Gm-Message-State: AOJu0YyQswsfI9I31Uo+zfhoDZ1v5tpQWhR7xrRcmU5nmCmgGYZHEjnH u02oN3thbSHNizfP+vqiwYvXmGgup0oyd+M2vnV+pVbBFkFdQTLAknXAvsj6CNCoj2yVsKbUSXI iJu/4Lio= X-Gm-Gg: Acq92OEDvtohHxkIrX/brevDINkHqdDbJzj3RFpdBnVqg5NvOv3+2DA6ZtBm0DYehnF boHCHsJf6hWFAIJVcAD9o26+IPFY6lAlaJGN7CKGHeGTXoaBnZsA05Hwbjc466EZx6IHj+uutey VoPmqT5xyyUFe0ArlkQLf0oBTiKc93/88Kyw1m1/DtwR3dBJC1W8LADqlrYSW9/R2KVE/KhIo3T LRukqjm0+6e6GSIxuceJqC3G+lPXvFnaCFAk524+gpmNVDiowLt5Z50/O94u0w8wk99eeV2yAyg 8eSjQUoYE+uh8IAEsMVAtKpUTG4bfZHDr6WB15MfuyNZo0vijOeye/AcQT9Rnk+bGbVmbiQUJJ7 0V/tbcPqdSvrInzVs0i+7bSglbDf7A7PfG0sIFEEdYH1R0D9e8P3ZPtfJSlc0Uawh/G7NoK9JEN XN8OZV7ddcJ95mF4wg/H/qMSgqrCSMz/ev0RP/stI90dRWjPS2RQCApQEaMtwi0Rk4XLTprf50i 6M4 X-Received: by 2002:a05:600c:1547:b0:489:1f04:96c3 with SMTP id 5b1f17b1804b1-48fc9a02834mr61577535e9.2.1778692556263; Wed, 13 May 2026 10:15:56 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v2] x86/emul: Adjust handling of CR8_LEGACY Date: Wed, 13 May 2026 18:15:53 +0100 Message-Id: <20260513171553.1772095-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1778692557-6F95E8B7-D450D6A4/0/0 X-purgate-type: clean X-purgate-size: 2089 X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1778692580245158500 The CR8_LEGACY feature was introduced in the K8 Revision F. It doesn't exi= st in prior revisions of the K8. Furthermore, from APM Vol2 3.1.5 CR8 (Task Priority Register, TPR): The AMD64 architecture introduces a new control register, CR8, defined as the task priority register (TPR). Additionally, from APM Vol3 4 System Instructions MOV CRn: CR8 can be read and written in 64-bit mode, using a REX prefix. CR8 can = be read and written in all modes using a LOCK prefix instead of a REX prefix= to specify the additional opcode bit. i.e. the LOCK prefix serves as an alternative encoding for REX.R. Switch decode_twobyte() from +=3D 8 to |=3D 8 to better match the descripti= on given. Other indications that the encoding isn't additive are that the CR intercepts stop at 15, and that LOCK MOV CR8 generates #UD rather than becoming a CR0 access. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich Reviewed-by: Teddy Astie --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 v2: * No dependency on LM. Also, designers never put an ADD into silicon if they can possibly avoid it, because it's large and slow compared to the single OR gate needed in this case. --- xen/arch/x86/x86_emulate/decode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/x86_emulate/decode.c b/xen/arch/x86/x86_emulate/d= ecode.c index 2c13356c4d17..51c89ddfc893 100644 --- a/xen/arch/x86/x86_emulate/decode.c +++ b/xen/arch/x86/x86_emulate/decode.c @@ -782,10 +782,10 @@ decode_twobyte(struct x86_emulate_state *s, case 0x20: case 0x22: /* mov to/from cr */ if ( s->lock_prefix && vcpu_has_cr8_legacy() ) { - s->modrm_reg +=3D 8; + s->modrm_reg |=3D 8; s->lock_prefix =3D false; } - /* fall through */ + fallthrough; case 0x21: case 0x23: /* mov to/from dr */ ASSERT(s->ea.type =3D=3D OP_REG); /* Early operand adjustment ensu= res this. */ generate_exception_if(s->lock_prefix, X86_EXC_UD); --=20 2.39.5