From nobody Sat May 30 11:15:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1778608691; cv=none; d=zohomail.com; s=zohoarc; b=YyBhaNjgLfvWspKCj2txZp9Jvk/1Sn+LBwsOFZZeatpOI8PtbxfdQcypdAwMc22JnGuoae/4K6uPs/Uns37FTNqLkTfiW5atQgEdJKcSVgHicDyQdHZUKupdl7m2D8zUiOp7lbsUrjwk68K/Q1ne+y9T7CdOTsa6KLn5SDdqvdg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778608691; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KrO2ypPs3nug/qhemFFmWuJVNCYfJiUtgn7azgRguR0=; b=GO5PF/6pSw7XjgxoD393KdWu7ge+FphBm1Fq9onV7vGudk0TL/uue527wt2fdXvawhc6mrwMqmV9rq/En+Pm8mTIGdTsgy2HRF6dttyllfXZ2MOogRxAlRDbtisjSYBLjf5RIIPxwGIAzRps+viM+UV31chIyBmQJrcA7qOLV7Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1778608690982221.35021572352525; Tue, 12 May 2026 10:58:10 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1307397.1579115 (Exim 4.92) (envelope-from ) id 1wMrMa-0003Oo-6J; Tue, 12 May 2026 17:57:48 +0000 Received: by outflank-mailman (output) from mailman id 1307397.1579115; Tue, 12 May 2026 17:57:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wMrMa-0003Oh-3Q; Tue, 12 May 2026 17:57:48 +0000 Received: by outflank-mailman (input) for mailman id 1307397; Tue, 12 May 2026 17:57:46 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wMrMX-0003Bf-W5 for xen-devel@lists.xenproject.org; Tue, 12 May 2026 17:57:46 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wMrMV-009D7s-RO for xen-devel@lists.xenproject.org; Tue, 12 May 2026 19:57:45 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 6a036a11-bab6-0a2a0a5309dd-0a2a4502963a-12 for ; Tue, 12 May 2026 19:57:45 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-720697.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 6a036a17-af86-0a2a45020019-d98c6eaca98e-1 for ; Tue, 12 May 2026 19:57:44 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 205A6168F; Tue, 12 May 2026 10:57:38 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 024873F85F; Tue, 12 May 2026 10:57:41 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778608663; bh=3OwJmJ83fF7wYUwwajm97vdwH/PiBu+huX5oR7YFd8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YGtG+/FGraeXfKwo6j2ZszCbIexHGTz5euMS3ApNO7W1S5knzb1eWlLwl7yHl76z8 htJu4fA71TzqxS+kS3Z+OK0tqmxB6fu5EB+s8UfHIAxCpzSVgQ1fm4dMxs9A93hetA B9kf5ORAAl6b45uX7SF1vjDdqw4xYWvcUCbV/kBE= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye , Harry Ramsey Subject: [PATCH v6 1/3] arm/mpu: implement setup_virt_paging for MPU systems Date: Tue, 12 May 2026 18:57:27 +0100 Message-Id: <20260512175729.1915120-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260512175729.1915120-1-luca.fancellu@arm.com> References: <20260512175729.1915120-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1778608664-ABB60161-24A4E566/0/0 X-purgate-type: clean X-purgate-size: 7761 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1778608694534154100 Content-Type: text/plain; charset="utf-8" From: Penny Zheng Implement setup_virt_paging for AArch64 MPU systems, taking care of stage 2 address translation regime, IPA bits, supported VMID length configuration and VTCR_EL2/VSTCR_EL2 register programming. Implement also the Armv8-R specific changes to ID_AA64MMFR0_EL1, related to the supported memory system architecture (PMSA/VMSA) and check that when MPU is built, the underlying HW is compatible with PMSA. By default MPU at EL2 and EL1 is required. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Signed-off-by: Harry Ramsey Reviewed-by: Michal Orzel --- v5: - removed spaces in inline if condition - Add Michal R-by v4: - Fixed typo in the comments - Fixed typo in the commit title and message - moved p2m_vmid_allocator_init() after write of VTCR_EL2 - Fixed printf format specifier %d -> %u v3: - Refactor unused code to more relevant commits. - Add P2M print information - Formatting issues - Update commit message v2: - Separate commit into multiple commits --- xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ xen/arch/arm/include/asm/cpufeature.h | 13 +++- xen/arch/arm/include/asm/processor.h | 8 +++ 4 files changed, 101 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c index b6d8b2777b58..4547417df97e 100644 --- a/xen/arch/arm/arm64/mpu/p2m.c +++ b/xen/arch/arm/arm64/mpu/p2m.c @@ -2,11 +2,89 @@ =20 #include #include +#include #include =20 void __init setup_virt_paging(void) { - BUG_ON("unimplemented"); + register_t vtcr_el2 =3D READ_SYSREG(VTCR_EL2); + register_t vstcr_el2 =3D READ_SYSREG(VSTCR_EL2); + + /* PA size */ + const unsigned int pa_range_info[] =3D {32, 36, 40, 42, 44, 48, 52, 0, + /* Invalid */}; + + /* + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured + * with IPA bits =3D=3D PA bits, compare against PA size. + */ + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) + p2m_ipa_bits =3D pa_range_info[system_cpuinfo.mm64.pa_range]; + + /* + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identi= fy the + * memory system configurations supported. In Armv8-R AArch64, the + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. + */ + if ( system_cpuinfo.mm64.msa !=3D MM64_MSA_PMSA_SUPPORT ) + goto fault; + + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b001= 0. */ + if ( (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_PMSA_SUPPORT) && + (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_VMSA_SUPPORT) ) + goto fault; + + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ + vtcr_el2 &=3D ~VTCR_MSA; + + /* + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation = output + * address space to access the Secure PA space as Armv8-R only impleme= nts + * secure state. + */ + vtcr_el2 &=3D ~VTCR_NSA; + + /* + * cpuinfo sanitization makes sure we support 16-bits VMID only if all= cores + * are supporting it. + * + * Set the VS bit only if 16 bit VMID is supported. + */ + if ( system_cpuinfo.mm64.vmid_bits =3D=3D MM64_VMID_16_BITS_SUPPORT ) + { + vtcr_el2 |=3D VTCR_VS; + max_vmid =3D MAX_VMID_16_BIT; + } + else + vtcr_el2 &=3D ~VTCR_VS; + + WRITE_SYSREG(vtcr_el2, VTCR_EL2); + + p2m_vmid_allocator_init(); + + /* + * VSTCR_EL2.SA defines secure stage 2 translation output address spac= e. + * To make sure that all stage 2 translations for the Secure PA space = access + * the Secure PA space, we keep SA bit as 0. + * + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS + * configuration is checked against stage 1 NS configuration in EL1&0 + * translation regime for the given address, and generates a fault if = they + * are different, we set SC bit 1. + */ + vstcr_el2 &=3D ~VSTCR_EL2_SA; + vstcr_el2 |=3D VSTCR_EL2_SC; + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); + + printk("P2M: %u-bit IPA with %u-bit PA and %u-bit VMID\n", + p2m_ipa_bits, + pa_range_info[system_cpuinfo.mm64.pa_range], + (MAX_VMID =3D=3D MAX_VMID_16_BIT) ? 16 : 8); + + return; + + fault: + panic("Hardware with no PMSAv8-64 support in any translation regime\n"= ); } =20 /* diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index 19d409d3eb5a..f3c11d871e86 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,10 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +/* Virtualization Secure Translation Control Register */ +#define VSTCR_EL2_SA (_AC(0x1,U) << 30) +#define VSTCR_EL2_SC (_AC(0x1,U) << 20) + #ifdef CONFIG_MPU /* * The Armv8-R AArch64 architecture always executes code in Secure diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/a= sm/cpufeature.h index 13353c8e1ad1..bf902a397068 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -248,6 +248,12 @@ struct cpuinfo_arm { unsigned long tgranule_16K:4; unsigned long tgranule_64K:4; unsigned long tgranule_4K:4; +#ifdef CONFIG_MPU + unsigned long __res0:16; + unsigned long msa:4; + unsigned long msa_frac:4; + unsigned long __res1:8; +#else unsigned long tgranule_16k_2:4; unsigned long tgranule_64k_2:4; unsigned long tgranule_4k_2:4; @@ -255,6 +261,7 @@ struct cpuinfo_arm { unsigned long __res0:8; unsigned long fgt:4; unsigned long ecv:4; +#endif =20 /* MMFR1 */ unsigned long hafdbs:4; @@ -267,13 +274,13 @@ struct cpuinfo_arm { unsigned long xnx:4; unsigned long twed:4; unsigned long ets:4; - unsigned long __res1:4; + unsigned long __res2:4; unsigned long afp:4; - unsigned long __res2:12; + unsigned long __res3:12; unsigned long ecbhb:4; =20 /* MMFR2 */ - unsigned long __res3:64; + unsigned long __res4:64; }; } mm64; =20 diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/as= m/processor.h index 1a48c9ff3b39..895d7cd50244 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -403,6 +403,9 @@ =20 #define VTCR_RES1 (_AC(1,UL)<<31) =20 +#define VTCR_MSA (_AC(0x1,UL)<<31) +#define VTCR_NSA (_AC(0x1,UL)<<30) + /* HCPTR Hyp. Coprocessor Trap Register */ #define HCPTR_TAM ((_AC(1,U)<<30)) #define HCPTR_TTA ((_AC(1,U)<<20)) /* Trap trace registers */ @@ -464,6 +467,11 @@ #define MM64_VMID_16_BITS_SUPPORT 0x2 #endif =20 +#define MM64_MSA_PMSA_SUPPORT 0xf +#define MM64_MSA_FRAC_NONE_SUPPORT 0x0 +#define MM64_MSA_FRAC_PMSA_SUPPORT 0x1 +#define MM64_MSA_FRAC_VMSA_SUPPORT 0x2 + #ifndef __ASSEMBLER__ =20 extern register_t __cpu_logical_map[]; --=20 2.34.1 From nobody Sat May 30 11:15:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1778608693; cv=none; d=zohomail.com; s=zohoarc; b=dBM0LJ0KE13zIdKh4IEvuY9WQ6Bmd0+KEVkAxgj2zj8iOfTZ3MllOlE4JzrASzBPdwOhDA2W2hGBSWxz/4RPYrqEMeXuHS9loJHlZ3Ap1dDwiI1L4+YspOBkZBXPzbL82x96KMflUIYKF+zz79454+irQoXEJU1dRb94lEpOKWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778608693; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5f06KT5/Tu1ZNVozoMI9B7oHEfd72hqe2wAzCyHrqNI=; b=m3pzTDg0VRjmQSmiwjsc+41q6Is1yRiA++zyozW92QPFpC1vT+Clv+qdpEtBfmjZi0HWp82lVjxZqPqMmpYBXKzypz4L07znpGnZQ4/hw6O0AOzZ1+GlblIQsc7lca1SSCbPbnunIKVnbGXqj8qgThAsKt0Vzp5nUNZwEs10sVE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1778608693081729.3240242901455; Tue, 12 May 2026 10:58:13 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1307398.1579120 (Exim 4.92) (envelope-from ) id 1wMrMa-0003VD-Iy; Tue, 12 May 2026 17:57:48 +0000 Received: by outflank-mailman (output) from mailman id 1307398.1579120; Tue, 12 May 2026 17:57:48 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wMrMa-0003Tz-Fu; Tue, 12 May 2026 17:57:48 +0000 Received: by outflank-mailman (input) for mailman id 1307398; Tue, 12 May 2026 17:57:47 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wMrMZ-0003OZ-45 for xen-devel@lists.xenproject.org; Tue, 12 May 2026 17:57:47 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wMrMW-009D7s-Vd for xen-devel@lists.xenproject.org; Tue, 12 May 2026 19:57:46 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 6a036a11-bab6-0a2a0a5309dd-0a2a4502963a-14 for ; Tue, 12 May 2026 19:57:46 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-720697.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 6a036a19-af86-0a2a45020019-d98c6eacd7ce-1 for ; Tue, 12 May 2026 19:57:46 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E6CC51684; Tue, 12 May 2026 10:57:39 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A60AE3F85F; Tue, 12 May 2026 10:57:43 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778608665; bh=pUlihSCtoluRvHSQDgApxcwFy6+3MCxnxU+k0Ku8GtY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TBbSArrt/uJJn0ZPk8KH0Uc5HoDBRzJdPOfk8dunk+ud0bHsMl8NKbiZWoZgLAzT7 H1utUjad+9BZPz3jIv7WhTjgsdbkydUJkoqCHDyRc05g/kAu3vjp9V2ISgAS/aBdci WYTxFgBrnxLIPkUxhHhiVBRnDADroFY1jgRm7rGk= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v6 2/3] arm/mpu: Introduce `v8r_el1_msa` device tree property for domains Date: Tue, 12 May 2026 18:57:28 +0100 Message-Id: <20260512175729.1915120-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260512175729.1915120-1-luca.fancellu@arm.com> References: <20260512175729.1915120-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1778608666-A9B70161-2DB769CA/0/0 X-purgate-type: clean X-purgate-size: 12627 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1778608696495158500 Content-Type: text/plain; charset="utf-8" From: Harry Ramsey Add a new device tree property `v8r_el1_msa` to select the MSA (memory system architecture) at EL1 for Armv8-R architecture: MPU or MMU, the former is the default if the property is not passed. Implement the dom0less path to parse the new device tree property, add a new domctl hypercall input parameter `v8r_el1_msa` for arm and add the sanitisation in arch_sanitise_domain_config(), the parameter is intended to be used on CONFIG_MPU systems and returns an error if selected for MMU. While there, add explicit padding and check that it's zero during arch domain config sanitisation, given the breaking change, bump the XEN_DOMCTL_INTERFACE_VERSION. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v6: - Add explicit padding to `struct xen_arch_domainconfig` and check it - Provide common v8r_el1_msa_domain_sanitise_config() for MMU/MPU - During domu_dt_v8r_el1_msa_parse() set PMSA when property not present - constify *node in domu_dt_v8r_el1_msa_parse() - Print full path of the node in domu_dt_v8r_el1_msa_parse() error msgs - typo fixing v5: - follow the way domu_dt_sci_parse and ARM_SCI is doing, but return error if property is present in MMU systems. - Align the commit message on the new changes - fix documentation - fix multiline comment - drop the explicit padding from struct xen_arch_domainconfig v4: - Rework the patch to have the v8r_el1_msa input parameter more enclosed in the Armv8-A (mmu)/Armv8-R (mpu) space. v3: - Improve commit message and device tree property description - Remove macro protection - Remove unused function is_mpu_domain - Code formatting --- docs/misc/arm/device-tree/booting.txt | 14 +++++ xen/arch/arm/dom0less-build.c | 74 +++++++++++++++++++++++++ xen/arch/arm/domain.c | 37 +++++++++++++ xen/arch/arm/include/asm/domain.h | 4 ++ xen/arch/arm/include/asm/domain_build.h | 10 ++++ xen/arch/arm/mpu/arm32/mm.c | 7 +++ xen/arch/arm/mpu/arm64/mm.c | 7 +++ xen/include/public/arch-arm.h | 7 +++ xen/include/public/domctl.h | 4 +- 9 files changed, 162 insertions(+), 2 deletions(-) diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-t= ree/booting.txt index 977b4286082f..f73839df090b 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -322,6 +322,20 @@ with the following properties: Should be used together with scmi-smc-passthrough Xen command line option. =20 +- v8r_el1_msa + + A string property specifying whether, on Armv8-R systems at EL1, a dom= ain + should use PMSAv8 (MPU) or VMSAv8 (MMU). + + - "mmu" + Enables VMSAv8 at EL1. This requires hardware support and is only + optionally available on AArch64. Not supported on AArch32. + + - "mpu" + Enables PMSAv8 at EL1. This is the default behavior when the property = is + not passed. This configuration requires static allocation (xen,static-= mem) + and direct mapping (direct-map). + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. =20 diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 52cf788a45ea..fecdb33d3e3a 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -302,6 +302,77 @@ static int __init domu_dt_sci_parse(struct dt_device_n= ode *node, return 0; } =20 +static int __init +domu_dt_v8r_el1_msa_parse(const struct dt_device_node *node, + struct xen_domctl_createdomain *d_cfg, + unsigned int flags) +{ + bool property_present =3D dt_property_read_bool(node, "v8r_el1_msa"); + + if ( !IS_ENABLED(CONFIG_MPU) ) + { + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE; + + if ( !property_present ) + return 0; + + printk(XENLOG_ERR + "Not supported 'v8r_el1_msa' DT property found for domain %= s\n", + dt_node_full_name(node)); + return -EINVAL; + } + + if ( !property_present ) + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA; + else + { + const char *v8r_el1_msa; + int ret =3D dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_= msa); + + if ( ret ) + return ret; + + if ( !strcmp(v8r_el1_msa, "mpu") ) + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_= PMSA; + else if ( !strcmp(v8r_el1_msa, "mmu") ) + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_= VMSA; + else + { + printk(XENLOG_ERR + "v8r_el1_msa value (%s) not valid for domain %s\n", + v8r_el1_msa, dt_node_full_name(node)); + return -EINVAL; + } + } + + switch ( d_cfg->arch.v8r_el1_msa ) + { + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA: + if ( !(flags & CDF_staticmem) || !(flags & CDF_directmap) ) + { + printk(XENLOG_ERR + "PMSA is not valid for domain (%s) without static alloc= ation and direct map (v8r_el1_msa)\n", + dt_node_full_name(node)); + return -EINVAL; + } + break; + + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA: + if ( !has_v8r_vmsa_support() ) + { + printk(XENLOG_ERR + "Platform doesn't support VMSA at EL1 (v8r_el1_msa)\n"); + return -EINVAL; + } + break; + + default: + return -EINVAL; + } + + return 0; +} + int __init arch_parse_dom0less_node(struct dt_device_node *node, struct boot_domain *bd) { @@ -315,6 +386,9 @@ int __init arch_parse_dom0less_node(struct dt_device_no= de *node, if ( domu_dt_sci_parse(node, d_cfg) ) panic("Error getting SCI configuration\n"); =20 + if ( domu_dt_v8r_el1_msa_parse(node, d_cfg, flags) ) + panic("Error getting v8r_el1_msa configuration\n"); + if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) ) { int vpl011_virq =3D GUEST_VPL011_SPI; diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..e579c3b1bb3c 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -538,6 +539,24 @@ void vcpu_switch_to_aarch64_mode(struct vcpu *v) v->arch.hcr_el2 |=3D HCR_RW; } =20 +static bool v8r_el1_msa_domain_sanitise_config( + const struct xen_domctl_createdomain *config) +{ + uint8_t v8r_el1_msa =3D config->arch.v8r_el1_msa; + + if ( !IS_ENABLED(CONFIG_MPU) ) + return v8r_el1_msa =3D=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE; + + if ( IS_ENABLED(CONFIG_ARM_32) ) + return v8r_el1_msa =3D=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA; + + if ( IS_ENABLED(CONFIG_ARM_64) ) + return (v8r_el1_msa =3D=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA)= || + (v8r_el1_msa =3D=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA); + + return false; +} + int arch_sanitise_domain_config(struct xen_domctl_createdomain *config) { unsigned int max_vcpus; @@ -554,6 +573,14 @@ int arch_sanitise_domain_config(struct xen_domctl_crea= tedomain *config) return -EINVAL; } =20 + /* Check config structure padding */ + if ( config->arch.pad ) + { + dprintk(XENLOG_INFO, + "Invalid domain configuration during domain creation\n"); + return -EINVAL; + } + /* Check feature flags */ if ( sve_vl_bits > 0 ) { @@ -630,6 +657,12 @@ int arch_sanitise_domain_config(struct xen_domctl_crea= tedomain *config) return -EINVAL; } =20 + if ( !v8r_el1_msa_domain_sanitise_config(config) ) + { + dprintk(XENLOG_INFO, "Unsupported v8r_el1_msa value\n"); + return -EINVAL; + } + return sci_domain_sanitise_config(config); } =20 @@ -722,6 +755,10 @@ int arch_domain_create(struct domain *d, d->arch.sve_vl =3D config->arch.sve_vl; #endif =20 +#ifdef CONFIG_MPU + d->arch.v8r_el1_msa =3D config->arch.v8r_el1_msa; +#endif + if ( (rc =3D sci_domain_init(d, config)) !=3D 0 ) goto fail; =20 diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index b24f02d269be..ac7300e41fcd 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -112,6 +112,10 @@ struct arch_domain #endif =20 struct resume_info resume_ctx; + +#ifdef CONFIG_MPU + uint8_t v8r_el1_msa; +#endif } __cacheline_aligned; =20 struct arch_vcpu diff --git a/xen/arch/arm/include/asm/domain_build.h b/xen/arch/arm/include= /asm/domain_build.h index 6674dac5e2f8..13e88fc0891b 100644 --- a/xen/arch/arm/include/asm/domain_build.h +++ b/xen/arch/arm/include/asm/domain_build.h @@ -19,6 +19,16 @@ int prepare_acpi(struct domain *d, struct kernel_info *k= info); =20 int add_ext_regions(unsigned long s_gfn, unsigned long e_gfn, void *data); =20 +#ifdef CONFIG_MPU +/* Utility function to determine if an Armv8-R processor supports VMSA. */ +bool has_v8r_vmsa_support(void); +#else +static inline bool has_v8r_vmsa_support(void) +{ + return false; +} +#endif /* CONFIG_MPU */ + #endif =20 /* diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c index a4673c351141..702bea804acd 100644 --- a/xen/arch/arm/mpu/arm32/mm.c +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include =20 #define GENERATE_WRITE_PR_REG_CASE(num, pr) \ case num: \ @@ -38,6 +40,11 @@ break; \ } =20 +bool has_v8r_vmsa_support(void) +{ + return false; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c index ed643cad4073..b8abcc6f7bc6 100644 --- a/xen/arch/arm/mpu/arm64/mm.c +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include =20 /* * The following are needed for the cases: GENERATE_WRITE_PR_REG_CASE @@ -32,6 +34,11 @@ break; \ } =20 +bool has_v8r_vmsa_support(void) +{ + return system_cpuinfo.mm64.msa_frac =3D=3D MM64_MSA_FRAC_VMSA_SUPPORT; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index cd563cf70684..7d6f87e8b2b1 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -330,6 +330,10 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 =20 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE 0 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA 1 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA 2 + struct xen_arch_domainconfig { /* IN/OUT */ uint8_t gic_version; @@ -355,6 +359,9 @@ struct xen_arch_domainconfig { uint32_t clock_frequency; /* IN */ uint8_t arm_sci_type; + /* IN */ + uint8_t v8r_el1_msa; + uint16_t pad; }; #endif /* __XEN__ || __XEN_TOOLS__ */ =20 diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 8f6708c0a7cd..23124547f347 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -30,9 +30,9 @@ * fields) don't require a change of the version. * Stable ops are NOT covered by XEN_DOMCTL_INTERFACE_VERSION! * - * Last version bump: Xen 4.19 + * Last version bump: Xen 4.22 */ -#define XEN_DOMCTL_INTERFACE_VERSION 0x00000017 +#define XEN_DOMCTL_INTERFACE_VERSION 0x00000018 =20 /* * NB. xen_domctl.domain is an IN/OUT parameter for this operation. --=20 2.34.1 From nobody Sat May 30 11:15:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1778608694; cv=none; d=zohomail.com; s=zohoarc; b=AxOS4B+chKMSN9ihW2boqAcAfYy8q0re3VGRngvco8fxbDldmYBbekJnkoP+14Ki6OMfKVBt8LqAwEXqpnNJVlKRyA8UzjbnRM2Q9lI225eKAdhUNn5fThBHQIaEWRNkYSqWRoRYXD+QKavdhGQu8hMIgtG29SlQnBLjGoVzxAk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1778608694; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VnAl3j5FIDLNO0VrEyEyvNXiWk6s8GdXVJg/A+ljiz0=; b=U+2Z5teqKPnOUrzKlHOuWrfBXBRkv4JvSFOIOrbSApkKLow+RKYOdm/gdsXMeaIgwxiRZQA9/kDVJT5B5BhUt8KtrEHZ+nVGbtBAk89J3Z6rWUGWIW3UbxPKnlby/fCThmnChHIYEv3g+jPW10gbC4+ibqTsIdwIlTRZezjQpII= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1778608694251221.5862870231157; Tue, 12 May 2026 10:58:14 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1307399.1579132 (Exim 4.92) (envelope-from ) id 1wMrMb-0003pd-Qm; Tue, 12 May 2026 17:57:49 +0000 Received: by outflank-mailman (output) from mailman id 1307399.1579132; Tue, 12 May 2026 17:57:49 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wMrMb-0003pW-Nk; Tue, 12 May 2026 17:57:49 +0000 Received: by outflank-mailman (input) for mailman id 1307399; Tue, 12 May 2026 17:57:48 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wMrMa-0003Q1-Ei for xen-devel@lists.xenproject.org; Tue, 12 May 2026 17:57:48 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wMrMY-009D7s-AA for xen-devel@lists.xenproject.org; Tue, 12 May 2026 19:57:47 +0200 Received: from [10.42.69.2] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 6a036a11-bab6-0a2a0a5309dd-0a2a4502963a-18 for ; Tue, 12 May 2026 19:57:47 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-720697.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 6a036a19-af86-0a2a45020019-d98c6eacd7ce-3 for ; Tue, 12 May 2026 19:57:47 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2EA27168F; Tue, 12 May 2026 10:57:41 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 774F53F85F; Tue, 12 May 2026 10:57:45 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778608666; bh=VCpUi1qw2aTk/5VvkiebTI4EVFxVnB22sLNkwL9YBf4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C8OtUX6BcH+wQikMQAXfmgaR4vGdDRscBuS4SkctVe6FamUTgyyXnMxN4YEMJ7Tzv I+DX034qS0NsfRQU5+YyObmDQMIDl7MVGuHtgU1yFV9EUhYywR1okYmWm72Dg5rLsF AX7szD/UPQBqplpxxgbOy1v6JnbOq5X4Fd7dakUQ= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v6 3/3] arm/mpu: Implement p2m tables Date: Tue, 12 May 2026 18:57:29 +0100 Message-Id: <20260512175729.1915120-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260512175729.1915120-1-luca.fancellu@arm.com> References: <20260512175729.1915120-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1778608667-8336C161-6EE4EC13/0/0 X-purgate-type: clean X-purgate-size: 5922 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1778608696459158500 Content-Type: text/plain; charset="utf-8" From: Harry Ramsey Implement `p2m_alloc_table`, `p2m_init` and `p2m_final_teardown` for MPU systems. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu Reviewed-by: Michal Orzel --- v6: - Included mpu.h for MAX_MPU_REGION_NR - used void* instead of char* in pointer arithmetic - fixed typo in comment - Add Michal R-by v5: - removed comment for P2M_ROOT_PAGES/P2M_ROOT_ORDER - used MAX_MPU_REGION_NR instead of opencoding 255 - use 'table' in p2m_alloc_table to clear pages - remove p2m_free_vmid() from error path in p2m_init() which is already handled outside v4: - no changes v3: - Check for alloc_xenheap_pages allocation - Clear additional page allocated for ARM64 - Add check for INVALID_VCPU_ID - Remove unnecessary function generate_vsctlr - Code formatting fixes --- xen/arch/arm/include/asm/arm32/mpu.h | 2 + xen/arch/arm/include/asm/arm64/mpu.h | 2 + xen/arch/arm/include/asm/mpu/p2m.h | 8 ++++ xen/arch/arm/include/asm/p2m.h | 5 ++ xen/arch/arm/mpu/p2m.c | 72 ++++++++++++++++++++++++++-- 5 files changed, 86 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/as= m/arm32/mpu.h index 2cf0f8cbacae..d565230f84ee 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -11,6 +11,8 @@ */ #define MPU_REGION_RES0 0x0 =20 +#define VSCTLR_VMID_SHIFT 16 + /* Hypervisor Protection Region Base Address Register */ typedef union { struct { diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h index 4f694190a8a3..8b86a03fee44 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -7,6 +7,8 @@ =20 #define MPU_REGION_RES0 (0xFFFFULL << 48) =20 +#define VSCTLR_VMID_SHIFT 48 + /* Protection Region Base Address Register */ typedef union { struct __packed { diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/= mpu/p2m.h index e46d9e757a1d..1484c75b55aa 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -3,8 +3,16 @@ #ifndef __ARM_MPU_P2M_H__ #define __ARM_MPU_P2M_H__ =20 +#include +#include +#include +#include + struct p2m_domain; =20 +#define P2M_ROOT_PAGES DIV_ROUND_UP(MAX_MPU_REGION_NR * sizeof(pr_t), PAGE= _SIZE) +#define P2M_ROOT_ORDER get_count_order(P2M_ROOT_PAGES) + static inline void p2m_clear_root_pages(struct p2m_domain *p2m) {} =20 static inline void p2m_tlb_flush_sync(struct p2m_domain *p2m) {} diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..ed1b6dd40f40 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -48,8 +48,13 @@ struct p2m_domain { /* Current VMID in use */ uint16_t vmid; =20 +#ifdef CONFIG_MMU /* Current Translation Table Base Register for the p2m */ uint64_t vttbr; +#else + /* Current Virtualization System Control Register for the p2m */ + register_t vsctlr; +#endif =20 /* Highest guest frame that's ever been mapped in the p2m */ gfn_t max_mapped_gfn; diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index f7fb58ab6aa8..f3ca8a4ab35f 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -28,10 +28,63 @@ void p2m_dump_info(struct domain *d) BUG_ON("unimplemented"); } =20 +static int p2m_alloc_table(struct domain *d) +{ + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + void *table =3D alloc_xenheap_pages(P2M_ROOT_ORDER, 0); + unsigned int i; + + if ( !table ) + { + printk(XENLOG_G_ERR "%pd: p2m: unable to allocate P2M MPU mapping = table\n", + d); + return -ENOMEM; + } + + p2m->root =3D virt_to_page(table); + + for ( i =3D 0; i < P2M_ROOT_PAGES; i++ ) + clear_page(table + (i * PAGE_SIZE)); + + return 0; +} + int p2m_init(struct domain *d) { - BUG_ON("unimplemented"); - return -EINVAL; + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + int rc =3D 0; + unsigned int cpu; + + rwlock_init(&p2m->lock); + + p2m->vmid =3D INVALID_VMID; + p2m->max_mapped_gfn =3D _gfn(0); + p2m->lowest_mapped_gfn =3D _gfn(ULONG_MAX); + + p2m->default_access =3D p2m_access_rwx; + /* mem_access is NOT supported on MPU system. */ + p2m->mem_access_enabled =3D false; + + /* Ensure that the type chosen is large enough for MAX_VIRT_CPUS. */ + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < MAX_VIRT_CPU= S); + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < INVALID_VCPU= _ID); + + for_each_possible_cpu(cpu) + p2m->last_vcpu_ran[cpu] =3D INVALID_VCPU_ID; + + /* + * "Trivial" initialization is now complete. Set the backpointer so th= at + * p2m_teardown() and related functions know to do something. + */ + p2m->domain =3D d; + + rc =3D p2m_alloc_vmid(d); + if ( rc ) + return rc; + + p2m->vsctlr =3D ((register_t)p2m->vmid << VSCTLR_VMID_SHIFT); + + return p2m_alloc_table(d); } =20 void p2m_save_state(struct vcpu *p) @@ -46,7 +99,20 @@ void p2m_restore_state(struct vcpu *n) =20 void p2m_final_teardown(struct domain *d) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + + /* p2m not actually initialized */ + if ( !p2m->domain ) + return; + + if ( p2m->root ) + free_xenheap_pages(page_to_virt(p2m->root), P2M_ROOT_ORDER); + + p2m->root =3D NULL; + + p2m_free_vmid(d); + + p2m->domain =3D NULL; } =20 bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) --=20 2.34.1