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Fri, 8 May 2026 07:33:59 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D62373F763; Fri, 8 May 2026 07:34:02 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778250844; bh=3OwJmJ83fF7wYUwwajm97vdwH/PiBu+huX5oR7YFd8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GtkHKE7eaEuqzyAEc+28pZDGbOT7oHXCt0WMgxCsQqSWXGwxAbYLMt0apfFw+sy97 VS0dr5OxqufzNH2YDBnrmc2ceWqaY1rn4JZDxQUUpFhkkSrFnk7wJgNNBJo76ytoAq koqbbcb5PHK8FtzsXURapvm1tBchwM+2Axh5yKKo= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye , Harry Ramsey Subject: [PATCH v5 1/3] arm/mpu: implement setup_virt_paging for MPU systems Date: Fri, 8 May 2026 15:33:51 +0100 Message-Id: <20260508143353.3512004-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260508143353.3512004-1-luca.fancellu@arm.com> References: <20260508143353.3512004-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-4011c0/1778250845-7E58E8B7-07AC936A/0/0 X-purgate-type: clean X-purgate-size: 7761 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1778250870128158500 Content-Type: text/plain; charset="utf-8" From: Penny Zheng Implement setup_virt_paging for AArch64 MPU systems, taking care of stage 2 address translation regime, IPA bits, supported VMID length configuration and VTCR_EL2/VSTCR_EL2 register programming. Implement also the Armv8-R specific changes to ID_AA64MMFR0_EL1, related to the supported memory system architecture (PMSA/VMSA) and check that when MPU is built, the underlying HW is compatible with PMSA. By default MPU at EL2 and EL1 is required. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Signed-off-by: Harry Ramsey Reviewed-by: Michal Orzel --- v5: - removed spaces in inline if condition - Add Michal R-by v4: - Fixed typo in the comments - Fixed typo in the commit title and message - moved p2m_vmid_allocator_init() after write of VTCR_EL2 - Fixed printf format specifier %d -> %u v3: - Refactor unused code to more relevant commits. - Add P2M print information - Formatting issues - Update commit message v2: - Separate commit into multiple commits --- xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ xen/arch/arm/include/asm/cpufeature.h | 13 +++- xen/arch/arm/include/asm/processor.h | 8 +++ 4 files changed, 101 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c index b6d8b2777b58..4547417df97e 100644 --- a/xen/arch/arm/arm64/mpu/p2m.c +++ b/xen/arch/arm/arm64/mpu/p2m.c @@ -2,11 +2,89 @@ =20 #include #include +#include #include =20 void __init setup_virt_paging(void) { - BUG_ON("unimplemented"); + register_t vtcr_el2 =3D READ_SYSREG(VTCR_EL2); + register_t vstcr_el2 =3D READ_SYSREG(VSTCR_EL2); + + /* PA size */ + const unsigned int pa_range_info[] =3D {32, 36, 40, 42, 44, 48, 52, 0, + /* Invalid */}; + + /* + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured + * with IPA bits =3D=3D PA bits, compare against PA size. + */ + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) + p2m_ipa_bits =3D pa_range_info[system_cpuinfo.mm64.pa_range]; + + /* + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identi= fy the + * memory system configurations supported. In Armv8-R AArch64, the + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. + */ + if ( system_cpuinfo.mm64.msa !=3D MM64_MSA_PMSA_SUPPORT ) + goto fault; + + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b001= 0. */ + if ( (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_PMSA_SUPPORT) && + (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_VMSA_SUPPORT) ) + goto fault; + + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ + vtcr_el2 &=3D ~VTCR_MSA; + + /* + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation = output + * address space to access the Secure PA space as Armv8-R only impleme= nts + * secure state. + */ + vtcr_el2 &=3D ~VTCR_NSA; + + /* + * cpuinfo sanitization makes sure we support 16-bits VMID only if all= cores + * are supporting it. + * + * Set the VS bit only if 16 bit VMID is supported. + */ + if ( system_cpuinfo.mm64.vmid_bits =3D=3D MM64_VMID_16_BITS_SUPPORT ) + { + vtcr_el2 |=3D VTCR_VS; + max_vmid =3D MAX_VMID_16_BIT; + } + else + vtcr_el2 &=3D ~VTCR_VS; + + WRITE_SYSREG(vtcr_el2, VTCR_EL2); + + p2m_vmid_allocator_init(); + + /* + * VSTCR_EL2.SA defines secure stage 2 translation output address spac= e. + * To make sure that all stage 2 translations for the Secure PA space = access + * the Secure PA space, we keep SA bit as 0. + * + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS + * configuration is checked against stage 1 NS configuration in EL1&0 + * translation regime for the given address, and generates a fault if = they + * are different, we set SC bit 1. + */ + vstcr_el2 &=3D ~VSTCR_EL2_SA; + vstcr_el2 |=3D VSTCR_EL2_SC; + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); + + printk("P2M: %u-bit IPA with %u-bit PA and %u-bit VMID\n", + p2m_ipa_bits, + pa_range_info[system_cpuinfo.mm64.pa_range], + (MAX_VMID =3D=3D MAX_VMID_16_BIT) ? 16 : 8); + + return; + + fault: + panic("Hardware with no PMSAv8-64 support in any translation regime\n"= ); } =20 /* diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index 19d409d3eb5a..f3c11d871e86 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,10 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +/* Virtualization Secure Translation Control Register */ +#define VSTCR_EL2_SA (_AC(0x1,U) << 30) +#define VSTCR_EL2_SC (_AC(0x1,U) << 20) + #ifdef CONFIG_MPU /* * The Armv8-R AArch64 architecture always executes code in Secure diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/a= sm/cpufeature.h index 13353c8e1ad1..bf902a397068 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -248,6 +248,12 @@ struct cpuinfo_arm { unsigned long tgranule_16K:4; unsigned long tgranule_64K:4; unsigned long tgranule_4K:4; +#ifdef CONFIG_MPU + unsigned long __res0:16; + unsigned long msa:4; + unsigned long msa_frac:4; + unsigned long __res1:8; +#else unsigned long tgranule_16k_2:4; unsigned long tgranule_64k_2:4; unsigned long tgranule_4k_2:4; @@ -255,6 +261,7 @@ struct cpuinfo_arm { unsigned long __res0:8; unsigned long fgt:4; unsigned long ecv:4; +#endif =20 /* MMFR1 */ unsigned long hafdbs:4; @@ -267,13 +274,13 @@ struct cpuinfo_arm { unsigned long xnx:4; unsigned long twed:4; unsigned long ets:4; - unsigned long __res1:4; + unsigned long __res2:4; unsigned long afp:4; - unsigned long __res2:12; + unsigned long __res3:12; unsigned long ecbhb:4; =20 /* MMFR2 */ - unsigned long __res3:64; + unsigned long __res4:64; }; } mm64; =20 diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/as= m/processor.h index 1a48c9ff3b39..895d7cd50244 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -403,6 +403,9 @@ =20 #define VTCR_RES1 (_AC(1,UL)<<31) =20 +#define VTCR_MSA (_AC(0x1,UL)<<31) +#define VTCR_NSA (_AC(0x1,UL)<<30) + /* HCPTR Hyp. Coprocessor Trap Register */ #define HCPTR_TAM ((_AC(1,U)<<30)) #define HCPTR_TTA ((_AC(1,U)<<20)) /* Trap trace registers */ @@ -464,6 +467,11 @@ #define MM64_VMID_16_BITS_SUPPORT 0x2 #endif =20 +#define MM64_MSA_PMSA_SUPPORT 0xf +#define MM64_MSA_FRAC_NONE_SUPPORT 0x0 +#define MM64_MSA_FRAC_PMSA_SUPPORT 0x1 +#define MM64_MSA_FRAC_VMSA_SUPPORT 0x2 + #ifndef __ASSEMBLER__ =20 extern register_t __cpu_logical_map[]; --=20 2.34.1 From nobody Sat May 30 11:15:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; 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a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778250846; bh=uOx6o3Ma3CDEZYD8HLSisMuej2xnQvxCr5Ghf1MGQ4g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YfNVCBFMoqLbWa8T0NU2W5xPSWLGjnjVlwGeUxqZ8CEdh5pBw3Czhs9o15L1x92Kp N5LvsV2jEKfW53O758lizcPXFPqV2GOhNIgAg+Mvt+Xdlk2op94Z5dFc/hkEVzquF3 +xGXytZaFPXOmyln83DBdYQkyTChbFbi+yRfEA/g= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v5 2/3] arm/mpu: Introduce `v8r_el1_msa` device tree property for domains Date: Fri, 8 May 2026 15:33:52 +0100 Message-Id: <20260508143353.3512004-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260508143353.3512004-1-luca.fancellu@arm.com> References: <20260508143353.3512004-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-bad1c0/1778250847-8AF8CA53-284254DA/0/0 X-purgate-type: clean X-purgate-size: 11918 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1778250871885158500 Content-Type: text/plain; charset="utf-8" From: Harry Ramsey Add a new device tree property `v8r_el1_msa` to select the MSA (memory system architecture) at EL1 for Armv8-R architecture: MPU or MMU, the former is the default if the property is not passed. Implement the dom0less path to parse the new device tree property, add a new domctl hypercall input parameter `v8r_el1_msa` for arm and add the sanitisation in arch_sanitise_domain_config(), the parameter is intended to be used on CONFIG_MPU systems and returns an error if selected for MMU. Given the breaking change, bump the XEN_DOMCTL_INTERFACE_VERSION. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v5: - follow the way domu_dt_sci_parse and ARM_SCI is doing, but return error if property is present in MMU systems. - Align the commit message on the new changes - fix documentation - fix multiline comment - drop the explicit padding from struct xen_arch_domainconfig v4: - Rework the patch to have the v8r_el1_msa input parameter more enclosed in the Armv8-A (mmu)/Armv8-R (mpu) space. v3: - Improve commit message and device tree property description - Remove macro protection - Remove unused function is_mpu_domain - Code formatting --- docs/misc/arm/device-tree/booting.txt | 14 +++++ xen/arch/arm/dom0less-build.c | 74 +++++++++++++++++++++++++ xen/arch/arm/domain.c | 11 ++++ xen/arch/arm/include/asm/domain.h | 4 ++ xen/arch/arm/include/asm/domain_build.h | 21 +++++++ xen/arch/arm/mpu/arm32/mm.c | 17 ++++++ xen/arch/arm/mpu/arm64/mm.c | 18 ++++++ xen/include/public/arch-arm.h | 6 ++ xen/include/public/domctl.h | 4 +- 9 files changed, 167 insertions(+), 2 deletions(-) diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-t= ree/booting.txt index 977b4286082f..2389ae610963 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -322,6 +322,20 @@ with the following properties: Should be used together with scmi-smc-passthrough Xen command line option. =20 +- v8r_el1_msa + + A string property specifying whether, on Armv8-R systems at EL1, a dom= ain + should use PMSAv8 (MPU) or VMSAv8 (MMU). + + - "mmu" + Enables VMSAv8 at EL1. This requires hardware support and is only + optionally available on AArch64. Not supported on AArch32. + + - "mpu" + Enables PMSAv8 at EL1. This is the default behaviour when the property= is + not passed. This configuration requires static allocation (xen,static-= mem) + and direct mapping (direct-map). + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. =20 diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 6f73c65e5151..2a0671bd0e8e 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -295,6 +295,77 @@ static int __init domu_dt_sci_parse(struct dt_device_n= ode *node, return 0; } =20 +static int __init +domu_dt_v8r_el1_msa_parse(struct dt_device_node *node, + struct xen_domctl_createdomain *d_cfg, + unsigned int flags) +{ + bool property_present =3D dt_property_read_bool(node, "v8r_el1_msa"); + + if ( !property_present ) + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE; + else + { + const char *v8r_el1_msa; + int ret =3D dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_= msa); + + if ( ret ) + return ret; + + if ( !strcmp(v8r_el1_msa, "mpu") ) + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_= PMSA; + else if ( !strcmp(v8r_el1_msa, "mmu") ) + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_= VMSA; + else + { + printk(XENLOG_ERR + "v8r_el1_msa value (%s) not valid for domain %s\n", + v8r_el1_msa, dt_node_name(node)); + return -EINVAL; + } + } + + if ( !IS_ENABLED(CONFIG_MPU) ) + { + if ( !property_present ) + return 0; + + printk(XENLOG_ERR + "Not supported 'v8r_el1_msa' DT property found for domain %= s\n", + dt_node_name(node)); + return -EINVAL; + } + + switch ( d_cfg->arch.v8r_el1_msa ) + { + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE: + fallthrough; + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA: + if ( !(flags & CDF_staticmem) || !(flags & CDF_directmap) ) + { + printk(XENLOG_ERR + "PMSA is not valid for domain (%s) without static alloc= ation and direct map (v8r_el1_msa)\n", + dt_node_name(node)); + return -EINVAL; + } + break; + + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA: + if ( !has_v8r_vmsa_support() ) + { + printk(XENLOG_ERR + "Platform doesn't support VMSA at EL1 (v8r_el1_msa)\n"); + return -EINVAL; + } + break; + + default: + return -EINVAL; + } + + return 0; +} + int __init arch_parse_dom0less_node(struct dt_device_node *node, struct boot_domain *bd) { @@ -308,6 +379,9 @@ int __init arch_parse_dom0less_node(struct dt_device_no= de *node, if ( domu_dt_sci_parse(node, d_cfg) ) panic("Error getting SCI configuration\n"); =20 + if ( domu_dt_v8r_el1_msa_parse(node, d_cfg, flags) ) + panic("Error getting v8r_el1_msa configuration\n"); + if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) ) { int vpl011_virq =3D GUEST_VPL011_SPI; diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..ac7d1abd9c7c 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -630,6 +631,12 @@ int arch_sanitise_domain_config(struct xen_domctl_crea= tedomain *config) return -EINVAL; } =20 + if ( !v8r_el1_msa_domain_sanitise_config(config) ) + { + dprintk(XENLOG_INFO, "Unsupported v8r_el1_msa value\n"); + return -EINVAL; + } + return sci_domain_sanitise_config(config); } =20 @@ -722,6 +729,10 @@ int arch_domain_create(struct domain *d, d->arch.sve_vl =3D config->arch.sve_vl; #endif =20 +#ifdef CONFIG_MPU + d->arch.v8r_el1_msa =3D config->arch.v8r_el1_msa; +#endif + if ( (rc =3D sci_domain_init(d, config)) !=3D 0 ) goto fail; =20 diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index b24f02d269be..ac7300e41fcd 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -112,6 +112,10 @@ struct arch_domain #endif =20 struct resume_info resume_ctx; + +#ifdef CONFIG_MPU + uint8_t v8r_el1_msa; +#endif } __cacheline_aligned; =20 struct arch_vcpu diff --git a/xen/arch/arm/include/asm/domain_build.h b/xen/arch/arm/include= /asm/domain_build.h index 6674dac5e2f8..50ddc0511e7e 100644 --- a/xen/arch/arm/include/asm/domain_build.h +++ b/xen/arch/arm/include/asm/domain_build.h @@ -19,6 +19,27 @@ int prepare_acpi(struct domain *d, struct kernel_info *k= info); =20 int add_ext_regions(unsigned long s_gfn, unsigned long e_gfn, void *data); =20 +#ifdef CONFIG_MPU +/* Utility function to determine if an Armv8-R processor supports VMSA. */ +bool has_v8r_vmsa_support(void); +bool v8r_el1_msa_domain_sanitise_config( + const struct xen_domctl_createdomain *config); +#else +static inline bool has_v8r_vmsa_support(void) +{ + return false; +} + +static inline bool v8r_el1_msa_domain_sanitise_config( + const struct xen_domctl_createdomain *config) +{ + if ( config->arch.v8r_el1_msa !=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_N= ONE ) + return false; + + return true; +} +#endif /* CONFIG_MPU */ + #endif =20 /* diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c index a4673c351141..a759ebdfc124 100644 --- a/xen/arch/arm/mpu/arm32/mm.c +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include =20 #define GENERATE_WRITE_PR_REG_CASE(num, pr) \ case num: \ @@ -38,6 +40,21 @@ break; \ } =20 +bool has_v8r_vmsa_support(void) +{ + return false; +} + +bool v8r_el1_msa_domain_sanitise_config( + const struct xen_domctl_createdomain *config) +{ + if ( config->arch.v8r_el1_msa !=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_N= ONE && + config->arch.v8r_el1_msa !=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_P= MSA ) + return false; + + return true; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c index ed643cad4073..441d209601c1 100644 --- a/xen/arch/arm/mpu/arm64/mm.c +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -5,6 +5,8 @@ #include #include #include +#include +#include =20 /* * The following are needed for the cases: GENERATE_WRITE_PR_REG_CASE @@ -32,6 +34,22 @@ break; \ } =20 +bool has_v8r_vmsa_support(void) +{ + return system_cpuinfo.mm64.msa_frac =3D=3D MM64_MSA_FRAC_VMSA_SUPPORT; +} + +bool v8r_el1_msa_domain_sanitise_config( + const struct xen_domctl_createdomain *config) +{ + if ( config->arch.v8r_el1_msa !=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_N= ONE && + config->arch.v8r_el1_msa !=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_P= MSA && + config->arch.v8r_el1_msa !=3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_V= MSA ) + return false; + + return true; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index cd563cf70684..6d222f15f6d5 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -330,6 +330,10 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 =20 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE 0 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA 1 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA 2 + struct xen_arch_domainconfig { /* IN/OUT */ uint8_t gic_version; @@ -355,6 +359,8 @@ struct xen_arch_domainconfig { uint32_t clock_frequency; /* IN */ uint8_t arm_sci_type; + /* IN */ + uint8_t v8r_el1_msa; }; #endif /* __XEN__ || __XEN_TOOLS__ */ =20 diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 8f6708c0a7cd..23124547f347 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -30,9 +30,9 @@ * fields) don't require a change of the version. * Stable ops are NOT covered by XEN_DOMCTL_INTERFACE_VERSION! * - * Last version bump: Xen 4.19 + * Last version bump: Xen 4.22 */ -#define XEN_DOMCTL_INTERFACE_VERSION 0x00000017 +#define XEN_DOMCTL_INTERFACE_VERSION 0x00000018 =20 /* * NB. xen_domctl.domain is an IN/OUT parameter for this operation. --=20 2.34.1 From nobody Sat May 30 11:15:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778250848; bh=+4j7r30qXJ3aM1HfODFFXXITIfg6L1ltdhkKBsZq2Gw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ud4MLurcDiQ/Ou5vERRTxiUlb0uetXgD4hULtOJqqP7m8pOB7jFwk9WbNn/d08t// PNKW7qSvQ/ZiDNaWmR0o/GT2TKWidfh0k6EqFBFgdrGFYx1BhVugWaNRNxTGyvvC/2 S+2MiC1kEB/TzU+KUGFhUPxxS8xp3bB5xnKJJjWk= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v5 3/3] arm/mpu: Implement p2m tables Date: Fri, 8 May 2026 15:33:53 +0100 Message-Id: <20260508143353.3512004-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260508143353.3512004-1-luca.fancellu@arm.com> References: <20260508143353.3512004-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-42698a/1778250849-19B68F3B-C370D5E2/0/0 X-purgate-type: clean X-purgate-size: 5702 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1778250876081154100 Content-Type: text/plain; charset="utf-8" From: Harry Ramsey Implement `p2m_alloc_table`, `p2m_init` and `p2m_final_teardown` for MPU systems. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu Reviewed-by: Michal Orzel --- v5: - removed comment for P2M_ROOT_PAGES/P2M_ROOT_ORDER - used MAX_MPU_REGION_NR instead of opencoding 255 - use 'table' in p2m_alloc_table to clear pages - remove p2m_free_vmid() from error path in p2m_init() which is already handled outside v4: - no changes v3: - Check for alloc_xenheap_pages allocation - Clear additional page allocated for ARM64 - Add check for INVALID_VCPU_ID - Remove unnecessary function generate_vsctlr - Code formatting fixes --- xen/arch/arm/include/asm/arm32/mpu.h | 2 + xen/arch/arm/include/asm/arm64/mpu.h | 2 + xen/arch/arm/include/asm/mpu/p2m.h | 7 +++ xen/arch/arm/include/asm/p2m.h | 5 ++ xen/arch/arm/mpu/p2m.c | 72 ++++++++++++++++++++++++++-- 5 files changed, 85 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/as= m/arm32/mpu.h index 2cf0f8cbacae..d565230f84ee 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -11,6 +11,8 @@ */ #define MPU_REGION_RES0 0x0 =20 +#define VSCTLR_VMID_SHIFT 16 + /* Hypervisor Protection Region Base Address Register */ typedef union { struct { diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h index 4f694190a8a3..8b86a03fee44 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -7,6 +7,8 @@ =20 #define MPU_REGION_RES0 (0xFFFFULL << 48) =20 +#define VSCTLR_VMID_SHIFT 48 + /* Protection Region Base Address Register */ typedef union { struct __packed { diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/= mpu/p2m.h index e46d9e757a1d..0d4149c71987 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -3,8 +3,15 @@ #ifndef __ARM_MPU_P2M_H__ #define __ARM_MPU_P2M_H__ =20 +#include +#include +#include + struct p2m_domain; =20 +#define P2M_ROOT_PAGES DIV_ROUND_UP(MAX_MPU_REGION_NR * sizeof(pr_t), PAGE= _SIZE) +#define P2M_ROOT_ORDER get_count_order(P2M_ROOT_PAGES) + static inline void p2m_clear_root_pages(struct p2m_domain *p2m) {} =20 static inline void p2m_tlb_flush_sync(struct p2m_domain *p2m) {} diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..ed1b6dd40f40 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -48,8 +48,13 @@ struct p2m_domain { /* Current VMID in use */ uint16_t vmid; =20 +#ifdef CONFIG_MMU /* Current Translation Table Base Register for the p2m */ uint64_t vttbr; +#else + /* Current Virtualization System Control Register for the p2m */ + register_t vsctlr; +#endif =20 /* Highest guest frame that's ever been mapped in the p2m */ gfn_t max_mapped_gfn; diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index f7fb58ab6aa8..8d5c65b1003f 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -28,10 +28,63 @@ void p2m_dump_info(struct domain *d) BUG_ON("unimplemented"); } =20 +static int p2m_alloc_table(struct domain *d) +{ + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + char *table =3D alloc_xenheap_pages(P2M_ROOT_ORDER, 0); + unsigned int i; + + if ( !table ) + { + printk(XENLOG_G_ERR "%pd: p2m: unable to allocate P2M MPU mapping = table\n", + d); + return -ENOMEM; + } + + p2m->root =3D virt_to_page(table); + + for ( i =3D 0; i < P2M_ROOT_PAGES; i++ ) + clear_page(table + (i * PAGE_SIZE)); + + return 0; +} + int p2m_init(struct domain *d) { - BUG_ON("unimplemented"); - return -EINVAL; + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + int rc =3D 0; + unsigned int cpu; + + rwlock_init(&p2m->lock); + + p2m->vmid =3D INVALID_VMID; + p2m->max_mapped_gfn =3D _gfn(0); + p2m->lowest_mapped_gfn =3D _gfn(ULONG_MAX); + + p2m->default_access =3D p2m_access_rwx; + /* mem_access is NOT supported in MPU system. */ + p2m->mem_access_enabled =3D false; + + /* Ensure that the type chosen is large enough for MAX_VIRT_CPUS. */ + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < MAX_VIRT_CPU= S); + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < INVALID_VCPU= _ID); + + for_each_possible_cpu(cpu) + p2m->last_vcpu_ran[cpu] =3D INVALID_VCPU_ID; + + /* + * "Trivial" initialization is now complete. Set the backpointer so th= at + * p2m_teardown() and related functions know to do something. + */ + p2m->domain =3D d; + + rc =3D p2m_alloc_vmid(d); + if ( rc ) + return rc; + + p2m->vsctlr =3D ((register_t)p2m->vmid << VSCTLR_VMID_SHIFT); + + return p2m_alloc_table(d); } =20 void p2m_save_state(struct vcpu *p) @@ -46,7 +99,20 @@ void p2m_restore_state(struct vcpu *n) =20 void p2m_final_teardown(struct domain *d) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + + /* p2m not actually initialized */ + if ( !p2m->domain ) + return; + + if ( p2m->root ) + free_xenheap_pages(page_to_virt(p2m->root), P2M_ROOT_ORDER); + + p2m->root =3D NULL; + + p2m_free_vmid(d); + + p2m->domain =3D NULL; } =20 bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) --=20 2.34.1