From nobody Tue May 5 08:59:09 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1776694995; cv=none; d=zohomail.com; s=zohoarc; b=legZm2FvaS2Y1p7M1/oqaPG+X1tC05HeWMMRUGAJHq1WiprY+Y6vHg3dknHnNU9qmL2JFIj8EQSC7VF3UPs/OhSAqFqw14Qsg1/iCufbKZxD+5EWMDwV5ctP94j0KflckvIuq0X5uJ1neUAX4IfLehmChatO214lbFoWpOdCCEA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776694995; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9yGjTfwXPwxHU2mY16tZv9s5eJGx5BBz0N9y2Yfqgns=; b=PWOPv+WuYX1QxDUmlBqii+/6yi2TBL06dABGpvV0FT9dUWzYu7TCKVo/FRgc9mBV1o4UuW0/+n1QzxmOanH2yMHSWGf3vNC1RqDsOckoyYl4p1upq11+DgtKRW2Q0/q3hf/Bg12xp811K9Fo8SOvABIGL3zk2cRXv8JQ/fI5fYA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1776694995879611.4685007975781; Mon, 20 Apr 2026 07:23:15 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1286046.1567169 (Exim 4.92) (envelope-from ) id 1wEpWV-0002KP-UB; Mon, 20 Apr 2026 14:22:51 +0000 Received: by outflank-mailman (output) from mailman id 1286046.1567169; Mon, 20 Apr 2026 14:22:51 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWV-0002KI-QI; Mon, 20 Apr 2026 14:22:51 +0000 Received: by outflank-mailman (input) for mailman id 1286046; Mon, 20 Apr 2026 14:22:50 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWU-000279-BE for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:22:50 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpWT-00BEkZ-O9 for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:22:49 +0200 Received: from [10.42.69.8] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e636b7-2eae-0a2a0a5409dd-0a2a4508c8cc-8 for ; Mon, 20 Apr 2026 16:22:49 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-c1860d.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e636b8-63b5-0a2a45080019-d98c6eacb7ce-1 for ; Mon, 20 Apr 2026 16:22:49 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDC8916F2; Mon, 20 Apr 2026 07:22:42 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 195AE3F7B4; Mon, 20 Apr 2026 07:22:46 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776694968; bh=qYmTbaJ+SsNtBEDJGVlBV6iD643KjLqETko4igFDlkY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AHi1STTNBpVKXfpv079dXbuoiWoVd8MqQlYxAzKxc3yXlPOdOgL0bBhpEDROFCA7g Um92Yg56HabhO1ka3LIKtPEWWz4oJELcwCNPjzr4NFgXX5WYX5FtDf7ZZ+KVRUd+dn tdnq/F12nPXai/UNox5EUWwbYyUIoSsqHS8tPnIY= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye , Harry Ramsey Subject: [PATCH v4 1/3] arm/mpu: implement setup_virt_paging for MPU systems Date: Mon, 20 Apr 2026 15:22:22 +0100 Message-Id: <20260420142224.1802911-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142224.1802911-1-luca.fancellu@arm.com> References: <20260420142224.1802911-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c1860d/1776694969-C0965DB1-E750CBF4/0/0 X-purgate-type: clean X-purgate-size: 7646 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1776694998723154100 Content-Type: text/plain; charset="utf-8" From: Penny Zheng Implement setup_virt_paging for AArch64 MPU systems, taking care of stage 2 address translation regime, IPA bits, supported VMID length configuration and VTCR_EL2/VSTCR_EL2 register programming. Implement also the Armv8-R specific changes to ID_AA64MMFR0_EL1, related to the supported memory system architecture (PMSA/VMSA) and check that when MPU is built, the underlying HW is compatible with PMSA. By default MPU at EL2 and EL1 is required. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Signed-off-by: Harry Ramsey Reviewed-by: Michal Orzel --- v4: - Fixed typo in the comments - Fixed typo in the commit title and message - moved p2m_vmid_allocator_init() after write of VTCR_EL2 - Fixed printf format specifier %d -> %u v3: - Refactor unused code to more relevant commits. - Add P2M print information - Formatting issues - Update commit message v2: - Separate commit into multiple commits --- xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ xen/arch/arm/include/asm/cpufeature.h | 13 +++- xen/arch/arm/include/asm/processor.h | 8 +++ 4 files changed, 101 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c index b6d8b2777b58..a39a1fc38946 100644 --- a/xen/arch/arm/arm64/mpu/p2m.c +++ b/xen/arch/arm/arm64/mpu/p2m.c @@ -2,11 +2,89 @@ =20 #include #include +#include #include =20 void __init setup_virt_paging(void) { - BUG_ON("unimplemented"); + register_t vtcr_el2 =3D READ_SYSREG(VTCR_EL2); + register_t vstcr_el2 =3D READ_SYSREG(VSTCR_EL2); + + /* PA size */ + const unsigned int pa_range_info[] =3D {32, 36, 40, 42, 44, 48, 52, 0, + /* Invalid */}; + + /* + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured + * with IPA bits =3D=3D PA bits, compare against PA size. + */ + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) + p2m_ipa_bits =3D pa_range_info[system_cpuinfo.mm64.pa_range]; + + /* + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identi= fy the + * memory system configurations supported. In Armv8-R AArch64, the + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. + */ + if ( system_cpuinfo.mm64.msa !=3D MM64_MSA_PMSA_SUPPORT ) + goto fault; + + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b001= 0. */ + if ( (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_PMSA_SUPPORT) && + (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_VMSA_SUPPORT) ) + goto fault; + + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ + vtcr_el2 &=3D ~VTCR_MSA; + + /* + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation = output + * address space to access the Secure PA space as Armv8-R only impleme= nts + * secure state. + */ + vtcr_el2 &=3D ~VTCR_NSA; + + /* + * cpuinfo sanitization makes sure we support 16-bits VMID only if all= cores + * are supporting it. + * + * Set the VS bit only if 16 bit VMID is supported. + */ + if ( system_cpuinfo.mm64.vmid_bits =3D=3D MM64_VMID_16_BITS_SUPPORT ) + { + vtcr_el2 |=3D VTCR_VS; + max_vmid =3D MAX_VMID_16_BIT; + } + else + vtcr_el2 &=3D ~VTCR_VS; + + WRITE_SYSREG(vtcr_el2, VTCR_EL2); + + p2m_vmid_allocator_init(); + + /* + * VSTCR_EL2.SA defines secure stage 2 translation output address spac= e. + * To make sure that all stage 2 translations for the Secure PA space = access + * the Secure PA space, we keep SA bit as 0. + * + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS + * configuration is checked against stage 1 NS configuration in EL1&0 + * translation regime for the given address, and generates a fault if = they + * are different, we set SC bit 1. + */ + vstcr_el2 &=3D ~VSTCR_EL2_SA; + vstcr_el2 |=3D VSTCR_EL2_SC; + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); + + printk("P2M: %u-bit IPA with %u-bit PA and %u-bit VMID\n", + p2m_ipa_bits, + pa_range_info[system_cpuinfo.mm64.pa_range], + ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) ? 16 : 8); + + return; + + fault: + panic("Hardware with no PMSAv8-64 support in any translation regime\n"= ); } =20 /* diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index 19d409d3eb5a..f3c11d871e86 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,10 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +/* Virtualization Secure Translation Control Register */ +#define VSTCR_EL2_SA (_AC(0x1,U) << 30) +#define VSTCR_EL2_SC (_AC(0x1,U) << 20) + #ifdef CONFIG_MPU /* * The Armv8-R AArch64 architecture always executes code in Secure diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/a= sm/cpufeature.h index 13353c8e1ad1..bf902a397068 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -248,6 +248,12 @@ struct cpuinfo_arm { unsigned long tgranule_16K:4; unsigned long tgranule_64K:4; unsigned long tgranule_4K:4; +#ifdef CONFIG_MPU + unsigned long __res0:16; + unsigned long msa:4; + unsigned long msa_frac:4; + unsigned long __res1:8; +#else unsigned long tgranule_16k_2:4; unsigned long tgranule_64k_2:4; unsigned long tgranule_4k_2:4; @@ -255,6 +261,7 @@ struct cpuinfo_arm { unsigned long __res0:8; unsigned long fgt:4; unsigned long ecv:4; +#endif =20 /* MMFR1 */ unsigned long hafdbs:4; @@ -267,13 +274,13 @@ struct cpuinfo_arm { unsigned long xnx:4; unsigned long twed:4; unsigned long ets:4; - unsigned long __res1:4; + unsigned long __res2:4; unsigned long afp:4; - unsigned long __res2:12; + unsigned long __res3:12; unsigned long ecbhb:4; =20 /* MMFR2 */ - unsigned long __res3:64; + unsigned long __res4:64; }; } mm64; =20 diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/as= m/processor.h index 1a48c9ff3b39..895d7cd50244 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -403,6 +403,9 @@ =20 #define VTCR_RES1 (_AC(1,UL)<<31) =20 +#define VTCR_MSA (_AC(0x1,UL)<<31) +#define VTCR_NSA (_AC(0x1,UL)<<30) + /* HCPTR Hyp. Coprocessor Trap Register */ #define HCPTR_TAM ((_AC(1,U)<<30)) #define HCPTR_TTA ((_AC(1,U)<<20)) /* Trap trace registers */ @@ -464,6 +467,11 @@ #define MM64_VMID_16_BITS_SUPPORT 0x2 #endif =20 +#define MM64_MSA_PMSA_SUPPORT 0xf +#define MM64_MSA_FRAC_NONE_SUPPORT 0x0 +#define MM64_MSA_FRAC_PMSA_SUPPORT 0x1 +#define MM64_MSA_FRAC_VMSA_SUPPORT 0x2 + #ifndef __ASSEMBLER__ =20 extern register_t __cpu_logical_map[]; --=20 2.34.1 From nobody Tue May 5 08:59:09 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1776694992; cv=none; d=zohomail.com; s=zohoarc; b=a7WJ9ldJdf59kfV9wJYbNSdlXg/7kE4OPonCLrikP0VGUqKww7nQxXI5oRSpmPe/2YaFiyW2JD9CwsHCcHP7DSo7XmR9sbuhEmjkRqVVU6ZnMbbKWRrUA96SbwPoQCLp8/ceLk2DEHJZCw4B80FSok1SzJey7J7f8m/znu9y34g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776694992; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cycqb8Glc5bvD1Q4TdXFQweI5CmZC0Tkv6ld18NIQhI=; b=j7K+g9ADEceNyARV5nZZnk2UV0vH+lsiIYY6xth7tw8V8DHO5SaDg5PEuoo60ycozarha5E5QHdPMGvmN4Enleh18Enoh3Cm+TUKzHzhSRWti9yYXAZv9NqjjpoHod/04tf1LgMiz62Mi9dhP3Zh56Mdp4ix/WBOgQZXsn/c/pg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1776694992126166.5563304900753; Mon, 20 Apr 2026 07:23:12 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1286048.1567177 (Exim 4.92) (envelope-from ) id 1wEpWX-0002Xa-2q; Mon, 20 Apr 2026 14:22:53 +0000 Received: by outflank-mailman (output) from mailman id 1286048.1567177; Mon, 20 Apr 2026 14:22:53 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWX-0002XT-0F; Mon, 20 Apr 2026 14:22:53 +0000 Received: by outflank-mailman (input) for mailman id 1286048; Mon, 20 Apr 2026 14:22:52 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWW-0002Oa-9c for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:22:52 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpWV-000Q5n-Mh for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:22:51 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e636b5-e002-0a2a0a5209dd-0a2a450bd802-14 for ; Mon, 20 Apr 2026 16:22:51 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-42698a.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e636ba-212f-0a2a450b0019-d98c6eacb892-1 for ; Mon, 20 Apr 2026 16:22:51 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B8A516F3; Mon, 20 Apr 2026 07:22:44 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B51A73F7B4; Mon, 20 Apr 2026 07:22:48 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776694970; bh=+vsui9ontMRbImpr24T712HFqgwztKghYeAs6axxQu4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m38uLElW2SN88vFJmSSpwqVV8dKLr9Lbp4AxlgCsc1zUQDEzF+Umb/3wGlILHWY/I M09xu8MndOKOFF44+ps7FUj+5dISiq8ySeIgEdEqeghFnWq0JjNtUUnlyDnCZxzKo2 G7i66FNS51Vz5RLkuDkyLKNckEVha/8ScqSngKfE= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Andrew Cooper , Anthony PERARD , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= Subject: [PATCH v4 2/3] arm/mpu: Introduce `v8r_el1_msa` device tree property for domains Date: Mon, 20 Apr 2026 15:22:23 +0100 Message-Id: <20260420142224.1802911-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142224.1802911-1-luca.fancellu@arm.com> References: <20260420142224.1802911-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-42698a/1776694971-0636CF3B-4468D4B2/0/0 X-purgate-type: clean X-purgate-size: 13636 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1776694993017158500 Content-Type: text/plain; charset="utf-8" From: Harry Ramsey Add a new device tree property `v8r_el1_msa` to select the MSA (memory system architecture) at EL1 for Armv8-R architecture: MPU or MMU, the former is the default if the property is not passed. The check and setting of this new input parameter for the guest configuration is performed in arch_domain_create() instead of the more usual arch_sanitise_domain_config() because the former has access to the Xen internal guest creation flags which are required to ensure PMSA can work (domain requires static allocation and direct mapping). The property is valid only when used on MPU systems and will result in a panic on MMU ones. Bumped XEN_DOMCTL_INTERFACE_VERSION because of the new domctl input parameter. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v4: - Rework the patch to have the v8r_el1_msa input parameter more enclosed in the Armv8-A (mmu)/Armv8-R (mpu) space. v3: - Improve commit message and device tree property description - Remove macro protection - Remove unused function is_mpu_domain - Code formatting --- docs/misc/arm/device-tree/booting.txt | 14 ++++ xen/arch/arm/dom0less-build.c | 3 + xen/arch/arm/domain.c | 4 ++ xen/arch/arm/include/asm/domain.h | 4 ++ xen/arch/arm/include/asm/domain_build.h | 8 +++ xen/arch/arm/include/asm/mmu/domain-build.h | 46 +++++++++++++ xen/arch/arm/include/asm/mpu.h | 5 ++ xen/arch/arm/include/asm/mpu/domain-build.h | 27 ++++++++ xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/arm32/mm.c | 5 ++ xen/arch/arm/mpu/arm64/mm.c | 5 ++ xen/arch/arm/mpu/domain-build.c | 76 +++++++++++++++++++++ xen/include/public/arch-arm.h | 7 ++ xen/include/public/domctl.h | 4 +- 14 files changed, 207 insertions(+), 2 deletions(-) create mode 100644 xen/arch/arm/include/asm/mmu/domain-build.h create mode 100644 xen/arch/arm/include/asm/mpu/domain-build.h create mode 100644 xen/arch/arm/mpu/domain-build.c diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-t= ree/booting.txt index 977b4286082f..c3f484a3b01a 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -322,6 +322,20 @@ with the following properties: Should be used together with scmi-smc-passthrough Xen command line option. =20 +- v8r_el1_msa + + A string property specifying whether, on Armv8-R systems, a domain + should use PMSAv8 (MPU) at EL1 or VMSAv8 (MMU) at EL1. + + - "mmu" + Enables VMSAv8 at EL1. This requires hardware support and is only + optionally available on AArch64. + + - "mpu" + Enables PMSAv8 at EL1. This is the default behaviour when the property= is + not passed. This configuration requires static allocation (xen,static-= mem) + and direct mapping (direct-map). + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. =20 diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c105389a..6f0256f9d825 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -24,6 +24,7 @@ #include #include #include +#include #include =20 #ifdef CONFIG_VGICV2 @@ -322,6 +323,8 @@ int __init arch_parse_dom0less_node(struct dt_device_no= de *node, if ( domu_dt_sci_parse(node, d_cfg) ) panic("Error getting SCI configuration\n"); =20 + arch_dt_v8r_el1_msa_parse(node, d_cfg); + if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) ) { int vpl011_virq =3D GUEST_VPL011_SPI; diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..dfa7ace1141b 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -725,6 +726,9 @@ int arch_domain_create(struct domain *d, if ( (rc =3D sci_domain_init(d, config)) !=3D 0 ) goto fail; =20 + if ( (rc =3D arch_set_v8r_el1_msa(d, config, flags)) !=3D 0 ) + goto fail; + return 0; =20 fail: diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index ffe5d0d9f0a6..4a3fb825962b 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -128,6 +128,10 @@ struct arch_domain #endif =20 struct resume_info resume_ctx; + +#ifdef CONFIG_MPU + uint8_t v8r_el1_msa; +#endif } __cacheline_aligned; =20 struct arch_vcpu diff --git a/xen/arch/arm/include/asm/domain_build.h b/xen/arch/arm/include= /asm/domain_build.h index 6674dac5e2f8..921d6f98f4f4 100644 --- a/xen/arch/arm/include/asm/domain_build.h +++ b/xen/arch/arm/include/asm/domain_build.h @@ -4,6 +4,14 @@ #include #include =20 +#if defined(CONFIG_MMU) +#include +#elif defined(CONFIG_MPU) +#include +#else +# error "Unknown memory management layout" +#endif + typedef __be32 gic_interrupt_t[3]; int make_psci_node(void *fdt); void evtchn_allocate(struct domain *d); diff --git a/xen/arch/arm/include/asm/mmu/domain-build.h b/xen/arch/arm/inc= lude/asm/mmu/domain-build.h new file mode 100644 index 000000000000..3e0d9a6a2a08 --- /dev/null +++ b/xen/arch/arm/include/asm/mmu/domain-build.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MMU_DOMAIN_BUILD_H__ +#define __ARM_MMU_DOMAIN_BUILD_H__ + +#include +#include +#include +#include +#include + +static inline +void arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, + struct xen_domctl_createdomain *d_cfg) +{ + const char *v8r_el1_msa; + + if ( !dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_msa) ) + panic("'v8r_el1_msa' property found, but CONFIG_MPU not selected\n= "); +} + +static inline +int arch_set_v8r_el1_msa(struct domain *d, + const struct xen_domctl_createdomain *config, + unsigned int flags) +{ + if ( config->arch.v8r_el1_msa ) + { + dprintk(XENLOG_INFO, + "arch.v8r_el1_msa set, but CONFIG_MPU not selected\n"); + return -EINVAL; + } + + return 0; +} + +#endif /* __ARM_MMU_DOMAIN_BUILD_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 72fa5b00b861..8a8c01086206 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -27,6 +27,11 @@ =20 #ifndef __ASSEMBLER__ =20 +/* + * Utility function to determine if an Armv8-R processor supports VMSA. + */ +bool has_v8r_vmsa_support(void); + /* * Set base address of MPU protection region. * diff --git a/xen/arch/arm/include/asm/mpu/domain-build.h b/xen/arch/arm/inc= lude/asm/mpu/domain-build.h new file mode 100644 index 000000000000..463cd85b5b7e --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/domain-build.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ARM_MPU_DOMAIN_BUILD_H__ +#define __ARM_MPU_DOMAIN_BUILD_H__ + +#include +#include +#include +#include + +void arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, + struct xen_domctl_createdomain *d_cfg); + +int arch_set_v8r_el1_msa(struct domain *d, + const struct xen_domctl_createdomain *config, + unsigned int flags); + +#endif /* __ARM_MPU_DOMAIN_BUILD_H__ */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 3327fadd5d0e..e3997e41b81b 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_ARM_32) +=3D arm32/ obj-$(CONFIG_ARM_64) +=3D arm64/ +obj-y +=3D domain-build.o obj-y +=3D domain-page.o obj-y +=3D mm.o obj-y +=3D p2m.o diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c index a4673c351141..5eaeb3400e6c 100644 --- a/xen/arch/arm/mpu/arm32/mm.c +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -38,6 +38,11 @@ break; \ } =20 +bool has_v8r_vmsa_support(void) +{ + return false; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c index ed643cad4073..b07e729a7d05 100644 --- a/xen/arch/arm/mpu/arm64/mm.c +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -32,6 +32,11 @@ break; \ } =20 +bool has_v8r_vmsa_support(void) +{ + return system_cpuinfo.mm64.msa_frac =3D=3D MM64_MSA_FRAC_VMSA_SUPPORT; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: diff --git a/xen/arch/arm/mpu/domain-build.c b/xen/arch/arm/mpu/domain-buil= d.c new file mode 100644 index 000000000000..1bdd0ffedebb --- /dev/null +++ b/xen/arch/arm/mpu/domain-build.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void __init arch_dt_v8r_el1_msa_parse(struct dt_device_node *node, + struct xen_domctl_createdomain *d_cf= g) +{ + const char *v8r_el1_msa; + + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE; + + if ( !dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_msa) ) + { + if ( !strcmp(v8r_el1_msa, "mmu") ) + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_= VMSA; + else if ( !strcmp(v8r_el1_msa, "mpu") ) + d_cfg->arch.v8r_el1_msa =3D XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_= PMSA; + else + panic("Invalid device tree option for v8r_el1_msa\n"); + } +} + +int arch_set_v8r_el1_msa(struct domain *d, + const struct xen_domctl_createdomain *config, + unsigned int flags) +{ + switch ( config->arch.v8r_el1_msa ) + { + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE: + fallthrough; + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA: + if ( !(flags & CDF_staticmem) || !(flags & CDF_directmap) ) + { + dprintk(XENLOG_INFO, + "PMSA is not valid for domain without static allocatio= n and direct map (v8r_el1_msa)\n"); + return -EINVAL; + } + break; + + case XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA: + if ( !has_v8r_vmsa_support() ) + { + dprintk(XENLOG_INFO, + "Platform does not support VMSA at EL1 (v8r_el1_msa)\n= "); + return -EINVAL; + } + break; + + default: + dprintk(XENLOG_INFO, "Unsupported arch.v8r_el1_msa value (%u)\n", + config->arch.v8r_el1_msa); + return -EINVAL; + } + + d->arch.v8r_el1_msa =3D config->arch.v8r_el1_msa; + + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index cd563cf70684..7d6f87e8b2b1 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -330,6 +330,10 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); #define XEN_DOMCTL_CONFIG_ARM_SCI_NONE 0 #define XEN_DOMCTL_CONFIG_ARM_SCI_SCMI_SMC 1 =20 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_NONE 0 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_PMSA 1 +#define XEN_DOMCTL_CONFIG_ARM_V8R_EL1_MSA_VMSA 2 + struct xen_arch_domainconfig { /* IN/OUT */ uint8_t gic_version; @@ -355,6 +359,9 @@ struct xen_arch_domainconfig { uint32_t clock_frequency; /* IN */ uint8_t arm_sci_type; + /* IN */ + uint8_t v8r_el1_msa; + uint16_t pad; }; #endif /* __XEN__ || __XEN_TOOLS__ */ =20 diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h index 8f6708c0a7cd..23124547f347 100644 --- a/xen/include/public/domctl.h +++ b/xen/include/public/domctl.h @@ -30,9 +30,9 @@ * fields) don't require a change of the version. * Stable ops are NOT covered by XEN_DOMCTL_INTERFACE_VERSION! * - * Last version bump: Xen 4.19 + * Last version bump: Xen 4.22 */ -#define XEN_DOMCTL_INTERFACE_VERSION 0x00000017 +#define XEN_DOMCTL_INTERFACE_VERSION 0x00000018 =20 /* * NB. xen_domctl.domain is an IN/OUT parameter for this operation. --=20 2.34.1 From nobody Tue May 5 08:59:09 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; t=1776695001; cv=none; d=zohomail.com; s=zohoarc; b=aEvx4U6gZzljK2kYyXlf8U5I29jHZ/KfZ5HVoTINWi2XdSnoobtPkwuEDsNJx3TiN+ITjS6WX3kav/y8UH2B0yA0PpcI+aiSaMmbze1H558vnIsFUNUdlhx0+yYmBtR2p33x2hZ/urfTtnUaoTt+h7kyY+1Bcm6IUJbzXzLJyWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1776695001; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Qo7KRFw+ygjpEUeCWNqkMxRiw95TPyR/GN1u49nflaw=; b=bm1DRyNavxeAz1Dbyuny7362x3D0URaFFjiZpOmTCcEgVOM381pEco73RspisuVZKkLV1g1+mt8VQnLSD8DIsuG+0MfT5GPLBKJaE7ns6aqdu0dbHxn//KCnuCiN+zWK8fNOvQ+cZbODvYNUV/dllw9Pp8pVcgTkmam47P+vQN0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1776695001531254.99443701017856; Mon, 20 Apr 2026 07:23:21 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1286049.1567186 (Exim 4.92) (envelope-from ) id 1wEpWY-0002nC-Ew; Mon, 20 Apr 2026 14:22:54 +0000 Received: by outflank-mailman (output) from mailman id 1286049.1567186; Mon, 20 Apr 2026 14:22:54 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWY-0002mz-9p; Mon, 20 Apr 2026 14:22:54 +0000 Received: by outflank-mailman (input) for mailman id 1286049; Mon, 20 Apr 2026 14:22:53 +0000 Received: from mx.expurgate.net ([195.190.135.10]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1wEpWX-0002XS-5V for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 14:22:53 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1wEpWW-000Q5n-IQ for xen-devel@lists.xenproject.org; Mon, 20 Apr 2026 16:22:52 +0200 Received: from [10.42.69.4] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 69e636ba-e002-0a2a0a5209dd-0a2a4504b0be-2 for ; Mon, 20 Apr 2026 16:22:52 +0200 Received: from [217.140.110.172] (helo=foss.arm.com) by tlsNG-ebf023.mxtls.expurgate.net with ESMTP (eXpurgate 4.56.1) (envelope-from ) id 69e636bb-1dec-0a2a45040019-d98c6eaccfd2-1 for ; Mon, 20 Apr 2026 16:22:52 +0200 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CDFB31516; Mon, 20 Apr 2026 07:22:45 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 748B73F7B4; Mon, 20 Apr 2026 07:22:50 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776694971; bh=2jwMTZ96/fznHmHt78iGUnOWdXQ8B7ZjteeUmUTDvnA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RNnZtM1TxQlcuIC9URWpVNKgROgJki95Skz6ZfJudAVau0lSSZCsDUBXG3viAE0bz GiPdbBTqkaJJ7FbK0onORaAiUtN8OyBrqA8dLXm46qjknqkEqeYdW3Hz8qVvu0j1/4 /bIBrdlcYro1k2NkiruLZiJA3/hny4T7qG4Rlezo= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v4 3/3] arm/mpu: Implement p2m tables Date: Mon, 20 Apr 2026 15:22:24 +0100 Message-Id: <20260420142224.1802911-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420142224.1802911-1-luca.fancellu@arm.com> References: <20260420142224.1802911-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-ebf023/1776694972-4B96A3FF-F69A46E1/0/0 X-purgate-type: clean X-purgate-size: 5745 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1776695002834158500 Content-Type: text/plain; charset="utf-8" From: Harry Ramsey Implement `p2m_alloc_table`, `p2m_init` and `p2m_final_teardown` for MPU systems. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v4: - no changes v3: - Check for alloc_xenheap_pages allocation - Clear additional page allocated for ARM64 - Add check for INVALID_VCPU_ID - Remove unnecessary function generate_vsctlr - Code formatting fixes --- xen/arch/arm/include/asm/arm32/mpu.h | 2 + xen/arch/arm/include/asm/arm64/mpu.h | 2 + xen/arch/arm/include/asm/mpu/p2m.h | 12 +++++ xen/arch/arm/include/asm/p2m.h | 5 ++ xen/arch/arm/mpu/p2m.c | 78 ++++++++++++++++++++++++++-- 5 files changed, 96 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/as= m/arm32/mpu.h index 2cf0f8cbacae..d565230f84ee 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -11,6 +11,8 @@ */ #define MPU_REGION_RES0 0x0 =20 +#define VSCTLR_VMID_SHIFT 16 + /* Hypervisor Protection Region Base Address Register */ typedef union { struct { diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h index 4f694190a8a3..8b86a03fee44 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -7,6 +7,8 @@ =20 #define MPU_REGION_RES0 (0xFFFFULL << 48) =20 +#define VSCTLR_VMID_SHIFT 48 + /* Protection Region Base Address Register */ typedef union { struct __packed { diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/= mpu/p2m.h index e46d9e757a1d..39fc0c944916 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -3,8 +3,20 @@ #ifndef __ARM_MPU_P2M_H__ #define __ARM_MPU_P2M_H__ =20 +#include +#include +#include + struct p2m_domain; =20 +/* + * The architecture allows at most 255 EL2 MPU memory regions. The size of= the + * MPU structure entry (pr_t) is 32 Bytes on AArch64 (requiring two 4KB pa= ges) + * and 16 bytes on AArch32 (requiring one 4KB page). + */ +#define P2M_ROOT_PAGES DIV_ROUND_UP(255 * sizeof(pr_t), PAGE_SIZE) +#define P2M_ROOT_ORDER get_count_order(P2M_ROOT_PAGES) + static inline void p2m_clear_root_pages(struct p2m_domain *p2m) {} =20 static inline void p2m_tlb_flush_sync(struct p2m_domain *p2m) {} diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..ed1b6dd40f40 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -48,8 +48,13 @@ struct p2m_domain { /* Current VMID in use */ uint16_t vmid; =20 +#ifdef CONFIG_MMU /* Current Translation Table Base Register for the p2m */ uint64_t vttbr; +#else + /* Current Virtualization System Control Register for the p2m */ + register_t vsctlr; +#endif =20 /* Highest guest frame that's ever been mapped in the p2m */ gfn_t max_mapped_gfn; diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index f7fb58ab6aa8..ec8f630acd90 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -28,10 +28,69 @@ void p2m_dump_info(struct domain *d) BUG_ON("unimplemented"); } =20 +static int p2m_alloc_table(struct domain *d) +{ + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + void *table =3D alloc_xenheap_pages(P2M_ROOT_ORDER, 0); + + if ( !table ) + { + printk(XENLOG_G_ERR "%pd: p2m: unable to allocate P2M MPU mapping = table\n", + d); + return -ENOMEM; + } + + p2m->root =3D virt_to_page(table); + + for (int i =3D 0; i < P2M_ROOT_PAGES; i++) + clear_page(page_to_virt(p2m->root + i)); + + return 0; +} + int p2m_init(struct domain *d) { - BUG_ON("unimplemented"); - return -EINVAL; + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + int rc =3D 0; + unsigned int cpu; + + rwlock_init(&p2m->lock); + + p2m->vmid =3D INVALID_VMID; + p2m->max_mapped_gfn =3D _gfn(0); + p2m->lowest_mapped_gfn =3D _gfn(ULONG_MAX); + + p2m->default_access =3D p2m_access_rwx; + /* mem_access is NOT supported in MPU system. */ + p2m->mem_access_enabled =3D false; + + /* Ensure that the type chosen is large enough for MAX_VIRT_CPUS. */ + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < MAX_VIRT_CPU= S); + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < INVALID_VCPU= _ID); + + for_each_possible_cpu(cpu) + p2m->last_vcpu_ran[cpu] =3D INVALID_VCPU_ID; + + /* + * "Trivial" initialization is now complete. Set the backpointer so th= at + * p2m_teardown() and related functions know to do something. + */ + p2m->domain =3D d; + + rc =3D p2m_alloc_vmid(d); + if ( rc ) + return rc; + + p2m->vsctlr =3D ((register_t)p2m->vmid << VSCTLR_VMID_SHIFT); + + rc =3D p2m_alloc_table(d); + if ( rc ) + { + p2m_free_vmid(d); + return rc; + } + + return 0; } =20 void p2m_save_state(struct vcpu *p) @@ -46,7 +105,20 @@ void p2m_restore_state(struct vcpu *n) =20 void p2m_final_teardown(struct domain *d) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + + /* p2m not actually initialized */ + if ( !p2m->domain ) + return; + + if ( p2m->root ) + free_xenheap_pages(page_to_virt(p2m->root), P2M_ROOT_ORDER); + + p2m->root =3D NULL; + + p2m_free_vmid(d); + + p2m->domain =3D NULL; } =20 bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) --=20 2.34.1