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Wed, 8 Apr 2026 06:55:40 -0700 (PDT) Received: from e125770.cambridge.arm.com (e125770.arm.com [10.1.199.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EAF2A3F641; Wed, 8 Apr 2026 06:55:44 -0700 (PDT) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775656546; bh=Jbkn6tr6DeeBrY5TgQXpfTzOB7k0l9K2i9UHo4esCJQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=janao23xhFbReleouDkYkbSn4pi/0x26slL4ykiuIE20zLLYWoXQ9WNlLe9Wl4VnT QTPD+N6S0V2vPzkNsVUz4KIhrWX3d+mEXH8btNJcyTyXaUpbxRE/PZnYZgy9lMmB/b dJhw9QR0DpXo+8LOzV82SpdNN+vT0NU49Oj04lQQ= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Penny Zheng , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk , Penny Zheng , Wei Chen , Hari Limaye , Harry Ramsey Subject: [PATCH v3 1/3] arm/mpu: implement setup_virt_paging for MPU system Date: Wed, 8 Apr 2026 14:55:29 +0100 Message-Id: <20260408135531.1744388-2-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260408135531.1744388-1-luca.fancellu@arm.com> References: <20260408135531.1744388-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1775656547-3133496F-1045722C/0/0 X-purgate-type: clean X-purgate-size: 7460 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1775656574157158500 Content-Type: text/plain; charset="utf-8" From: Penny Zheng Implement setup_virt_paging for aarch64 MPU systems, taking tare of stage 2 address translation regime, IPA bits, supported VMID length configuration and vtcr_el2/vstcr_el2 register programming. Implement also the Armv8-R specific changes to ID_AA64MMFR0_EL1, related to the supported memory system architecture (PMSA/VMSA) and check that when MPU is built, the underlying HW is compatible with PMSA. By default MPU at EL2 and EL1 is required. Signed-off-by: Penny Zheng Signed-off-by: Wei Chen Signed-off-by: Luca Fancellu Signed-off-by: Hari Limaye Signed-off-by: Harry Ramsey --- v3: - Refactor unused code to more relevant commits. - Add P2M print information - Formatting issues - Update commit message v2: - Seperate commit into multiple commits --- xen/arch/arm/arm64/mpu/p2m.c | 80 +++++++++++++++++++++++- xen/arch/arm/include/asm/arm64/sysregs.h | 4 ++ xen/arch/arm/include/asm/cpufeature.h | 13 +++- xen/arch/arm/include/asm/processor.h | 8 +++ 4 files changed, 101 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/arm64/mpu/p2m.c b/xen/arch/arm/arm64/mpu/p2m.c index b6d8b2777b58..fda512dc7c8f 100644 --- a/xen/arch/arm/arm64/mpu/p2m.c +++ b/xen/arch/arm/arm64/mpu/p2m.c @@ -2,11 +2,89 @@ =20 #include #include +#include #include =20 void __init setup_virt_paging(void) { - BUG_ON("unimplemented"); + register_t vtcr_el2 =3D READ_SYSREG(VTCR_EL2); + register_t vstcr_el2 =3D READ_SYSREG(VSTCR_EL2); + + /* PA size */ + const unsigned int pa_range_info[] =3D {32, 36, 40, 42, 44, 48, 52, 0, + /* Invalid */}; + + /* + * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured + * with IPA bits =3D=3D PA bits, compare against "pabits". + */ + if ( pa_range_info[system_cpuinfo.mm64.pa_range] < p2m_ipa_bits ) + p2m_ipa_bits =3D pa_range_info[system_cpuinfo.mm64.pa_range]; + + /* + * The MSA and MSA_frac fields in the ID_AA64MMFR0_EL1 register identi= fy the + * memory system configurations supported. In Armv8-R AArch64, the + * only permitted value for ID_AA64MMFR0_EL1.MSA is 0b1111. + */ + if ( system_cpuinfo.mm64.msa !=3D MM64_MSA_PMSA_SUPPORT ) + goto fault; + + /* Permitted values for ID_AA64MMFR0_EL1.MSA_frac are 0b0001 and 0b001= 0. */ + if ( (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_PMSA_SUPPORT) && + (system_cpuinfo.mm64.msa_frac !=3D MM64_MSA_FRAC_VMSA_SUPPORT) ) + goto fault; + + /* Stage 1 EL1&0 translation regime uses PMSAv8 by default */ + vtcr_el2 &=3D ~VTCR_MSA; + + /* + * Clear VTCR_EL2.NSA bit to configure non-secure stage 2 translation = output + * address space to access the Secure PA space as Armv8r only implemen= ts + * secure state. + */ + vtcr_el2 &=3D ~VTCR_NSA; + + /* + * cpuinfo sanitization makes sure we support 16bits VMID only if all = cores + * are supporting it. + * + * Set the VS bit only if 16 bit VIMD is supported. + */ + if ( system_cpuinfo.mm64.vmid_bits =3D=3D MM64_VMID_16_BITS_SUPPORT ) + { + vtcr_el2 |=3D VTCR_VS; + max_vmid =3D MAX_VMID_16_BIT; + } + else + vtcr_el2 &=3D ~VTCR_VS; + + p2m_vmid_allocator_init(); + + WRITE_SYSREG(vtcr_el2, VTCR_EL2); + + /* + * VSTCR_EL2.SA defines secure stage 2 translation output address spac= e. + * To make sure that all stage 2 translations for the Secure PA space = access + * the Secure PA space, we keep SA bit as 0. + * + * VSTCR_EL2.SC is NS check enable bit. To make sure that Stage 2 NS + * configuration is checked against stage 1 NS configuration in EL1&0 + * translation regime for the given address, and generates a fault if = they + * are different, we set SC bit 1. + */ + vstcr_el2 &=3D ~VSTCR_EL2_SA; + vstcr_el2 |=3D VSTCR_EL2_SC; + WRITE_SYSREG(vstcr_el2, VSTCR_EL2); + + printk("P2M: %d-bit IPA with %d-bit PA and %d-bit VMID\n", + p2m_ipa_bits, + pa_range_info[system_cpuinfo.mm64.pa_range], + ( MAX_VMID =3D=3D MAX_VMID_16_BIT ) ? 16 : 8); + + return; + + fault: + panic("Hardware with no PMSAv8-64 support in any translation regime\n"= ); } =20 /* diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/includ= e/asm/arm64/sysregs.h index 19d409d3eb5a..f3c11d871e86 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,10 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff =20 +/* Virtualization Secure Translation Control Register */ +#define VSTCR_EL2_SA (_AC(0x1,U) << 30) +#define VSTCR_EL2_SC (_AC(0x1,U) << 20) + #ifdef CONFIG_MPU /* * The Armv8-R AArch64 architecture always executes code in Secure diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/a= sm/cpufeature.h index 13353c8e1ad1..bf902a397068 100644 --- a/xen/arch/arm/include/asm/cpufeature.h +++ b/xen/arch/arm/include/asm/cpufeature.h @@ -248,6 +248,12 @@ struct cpuinfo_arm { unsigned long tgranule_16K:4; unsigned long tgranule_64K:4; unsigned long tgranule_4K:4; +#ifdef CONFIG_MPU + unsigned long __res0:16; + unsigned long msa:4; + unsigned long msa_frac:4; + unsigned long __res1:8; +#else unsigned long tgranule_16k_2:4; unsigned long tgranule_64k_2:4; unsigned long tgranule_4k_2:4; @@ -255,6 +261,7 @@ struct cpuinfo_arm { unsigned long __res0:8; unsigned long fgt:4; unsigned long ecv:4; +#endif =20 /* MMFR1 */ unsigned long hafdbs:4; @@ -267,13 +274,13 @@ struct cpuinfo_arm { unsigned long xnx:4; unsigned long twed:4; unsigned long ets:4; - unsigned long __res1:4; + unsigned long __res2:4; unsigned long afp:4; - unsigned long __res2:12; + unsigned long __res3:12; unsigned long ecbhb:4; =20 /* MMFR2 */ - unsigned long __res3:64; + unsigned long __res4:64; }; } mm64; =20 diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/as= m/processor.h index 1a48c9ff3b39..895d7cd50244 100644 --- a/xen/arch/arm/include/asm/processor.h +++ b/xen/arch/arm/include/asm/processor.h @@ -403,6 +403,9 @@ =20 #define VTCR_RES1 (_AC(1,UL)<<31) =20 +#define VTCR_MSA (_AC(0x1,UL)<<31) +#define VTCR_NSA (_AC(0x1,UL)<<30) + /* HCPTR Hyp. Coprocessor Trap Register */ #define HCPTR_TAM ((_AC(1,U)<<30)) #define HCPTR_TTA ((_AC(1,U)<<20)) /* Trap trace registers */ @@ -464,6 +467,11 @@ #define MM64_VMID_16_BITS_SUPPORT 0x2 #endif =20 +#define MM64_MSA_PMSA_SUPPORT 0xf +#define MM64_MSA_FRAC_NONE_SUPPORT 0x0 +#define MM64_MSA_FRAC_PMSA_SUPPORT 0x1 +#define MM64_MSA_FRAC_VMSA_SUPPORT 0x2 + #ifndef __ASSEMBLER__ =20 extern register_t __cpu_logical_map[]; --=20 2.34.1 From nobody Sun Apr 12 22:39:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=arm.com ARC-Seal: i=1; a=rsa-sha256; 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a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775656548; bh=v5LF9EBgnpQL3pb+wunpmzDERz+oj+KrD99jf6QSUyw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KlPwKuHMTA3nm6OSjAxLvuR9Qvyu1Bs4h2BMjvm8xbW1beM0vu/VITGIND60fgeBW Njl8aP1nGuhPfHde+wdmASMyeVPa9v8wipSdgR03K1GwRVbGtI3wyc3xCZEXSW8fql Oolf4ht585ZHaQ5pcKahZyOpaA7fnLGXe+fzUsGM= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v3 2/3] arm/mpu: Introduce `v8r_el1_msa` device tree property for domains Date: Wed, 8 Apr 2026 14:55:30 +0100 Message-Id: <20260408135531.1744388-3-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260408135531.1744388-1-luca.fancellu@arm.com> References: <20260408135531.1744388-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-c201ff/1775656549-38BE896F-DE5C9B4A/0/0 X-purgate-type: clean X-purgate-size: 6467 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1775656572502158500 Content-Type: text/plain; charset="utf-8" From: Harry Ramsey Add a new device tree property `v8r_el1_msa` to select the MSA (memory system architecture) at EL1 i.e. MPU(default) or MMU. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v3: - Improve commit message and device tree property description - Remove macro protection - Remove unused function is_mpu_domain - Code formatting --- docs/misc/arm/device-tree/booting.txt | 12 ++++++++++++ xen/arch/arm/dom0less-build.c | 24 ++++++++++++++++++++++++ xen/arch/arm/domain.c | 4 ++++ xen/arch/arm/include/asm/domain.h | 7 +++++++ xen/arch/arm/include/asm/mpu.h | 5 +++++ xen/arch/arm/mpu/arm32/mm.c | 5 +++++ xen/arch/arm/mpu/arm64/mm.c | 5 +++++ xen/include/public/arch-arm.h | 2 ++ 8 files changed, 64 insertions(+) diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-t= ree/booting.txt index 977b4286082f..b1a329c0e8d9 100644 --- a/docs/misc/arm/device-tree/booting.txt +++ b/docs/misc/arm/device-tree/booting.txt @@ -322,6 +322,18 @@ with the following properties: Should be used together with scmi-smc-passthrough Xen command line option. =20 +- v8r_el1_msa + + A string property specifying whether, on Armv8-R systems, a domain + should use PMSAv8 (MPU) at EL1 or VMSAv8 (MMU) at EL1. + + - "mmu" + Enables VMSAv8 at EL1. This requires hardware support and is only + optionally available on AArch64. + + - "mpu" + Enables PMSAv8 at EL1. (Default) + Under the "xen,domain" compatible node, one or more sub-nodes are present for the DomU kernel and ramdisk. =20 diff --git a/xen/arch/arm/dom0less-build.c b/xen/arch/arm/dom0less-build.c index 4181c105389a..456dc553bb23 100644 --- a/xen/arch/arm/dom0less-build.c +++ b/xen/arch/arm/dom0less-build.c @@ -24,6 +24,7 @@ #include #include #include +#include #include =20 #ifdef CONFIG_VGICV2 @@ -315,6 +316,7 @@ int __init arch_parse_dom0less_node(struct dt_device_no= de *node, struct xen_domctl_createdomain *d_cfg =3D &bd->create_cfg; unsigned int flags =3D bd->create_flags; uint32_t val; + const char *v8r_el1_msa; =20 d_cfg->arch.gic_version =3D XEN_DOMCTL_CONFIG_GIC_NATIVE; d_cfg->flags |=3D XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap; @@ -322,6 +324,28 @@ int __init arch_parse_dom0less_node(struct dt_device_n= ode *node, if ( domu_dt_sci_parse(node, d_cfg) ) panic("Error getting SCI configuration\n"); =20 + if (!dt_property_read_string(node, "v8r_el1_msa", &v8r_el1_msa)) + { +#ifdef CONFIG_MPU + if ( !strcmp(v8r_el1_msa, "mmu") ) + { + if ( !has_v8r_vmsa_support() ) + panic("Platform does not support VMSA at EL1 (v8r_el1_msa)= \n"); + d_cfg->arch.v8r_el1_msa =3D MPU_EL1_VMSA; + } + else if ( !strcmp(v8r_el1_msa, "mpu") ) + { + d_cfg->arch.v8r_el1_msa =3D MPU_EL1_PMSA; + if ( !(flags & CDF_staticmem) || !(flags & CDF_directmap) ) + panic("PMSA is not valid for domain without static allocat= ion and direct map (v8r_el1_msa)\n"); + } + else + panic("Invalid device tree option for v8r_el1_msa\n"); +#else + panic("'v8r_el1_msa' property found, but CONFIG_MPU not selected\n= "); +#endif + } + if ( !dt_property_read_u32(node, "nr_spis", &d_cfg->arch.nr_spis) ) { int vpl011_virq =3D GUEST_VPL011_SPI; diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 26380a807cad..c044293acd39 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -725,6 +725,10 @@ int arch_domain_create(struct domain *d, if ( (rc =3D sci_domain_init(d, config)) !=3D 0 ) goto fail; =20 +#ifdef CONFIG_MPU + d->arch.v8r_el1_msa =3D config->arch.v8r_el1_msa; +#endif + return 0; =20 fail: diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index ffe5d0d9f0a6..fd0a83046893 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -30,6 +30,9 @@ enum domain_type { #define is_64bit_domain(d) (0) #endif =20 +#define MPU_EL1_PMSA 0 +#define MPU_EL1_VMSA 1 + /* * Is the domain using the host memory layout? * @@ -128,6 +131,10 @@ struct arch_domain #endif =20 struct resume_info resume_ctx; + +#ifdef CONFIG_MPU + uint8_t v8r_el1_msa; +#endif } __cacheline_aligned; =20 struct arch_vcpu diff --git a/xen/arch/arm/include/asm/mpu.h b/xen/arch/arm/include/asm/mpu.h index 72fa5b00b861..8a8c01086206 100644 --- a/xen/arch/arm/include/asm/mpu.h +++ b/xen/arch/arm/include/asm/mpu.h @@ -27,6 +27,11 @@ =20 #ifndef __ASSEMBLER__ =20 +/* + * Utility function to determine if an Armv8-R processor supports VMSA. + */ +bool has_v8r_vmsa_support(void); + /* * Set base address of MPU protection region. * diff --git a/xen/arch/arm/mpu/arm32/mm.c b/xen/arch/arm/mpu/arm32/mm.c index a4673c351141..5eaeb3400e6c 100644 --- a/xen/arch/arm/mpu/arm32/mm.c +++ b/xen/arch/arm/mpu/arm32/mm.c @@ -38,6 +38,11 @@ break; \ } =20 +bool has_v8r_vmsa_support(void) +{ + return false; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: diff --git a/xen/arch/arm/mpu/arm64/mm.c b/xen/arch/arm/mpu/arm64/mm.c index ed643cad4073..b07e729a7d05 100644 --- a/xen/arch/arm/mpu/arm64/mm.c +++ b/xen/arch/arm/mpu/arm64/mm.c @@ -32,6 +32,11 @@ break; \ } =20 +bool has_v8r_vmsa_support(void) +{ + return system_cpuinfo.mm64.msa_frac =3D=3D MM64_MSA_FRAC_VMSA_SUPPORT; +} + /* * Armv8-R supports direct access and indirect access to the MPU regions t= hrough * registers: diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index cd563cf70684..23df2f24cb09 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -355,6 +355,8 @@ struct xen_arch_domainconfig { uint32_t clock_frequency; /* IN */ uint8_t arm_sci_type; + /* IN */ + uint8_t v8r_el1_msa; }; #endif /* __XEN__ || __XEN_TOOLS__ */ =20 --=20 2.34.1 From nobody Sun Apr 12 22:39:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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dkim=pass header.s=foss header.d=arm.com header.i="@arm.com" header.h="From:To:Cc:Subject:Date:In-Reply-To:References" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775656549; bh=MZfKdfd+Fjj1nByHopUcpOrzmuP31AXPE7A1SX/KVCM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kece+ckOVuHEDt+c/9tCpgkrxKngvpG1tEBgmcyidiwZ3p1OHEQHQUAHP7pPUU3A2 gxKcYy1aY2+wxvShLu/vmmgvoENvxwEt87duuVzn1GeC6DZWaByS+0awZahbr9/+V4 50lnYBTq18dbPms5Uro++lahgvoc/jiRQBeU3zHM= From: Luca Fancellu To: xen-devel@lists.xenproject.org Cc: Harry Ramsey , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , Volodymyr Babchuk Subject: [PATCH v3 3/3] arm/mpu: Implement p2m tables Date: Wed, 8 Apr 2026 14:55:31 +0100 Message-Id: <20260408135531.1744388-4-luca.fancellu@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260408135531.1744388-1-luca.fancellu@arm.com> References: <20260408135531.1744388-1-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-purgate-ID: tlsNG-720697/1775656550-ACB37CD1-35573629/0/0 X-purgate-type: clean X-purgate-size: 5725 X-ZohoMail-DKIM: pass (identity @arm.com) X-ZM-MESSAGEID: 1775656588251158500 Content-Type: text/plain; charset="utf-8" From: Harry Ramsey Implement `p2m_alloc_table`, `p2m_init` and `p2m_final_teardown` for MPU systems. Signed-off-by: Harry Ramsey Signed-off-by: Luca Fancellu --- v3: - Check for alloc_xenheap_pages allocation - Clear additional page allocated for ARM64 - Add check for INVALID_VCPU_ID - Remove unnecessary function generate_vsctlr - Code formatting fixes --- xen/arch/arm/include/asm/arm32/mpu.h | 2 + xen/arch/arm/include/asm/arm64/mpu.h | 2 + xen/arch/arm/include/asm/mpu/p2m.h | 12 +++++ xen/arch/arm/include/asm/p2m.h | 5 ++ xen/arch/arm/mpu/p2m.c | 78 ++++++++++++++++++++++++++-- 5 files changed, 96 insertions(+), 3 deletions(-) diff --git a/xen/arch/arm/include/asm/arm32/mpu.h b/xen/arch/arm/include/as= m/arm32/mpu.h index 2cf0f8cbacae..d565230f84ee 100644 --- a/xen/arch/arm/include/asm/arm32/mpu.h +++ b/xen/arch/arm/include/asm/arm32/mpu.h @@ -11,6 +11,8 @@ */ #define MPU_REGION_RES0 0x0 =20 +#define VSCTLR_VMID_SHIFT 16 + /* Hypervisor Protection Region Base Address Register */ typedef union { struct { diff --git a/xen/arch/arm/include/asm/arm64/mpu.h b/xen/arch/arm/include/as= m/arm64/mpu.h index 4f694190a8a3..8b86a03fee44 100644 --- a/xen/arch/arm/include/asm/arm64/mpu.h +++ b/xen/arch/arm/include/asm/arm64/mpu.h @@ -7,6 +7,8 @@ =20 #define MPU_REGION_RES0 (0xFFFFULL << 48) =20 +#define VSCTLR_VMID_SHIFT 48 + /* Protection Region Base Address Register */ typedef union { struct __packed { diff --git a/xen/arch/arm/include/asm/mpu/p2m.h b/xen/arch/arm/include/asm/= mpu/p2m.h index e46d9e757a1d..39fc0c944916 100644 --- a/xen/arch/arm/include/asm/mpu/p2m.h +++ b/xen/arch/arm/include/asm/mpu/p2m.h @@ -3,8 +3,20 @@ #ifndef __ARM_MPU_P2M_H__ #define __ARM_MPU_P2M_H__ =20 +#include +#include +#include + struct p2m_domain; =20 +/* + * The architecture allows at most 255 EL2 MPU memory regions. The size of= the + * MPU structure entry (pr_t) is 32 Bytes on AArch64 (requiring two 4KB pa= ges) + * and 16 bytes on AArch32 (requiring one 4KB page). + */ +#define P2M_ROOT_PAGES DIV_ROUND_UP(255 * sizeof(pr_t), PAGE_SIZE) +#define P2M_ROOT_ORDER get_count_order(P2M_ROOT_PAGES) + static inline void p2m_clear_root_pages(struct p2m_domain *p2m) {} =20 static inline void p2m_tlb_flush_sync(struct p2m_domain *p2m) {} diff --git a/xen/arch/arm/include/asm/p2m.h b/xen/arch/arm/include/asm/p2m.h index 010ce8c9ebbd..ed1b6dd40f40 100644 --- a/xen/arch/arm/include/asm/p2m.h +++ b/xen/arch/arm/include/asm/p2m.h @@ -48,8 +48,13 @@ struct p2m_domain { /* Current VMID in use */ uint16_t vmid; =20 +#ifdef CONFIG_MMU /* Current Translation Table Base Register for the p2m */ uint64_t vttbr; +#else + /* Current Virtualization System Control Register for the p2m */ + register_t vsctlr; +#endif =20 /* Highest guest frame that's ever been mapped in the p2m */ gfn_t max_mapped_gfn; diff --git a/xen/arch/arm/mpu/p2m.c b/xen/arch/arm/mpu/p2m.c index f7fb58ab6aa8..ec8f630acd90 100644 --- a/xen/arch/arm/mpu/p2m.c +++ b/xen/arch/arm/mpu/p2m.c @@ -28,10 +28,69 @@ void p2m_dump_info(struct domain *d) BUG_ON("unimplemented"); } =20 +static int p2m_alloc_table(struct domain *d) +{ + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + void *table =3D alloc_xenheap_pages(P2M_ROOT_ORDER, 0); + + if ( !table ) + { + printk(XENLOG_G_ERR "%pd: p2m: unable to allocate P2M MPU mapping = table\n", + d); + return -ENOMEM; + } + + p2m->root =3D virt_to_page(table); + + for (int i =3D 0; i < P2M_ROOT_PAGES; i++) + clear_page(page_to_virt(p2m->root + i)); + + return 0; +} + int p2m_init(struct domain *d) { - BUG_ON("unimplemented"); - return -EINVAL; + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + int rc =3D 0; + unsigned int cpu; + + rwlock_init(&p2m->lock); + + p2m->vmid =3D INVALID_VMID; + p2m->max_mapped_gfn =3D _gfn(0); + p2m->lowest_mapped_gfn =3D _gfn(ULONG_MAX); + + p2m->default_access =3D p2m_access_rwx; + /* mem_access is NOT supported in MPU system. */ + p2m->mem_access_enabled =3D false; + + /* Ensure that the type chosen is large enough for MAX_VIRT_CPUS. */ + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < MAX_VIRT_CPU= S); + BUILD_BUG_ON((1 << (sizeof(p2m->last_vcpu_ran[0]) * 8)) < INVALID_VCPU= _ID); + + for_each_possible_cpu(cpu) + p2m->last_vcpu_ran[cpu] =3D INVALID_VCPU_ID; + + /* + * "Trivial" initialization is now complete. Set the backpointer so th= at + * p2m_teardown() and related functions know to do something. + */ + p2m->domain =3D d; + + rc =3D p2m_alloc_vmid(d); + if ( rc ) + return rc; + + p2m->vsctlr =3D ((register_t)p2m->vmid << VSCTLR_VMID_SHIFT); + + rc =3D p2m_alloc_table(d); + if ( rc ) + { + p2m_free_vmid(d); + return rc; + } + + return 0; } =20 void p2m_save_state(struct vcpu *p) @@ -46,7 +105,20 @@ void p2m_restore_state(struct vcpu *n) =20 void p2m_final_teardown(struct domain *d) { - BUG_ON("unimplemented"); + struct p2m_domain *p2m =3D p2m_get_hostp2m(d); + + /* p2m not actually initialized */ + if ( !p2m->domain ) + return; + + if ( p2m->root ) + free_xenheap_pages(page_to_virt(p2m->root), P2M_ROOT_ORDER); + + p2m->root =3D NULL; + + p2m_free_vmid(d); + + p2m->domain =3D NULL; } =20 bool p2m_resolve_translation_fault(struct domain *d, gfn_t gfn) --=20 2.34.1