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From: Ross Lagerwall To: xen-devel@lists.xenproject.org Cc: Andrew Cooper , Anthony PERARD , Michal Orzel , Jan Beulich , Julien Grall , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Stefano Stabellini , Ross Lagerwall Subject: [PATCH v1 1/8] x86: Always use eager-fpu Date: Thu, 19 Mar 2026 13:29:17 +0000 Message-ID: <20260319132924.1469809-2-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260319132924.1469809-1-ross.lagerwall@citrix.com> References: <20260319132924.1469809-1-ross.lagerwall@citrix.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P265CA0059.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:2af::15) To DS0PR03MB8272.namprd03.prod.outlook.com (2603:10b6:8:28f::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR03MB8272:EE_|CH5PR03MB7816:EE_ X-MS-Office365-Filtering-Correlation-Id: 10c201f1-63c7-4458-1262-08de85bb8d6a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|22082099003|56012099003|18002099003; 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charset="utf-8" Lazy FPU avoids some work during a context switch but pushes the costs elsewhere: * For a workload running some Windows VMs, I measured about 83% of context switches out had used the FPU so most of the time the FPU save/restore is not avoided, just delayed. * Setting/clearing the cr0.TS bit is serializing and reportedly slower than the processor optimized xsave/restore. * Linux uses PKRU so a partial xsave/restore is performed on each context switch anyway, followed by a second xsave/restore at some point during execution. There is no measurable performance benefit for using lazy FPU and it adds unwanted complexity so remove the option and always use eager-fpu. Signed-off-by: Ross Lagerwall --- docs/misc/hypfs-paths.pandoc | 2 - docs/misc/xen-command-line.pandoc | 7 +-- xen/arch/x86/i387.c | 2 +- xen/arch/x86/include/asm/spec_ctrl.h | 1 - xen/arch/x86/spec_ctrl.c | 88 ++-------------------------- 5 files changed, 6 insertions(+), 94 deletions(-) diff --git a/docs/misc/hypfs-paths.pandoc b/docs/misc/hypfs-paths.pandoc index e86f7d0dbef9..1553cb0bcb7f 100644 --- a/docs/misc/hypfs-paths.pandoc +++ b/docs/misc/hypfs-paths.pandoc @@ -108,12 +108,10 @@ A populated Xen hypervisor file system might look lik= e the following example: active-hvm/ directory for mitigations active in hvm doami= ns msr-spec-ctrl "No" or "Yes" rsb "No" or "Yes" - eager-fpu "No" or "Yes" md-clear "No" or "Yes" active-pv/ directory for mitigations active in pv doamins msr-spec-ctrl "No" or "Yes" rsb "No" or "Yes" - eager-fpu "No" or "Yes" md-clear "No" or "Yes" xpti "No" or list of "dom0", "domU", "PCID-on" l1tf-shadow "No" or list of "dom0", "domU" diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line= .pandoc index ebdca007d26b..6c77129732bf 100644 --- a/docs/misc/xen-command-line.pandoc +++ b/docs/misc/xen-command-line.pandoc @@ -2470,7 +2470,7 @@ By default SSBD will be mitigated at runtime (i.e `ss= bd=3Druntime`). > {msr-sc,rsb,verw,{ibpb,bhb}-entry}=3D|{pv,hvm}=3D, > bti-thunk=3Dretpoline|lfence|jmp,bhb-seq=3Dshort|tsx|long, > {ibrs,ibpb,ssbd,psfd, -> eager-fpu,l1d-flush,branch-harden,srb-lock, +> l1d-flush,branch-harden,srb-lock, > unpriv-mmio,gds-mit,div-scrub,lock-harden, > bhi-dis-s,bp-spec-reduce,ibpb-alt}=3D ]` =20 @@ -2574,11 +2574,6 @@ On hardware supporting IBPB (Indirect Branch Predict= ion Barrier), the `ibpb=3D` option can be used to force (the default) or prevent Xen from issuing bran= ch prediction barriers on vcpu context switches. =20 -On all hardware, the `eager-fpu=3D` option can be used to force or prevent= Xen -from using fully eager FPU context switches. This is currently implemente= d as -a global control. By default, Xen will choose to use fully eager context -switches on hardware believed to speculate past #NM exceptions. - On hardware supporting L1D_FLUSH, the `l1d-flush=3D` option can be used to= force or prevent Xen from issuing an L1 data cache flush on each VMEntry. Irrespective of Xen's setting, the feature is virtualised for HVM guests to diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index b84cd6f7a9e1..954ba3b1799b 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -297,7 +297,7 @@ void save_fpu_enable(void) /* Initialize FPU's context save area */ int vcpu_init_fpu(struct vcpu *v) { - v->arch.fully_eager_fpu =3D opt_eager_fpu; + v->arch.fully_eager_fpu =3D true; =20 return xstate_alloc_save_area(v); } diff --git a/xen/arch/x86/include/asm/spec_ctrl.h b/xen/arch/x86/include/as= m/spec_ctrl.h index 505e3ab863f0..8f82533c416a 100644 --- a/xen/arch/x86/include/asm/spec_ctrl.h +++ b/xen/arch/x86/include/asm/spec_ctrl.h @@ -79,7 +79,6 @@ static always_inline void spec_ctrl_new_guest_context(voi= d) extern int8_t opt_ibpb_ctxt_switch; extern bool opt_ssbd; extern int8_t opt_bhi_dis_s; -extern int8_t opt_eager_fpu; extern int8_t opt_l1d_flush; =20 extern bool bsp_delay_spec_ctrl; diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index dd0413e1fc13..bc8538a56f0e 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -61,7 +61,6 @@ static int8_t __initdata opt_psfd =3D -1; int8_t __ro_after_init opt_bhi_dis_s =3D -1; =20 int8_t __ro_after_init opt_ibpb_ctxt_switch =3D -1; -int8_t __ro_after_init opt_eager_fpu =3D -1; int8_t __ro_after_init opt_l1d_flush =3D -1; static bool __initdata opt_branch_harden =3D IS_ENABLED(CONFIG_SPECULATIVE_HARDEN_BRANCH); @@ -104,8 +103,6 @@ static int __init cf_check parse_spec_ctrl(const char *= s) opt_msr_sc_pv =3D false; opt_msr_sc_hvm =3D false; =20 - opt_eager_fpu =3D 0; - if ( opt_xpti_hwdom < 0 ) opt_xpti_hwdom =3D 0; if ( opt_xpti_domu < 0 ) @@ -336,8 +333,6 @@ static int __init cf_check parse_spec_ctrl(const char *= s) /* Misc settings. */ else if ( (val =3D parse_boolean("ibpb", s, ss)) >=3D 0 ) opt_ibpb_ctxt_switch =3D val; - else if ( (val =3D parse_boolean("eager-fpu", s, ss)) >=3D 0 ) - opt_eager_fpu =3D val; else if ( (val =3D parse_boolean("l1d-flush", s, ss)) >=3D 0 ) opt_l1d_flush =3D val; else if ( (val =3D parse_boolean("branch-harden", s, ss)) >=3D 0 ) @@ -648,32 +643,30 @@ static void __init print_details(enum ind_thunk thunk) * mitigation support for guests. */ #ifdef CONFIG_HVM - printk(" Support for HVM VMs:%s%s%s%s%s%s%s%s\n", + printk(" Support for HVM VMs:%s%s%s%s%s%s%s\n", (boot_cpu_has(X86_FEATURE_SC_MSR_HVM) || boot_cpu_has(X86_FEATURE_SC_RSB_HVM) || boot_cpu_has(X86_FEATURE_IBPB_ENTRY_HVM) || opt_bhb_entry_hvm || amd_virt_spec_ctrl || - opt_eager_fpu || opt_verw_hvm) ? "" : = " None", + opt_verw_hvm) ? "" : = " None", boot_cpu_has(X86_FEATURE_SC_MSR_HVM) ? " MSR_SPEC_CTRL" : = "", (boot_cpu_has(X86_FEATURE_SC_MSR_HVM) || amd_virt_spec_ctrl) ? " MSR_VIRT_SPEC_CTR= L" : "", boot_cpu_has(X86_FEATURE_SC_RSB_HVM) ? " RSB" : = "", - opt_eager_fpu ? " EAGER_FPU" : = "", opt_verw_hvm ? " VERW" : = "", boot_cpu_has(X86_FEATURE_IBPB_ENTRY_HVM) ? " IBPB-entry" : = "", opt_bhb_entry_hvm ? " BHB-entry" : = ""); =20 #endif #ifdef CONFIG_PV - printk(" Support for PV VMs:%s%s%s%s%s%s%s\n", + printk(" Support for PV VMs:%s%s%s%s%s%s\n", (boot_cpu_has(X86_FEATURE_SC_MSR_PV) || boot_cpu_has(X86_FEATURE_SC_RSB_PV) || boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV) || opt_bhb_entry_pv || - opt_eager_fpu || opt_verw_pv) ? "" : = " None", + opt_verw_pv) ? "" : = " None", boot_cpu_has(X86_FEATURE_SC_MSR_PV) ? " MSR_SPEC_CTRL" : = "", boot_cpu_has(X86_FEATURE_SC_RSB_PV) ? " RSB" : = "", - opt_eager_fpu ? " EAGER_FPU" : = "", opt_verw_pv ? " VERW" : = "", boot_cpu_has(X86_FEATURE_IBPB_ENTRY_PV) ? " IBPB-entry" : = "", opt_bhb_entry_pv ? " BHB-entry" : = ""); @@ -959,75 +952,6 @@ static bool __init rsb_is_full_width(void) return true; } =20 -/* Calculate whether this CPU speculates past #NM */ -static bool __init should_use_eager_fpu(void) -{ - /* - * Assume all unrecognised processors are ok. This is only known to - * affect Intel Family 6 processors. - */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) - return false; - - switch ( boot_cpu_data.model ) - { - /* - * Core processors since at least Nehalem are vulnerable. - */ - case 0x1e: /* Nehalem */ - case 0x1f: /* Auburndale / Havendale */ - case 0x1a: /* Nehalem EP */ - case 0x2e: /* Nehalem EX */ - case 0x25: /* Westmere */ - case 0x2c: /* Westmere EP */ - case 0x2f: /* Westmere EX */ - case 0x2a: /* SandyBridge */ - case 0x2d: /* SandyBridge EP/EX */ - case 0x3a: /* IvyBridge */ - case 0x3e: /* IvyBridge EP/EX */ - case 0x3c: /* Haswell */ - case 0x3f: /* Haswell EX/EP */ - case 0x45: /* Haswell D */ - case 0x46: /* Haswell H */ - case 0x3d: /* Broadwell */ - case 0x47: /* Broadwell H */ - case 0x4f: /* Broadwell EP/EX */ - case 0x56: /* Broadwell D */ - case 0x4e: /* Skylake M */ - case 0x55: /* Skylake X */ - case 0x5e: /* Skylake D */ - case 0x66: /* Cannonlake */ - case 0x67: /* Cannonlake? */ - case 0x8e: /* Kabylake M */ - case 0x9e: /* Kabylake D */ - return true; - - /* - * Atom processors are not vulnerable. - */ - case 0x1c: /* Pineview */ - case 0x26: /* Lincroft */ - case 0x27: /* Penwell */ - case 0x35: /* Cloverview */ - case 0x36: /* Cedarview */ - case 0x37: /* Baytrail / Valleyview (Silvermont) */ - case 0x4d: /* Avaton / Rangely (Silvermont) */ - case 0x4c: /* Cherrytrail / Brasswell */ - case 0x4a: /* Merrifield */ - case 0x5a: /* Moorefield */ - case 0x5c: /* Goldmont */ - case 0x5f: /* Denverton */ - case 0x7a: /* Gemini Lake */ - return false; - - default: - printk("Unrecognised CPU model %#x - assuming vulnerable to LazyFP= U\n", - boot_cpu_data.model); - return true; - } -} - /* * https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculati= ve-return-stack-overflow-whitepaper.pdf */ @@ -2221,10 +2145,6 @@ void __init init_speculation_mitigations(void) =20 div_calculations(hw_smt_enabled); =20 - /* Check whether Eager FPU should be enabled by default. */ - if ( opt_eager_fpu =3D=3D -1 ) - opt_eager_fpu =3D should_use_eager_fpu(); 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charset="utf-8" Remove lazy FPU support from the VMX code since fully_eager_fpu is now always true. No functional change intended. Signed-off-by: Ross Lagerwall Reviewed-by: Andrew Cooper --- xen/arch/x86/hvm/vmx/vmcs.c | 8 +-- xen/arch/x86/hvm/vmx/vmx.c | 70 +------------------------ xen/arch/x86/hvm/vmx/vvmx.c | 15 +----- xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 2 - 4 files changed, 5 insertions(+), 90 deletions(-) diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index c2e7f9aed39f..8e52ef4d497a 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -1247,10 +1247,7 @@ static int construct_vmcs(struct vcpu *v) __vmwrite(HOST_TR_SELECTOR, TSS_SELECTOR); =20 /* Host control registers. */ - v->arch.hvm.vmx.host_cr0 =3D read_cr0() & ~X86_CR0_TS; - if ( !v->arch.fully_eager_fpu ) - v->arch.hvm.vmx.host_cr0 |=3D X86_CR0_TS; - __vmwrite(HOST_CR0, v->arch.hvm.vmx.host_cr0); + __vmwrite(HOST_CR0, read_cr0()); __vmwrite(HOST_CR4, mmu_cr4_features); if ( cpu_has_vmx_efer ) __vmwrite(HOST_EFER, read_efer()); @@ -1330,8 +1327,7 @@ static int construct_vmcs(struct vcpu *v) __vmwrite(VMCS_LINK_POINTER, ~0UL); =20 v->arch.hvm.vmx.exception_bitmap =3D HVM_TRAP_MASK - | (paging_mode_hap(d) ? 0 : (1U << X86_EXC_PF)) - | (v->arch.fully_eager_fpu ? 0 : (1U << X86_EXC_NM)); + | (paging_mode_hap(d) ? 0 : (1U << X86_EXC_PF)); =20 if ( cpu_has_vmx_notify_vm_exiting ) __vmwrite(NOTIFY_WINDOW, vm_notify_window); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 82c55f49aea9..03daf2f52bf2 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -68,7 +68,6 @@ static void cf_check vmx_update_guest_cr( struct vcpu *v, unsigned int cr, unsigned int flags); static void cf_check vmx_update_guest_efer(struct vcpu *v); static void cf_check vmx_wbinvd_intercept(void); -static void cf_check vmx_fpu_dirty_intercept(void); static int cf_check vmx_msr_read_intercept( unsigned int msr, uint64_t *msr_content); static int cf_check vmx_msr_write_intercept( @@ -1130,41 +1129,6 @@ static int cf_check vmx_load_vmcs_ctxt(struct vcpu *= v, struct hvm_hw_cpu *ctxt) return 0; } =20 -static void vmx_fpu_enter(struct vcpu *v) -{ - vcpu_restore_fpu_lazy(v); - v->arch.hvm.vmx.exception_bitmap &=3D ~(1u << X86_EXC_NM); - vmx_update_exception_bitmap(v); - v->arch.hvm.vmx.host_cr0 &=3D ~X86_CR0_TS; - __vmwrite(HOST_CR0, v->arch.hvm.vmx.host_cr0); -} - -static void cf_check vmx_fpu_leave(struct vcpu *v) -{ - ASSERT(!v->fpu_dirtied); - ASSERT(read_cr0() & X86_CR0_TS); - - if ( !(v->arch.hvm.vmx.host_cr0 & X86_CR0_TS) ) - { - v->arch.hvm.vmx.host_cr0 |=3D X86_CR0_TS; - __vmwrite(HOST_CR0, v->arch.hvm.vmx.host_cr0); - } - - /* - * If the guest does not have TS enabled then we must cause and handle= an - * exception on first use of the FPU. If the guest *does* have TS enab= led - * then this is not necessary: no FPU activity can occur until the gue= st - * clears CR0.TS, and we will initialise the FPU when that happens. - */ - if ( !(v->arch.hvm.guest_cr[0] & X86_CR0_TS) ) - { - v->arch.hvm.hw_cr[0] |=3D X86_CR0_TS; - __vmwrite(GUEST_CR0, v->arch.hvm.hw_cr[0]); - v->arch.hvm.vmx.exception_bitmap |=3D (1u << X86_EXC_NM); - vmx_update_exception_bitmap(v); - } -} - static void cf_check vmx_ctxt_switch_from(struct vcpu *v) { /* @@ -1187,8 +1151,6 @@ static void cf_check vmx_ctxt_switch_from(struct vcpu= *v) vmx_vmcs_reload(v); } =20 - if ( !v->arch.fully_eager_fpu ) - vmx_fpu_leave(v); vmx_save_guest_msrs(v); vmx_restore_host_msrs(); vmx_save_dr(v); @@ -1771,17 +1733,6 @@ static void cf_check vmx_update_guest_cr( else nvmx_set_cr_read_shadow(v, 0); =20 - if ( !(v->arch.hvm.guest_cr[0] & X86_CR0_TS) ) - { - if ( v !=3D current ) - { - if ( !v->arch.fully_eager_fpu ) - hw_cr0_mask |=3D X86_CR0_TS; - } - else if ( v->arch.hvm.hw_cr[0] & X86_CR0_TS ) - vmx_fpu_enter(v); - } - realmode =3D !(v->arch.hvm.guest_cr[0] & X86_CR0_PE); =20 if ( !vmx_unrestricted_guest(v) && @@ -2915,7 +2866,6 @@ static struct hvm_function_table __initdata_cf_clobbe= r vmx_function_table =3D { .update_guest_cr =3D vmx_update_guest_cr, .update_guest_efer =3D vmx_update_guest_efer, .cpuid_policy_changed =3D vmx_cpuid_policy_changed, - .fpu_leave =3D vmx_fpu_leave, .set_guest_pat =3D vmx_set_guest_pat, .get_guest_pat =3D vmx_get_guest_pat, .set_tsc_offset =3D vmx_set_tsc_offset, @@ -2927,7 +2877,6 @@ static struct hvm_function_table __initdata_cf_clobbe= r vmx_function_table =3D { .cpu_up =3D vmx_cpu_up, .cpu_down =3D vmx_cpu_down, .wbinvd_intercept =3D vmx_wbinvd_intercept, - .fpu_dirty_intercept =3D vmx_fpu_dirty_intercept, .msr_read_intercept =3D vmx_msr_read_intercept, .msr_write_intercept =3D vmx_msr_write_intercept, .handle_cd =3D vmx_handle_cd, @@ -3281,20 +3230,6 @@ void update_guest_eip(void) hvm_inject_hw_exception(X86_EXC_DB, X86_EVENT_NO_EC); } =20 -static void cf_check vmx_fpu_dirty_intercept(void) -{ - struct vcpu *curr =3D current; - - vmx_fpu_enter(curr); - - /* Disable TS in guest CR0 unless the guest wants the exception too. */ - if ( !(curr->arch.hvm.guest_cr[0] & X86_CR0_TS) ) - { - curr->arch.hvm.hw_cr[0] &=3D ~X86_CR0_TS; - __vmwrite(GUEST_CR0, curr->arch.hvm.hw_cr[0]); - } -} - static void vmx_dr_access(unsigned long exit_qualification, struct cpu_user_regs *regs) { @@ -4543,10 +4478,7 @@ void asmlinkage vmx_vmexit_handler(struct cpu_user_r= egs *regs) domain_pause_for_debugger(); } break; - case X86_EXC_NM: - TRACE(TRC_HVM_TRAP, vector); - vmx_fpu_dirty_intercept(); - break; + case X86_EXC_PF: __vmread(EXIT_QUALIFICATION, &exit_qualification); __vmread(VM_EXIT_INTR_ERROR_CODE, &ecode); diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c index 38952f06961e..e4cdfe55c18e 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1238,9 +1238,6 @@ static void virtual_vmentry(struct cpu_user_regs *reg= s) regs->rsp =3D get_vvmcs(v, GUEST_RSP); regs->rflags =3D get_vvmcs(v, GUEST_RFLAGS); =20 - /* updating host cr0 to sync TS bit */ - __vmwrite(HOST_CR0, v->arch.hvm.vmx.host_cr0); - /* Setup virtual ETP for L2 guest*/ if ( nestedhvm_paging_mode_hap(v) ) /* This will setup the initial np2m for the nested vCPU */ @@ -1468,9 +1465,6 @@ static void virtual_vmexit(struct cpu_user_regs *regs) /* VM exit clears all bits except bit 1 */ regs->rflags =3D X86_EFLAGS_MBS; =20 - /* updating host cr0 to sync TS bit */ - __vmwrite(HOST_CR0, v->arch.hvm.vmx.host_cr0); - if ( cpu_has_vmx_virtual_intr_delivery ) nvmx_update_apicv(v); =20 @@ -2458,19 +2452,14 @@ int nvmx_n2_vmexit_handler(struct cpu_user_regs *re= gs, __vmread(VM_EXIT_INTR_INFO, &intr_info); vector =3D intr_info & INTR_INFO_VECTOR_MASK; /* - * decided by L0 and L1 exception bitmap, if the vetor is set by - * both, L0 has priority on #PF and #NM, L1 has priority on others + * decided by L0 and L1 exception bitmap, if the vector is set by + * both, L0 has priority on #PF, L1 has priority on others */ if ( vector =3D=3D X86_EXC_PF ) { if ( paging_mode_hap(v->domain) ) nvcpu->nv_vmexit_pending =3D 1; } - else if ( vector =3D=3D X86_EXC_NM ) - { - if ( v->fpu_dirtied ) - nvcpu->nv_vmexit_pending =3D 1; - } else if ( (intr_info & valid_mask) =3D=3D valid_mask ) { exec_bitmap =3D get_vvmcs(v, EXCEPTION_BITMAP); diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include= /asm/hvm/vmx/vmcs.h index 879ec10cefd0..88bded5190c9 100644 --- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h +++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h @@ -149,8 +149,6 @@ struct vmx_vcpu { DECLARE_BITMAP(eoi_exit_bitmap, X86_IDT_VECTORS); struct pi_desc pi_desc; =20 - unsigned long host_cr0; - /* Do we need to tolerate a spurious EPT_MISCONFIG VM exit? */ bool ept_spurious_misconfig; =20 --=20 2.53.0 From nobody Mon Mar 23 19:52:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; 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charset="utf-8" Remove lazy FPU support from the SVM code since fully_eager_fpu is now always true. No functional change intended. Signed-off-by: Ross Lagerwall Reviewed-by: Andrew Cooper --- xen/arch/x86/hvm/svm/nestedsvm.c | 67 +------------------- xen/arch/x86/hvm/svm/svm.c | 81 +----------------------- xen/arch/x86/hvm/svm/vmcb.c | 4 +- xen/arch/x86/include/asm/hvm/svm-types.h | 6 -- 4 files changed, 4 insertions(+), 154 deletions(-) diff --git a/xen/arch/x86/hvm/svm/nestedsvm.c b/xen/arch/x86/hvm/svm/nested= svm.c index a63ec613465f..ef6fa5d23b67 100644 --- a/xen/arch/x86/hvm/svm/nestedsvm.c +++ b/xen/arch/x86/hvm/svm/nestedsvm.c @@ -165,58 +165,6 @@ int cf_check nsvm_vcpu_reset(struct vcpu *v) return 0; } =20 -static uint64_t nestedsvm_fpu_vmentry(uint64_t n1cr0, - struct vmcb_struct *vvmcb, - struct vmcb_struct *n1vmcb, struct vmcb_struct *n2vmcb) -{ - uint64_t vcr0; - - vcr0 =3D vvmcb->_cr0; - if ( !(n1cr0 & X86_CR0_TS) && (n1vmcb->_cr0 & X86_CR0_TS) ) - { - /* - * svm_fpu_leave() run while l1 guest was running. - * Sync FPU state with l2 guest. - */ - vcr0 |=3D X86_CR0_TS; - n2vmcb->_exception_intercepts |=3D (1U << X86_EXC_NM); - } - else if ( !(vcr0 & X86_CR0_TS) && (n2vmcb->_cr0 & X86_CR0_TS) ) - { - /* - * svm_fpu_enter() run while l1 guest was running. - * Sync FPU state with l2 guest. - */ - vcr0 &=3D ~X86_CR0_TS; - n2vmcb->_exception_intercepts &=3D ~(1U << X86_EXC_NM); - } - - return vcr0; -} - -static void nestedsvm_fpu_vmexit(struct vmcb_struct *n1vmcb, - struct vmcb_struct *n2vmcb, uint64_t n1cr0, uint64_t guest_cr0) -{ - if ( !(guest_cr0 & X86_CR0_TS) && (n2vmcb->_cr0 & X86_CR0_TS) ) - { - /* - * svm_fpu_leave() run while l2 guest was running. - * Sync FPU state with l1 guest. - */ - n1vmcb->_cr0 |=3D X86_CR0_TS; - n1vmcb->_exception_intercepts |=3D (1U << X86_EXC_NM); - } - else if ( !(n1cr0 & X86_CR0_TS) && (n1vmcb->_cr0 & X86_CR0_TS) ) - { - /* - * svm_fpu_enter() run while l2 guest was running. - * Sync FPU state with l1 guest. - */ - n1vmcb->_cr0 &=3D ~X86_CR0_TS; - n1vmcb->_exception_intercepts &=3D ~(1U << X86_EXC_NM); - } -} - static int nsvm_vcpu_hostsave(struct vcpu *v, unsigned int inst_len) { struct nestedsvm *svm =3D &vcpu_nestedsvm(v); @@ -246,7 +194,6 @@ static int nsvm_vcpu_hostsave(struct vcpu *v, unsigned = int inst_len) static int nsvm_vcpu_hostrestore(struct vcpu *v, struct cpu_user_regs *reg= s) { struct nestedvcpu *nv =3D &vcpu_nestedhvm(v); - struct nestedsvm *svm =3D &vcpu_nestedsvm(v); struct vmcb_struct *n1vmcb, *n2vmcb; int rc; =20 @@ -281,8 +228,6 @@ static int nsvm_vcpu_hostrestore(struct vcpu *v, struct= cpu_user_regs *regs) gdprintk(XENLOG_ERR, "hvm_set_cr4 failed, rc: %u\n", rc); =20 /* CR0 */ - nestedsvm_fpu_vmexit(n1vmcb, n2vmcb, - svm->ns_cr0, v->arch.hvm.guest_cr[0]); v->arch.hvm.guest_cr[0] =3D n1vmcb->_cr0 | X86_CR0_PE; n1vmcb->rflags &=3D ~X86_EFLAGS_VM; rc =3D hvm_set_cr0(n1vmcb->_cr0 | X86_CR0_PE, true); @@ -290,7 +235,6 @@ static int nsvm_vcpu_hostrestore(struct vcpu *v, struct= cpu_user_regs *regs) hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) gdprintk(XENLOG_ERR, "hvm_set_cr0 failed, rc: %u\n", rc); - svm->ns_cr0 =3D v->arch.hvm.guest_cr[0]; =20 /* CR2 */ v->arch.hvm.guest_cr[2] =3D n1vmcb->_cr2; @@ -418,7 +362,6 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, stru= ct cpu_user_regs *regs) struct vmcb_struct *ns_vmcb, *n1vmcb, *n2vmcb; vmcbcleanbits_t clean =3D {}; int rc; - uint64_t cr0; =20 ns_vmcb =3D nv->nv_vvmcx; n1vmcb =3D nv->nv_n1vmcx; @@ -452,7 +395,6 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, stru= ct cpu_user_regs *regs) * safed here. * The overhead comes from (ordered from highest to lowest): * - svm_ctxt_switch_to (CPU context switching) - * - svm_fpu_enter, svm_fpu_leave (lazy FPU switching) * - emulated CLGI (clears VINTR intercept) * - host clears VINTR intercept * Test results show that the overhead is high enough that the @@ -551,10 +493,8 @@ static int nsvm_vmcb_prepare4vmrun(struct vcpu *v, str= uct cpu_user_regs *regs) gdprintk(XENLOG_ERR, "hvm_set_cr4 failed, rc: %u\n", rc); =20 /* CR0 */ - svm->ns_cr0 =3D v->arch.hvm.guest_cr[0]; - cr0 =3D nestedsvm_fpu_vmentry(svm->ns_cr0, ns_vmcb, n1vmcb, n2vmcb); v->arch.hvm.guest_cr[0] =3D ns_vmcb->_cr0; - rc =3D hvm_set_cr0(cr0, true); + rc =3D hvm_set_cr0(ns_vmcb->_cr0, true); if ( rc =3D=3D X86EMUL_EXCEPTION ) hvm_inject_hw_exception(X86_EXC_GP, 0); if ( rc !=3D X86EMUL_OKAY ) @@ -1305,11 +1245,6 @@ nestedsvm_check_intercepts(struct vcpu *v, struct cp= u_user_regs *regs, case VMEXIT_INTR: case VMEXIT_NMI: return NESTEDHVM_VMEXIT_HOST; - case VMEXIT_EXCEPTION_NM: - /* Host must handle lazy fpu context switching first. - * Then inject the VMEXIT if L1 guest intercepts this. - */ - return NESTEDHVM_VMEXIT_HOST; =20 case VMEXIT_NPF: if ( nestedhvm_paging_mode_hap(v) ) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 243c41fb13a8..2546705d245c 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -104,38 +104,6 @@ static void cf_check svm_cpu_down(void) write_efer(read_efer() & ~EFER_SVME); } =20 -static void svm_fpu_enter(struct vcpu *v) -{ - struct vmcb_struct *n1vmcb =3D vcpu_nestedhvm(v).nv_n1vmcx; - - vcpu_restore_fpu_lazy(v); - vmcb_set_exception_intercepts( - n1vmcb, - vmcb_get_exception_intercepts(n1vmcb) & ~(1U << X86_EXC_NM)); -} - -static void cf_check svm_fpu_leave(struct vcpu *v) -{ - struct vmcb_struct *n1vmcb =3D vcpu_nestedhvm(v).nv_n1vmcx; - - ASSERT(!v->fpu_dirtied); - ASSERT(read_cr0() & X86_CR0_TS); - - /* - * If the guest does not have TS enabled then we must cause and handle= an - * exception on first use of the FPU. If the guest *does* have TS enab= led - * then this is not necessary: no FPU activity can occur until the gue= st - * clears CR0.TS, and we will initialise the FPU when that happens. - */ - if ( !(v->arch.hvm.guest_cr[0] & X86_CR0_TS) ) - { - vmcb_set_exception_intercepts( - n1vmcb, - vmcb_get_exception_intercepts(n1vmcb) | (1U << X86_EXC_NM)); - vmcb_set_cr0(n1vmcb, vmcb_get_cr0(n1vmcb) | X86_CR0_TS); - } -} - static void cf_check svm_update_guest_cr( struct vcpu *v, unsigned int cr, unsigned int flags) { @@ -145,20 +113,6 @@ static void cf_check svm_update_guest_cr( switch ( cr ) { case 0: - { - unsigned long hw_cr0_mask =3D 0; - - if ( !(v->arch.hvm.guest_cr[0] & X86_CR0_TS) ) - { - if ( v !=3D current ) - { - if ( !v->arch.fully_eager_fpu ) - hw_cr0_mask |=3D X86_CR0_TS; - } - else if ( vmcb_get_cr0(vmcb) & X86_CR0_TS ) - svm_fpu_enter(v); - } - if ( paging_mode_hap(v->domain) ) { uint32_t intercepts =3D vmcb_get_cr_intercepts(vmcb); @@ -169,12 +123,12 @@ static void cf_check svm_update_guest_cr( vmcb_set_cr_intercepts(vmcb, intercepts | CR_INTERCEPT_CR3_= WRITE); } =20 - value =3D v->arch.hvm.guest_cr[0] | hw_cr0_mask; + value =3D v->arch.hvm.guest_cr[0]; if ( paging_mode_shadow(v->domain) ) value |=3D X86_CR0_PG | X86_CR0_WP; vmcb_set_cr0(vmcb, value); break; - } + case 2: vmcb_set_cr2(vmcb, v->arch.hvm.guest_cr[2]); break; @@ -909,9 +863,6 @@ static void cf_check svm_ctxt_switch_from(struct vcpu *= v) if ( unlikely((read_efer() & EFER_SVME) =3D=3D 0) ) return; =20 - if ( !v->arch.fully_eager_fpu ) - svm_fpu_leave(v); - svm_save_dr(v); svm_tsc_ratio_save(v); =20 @@ -1678,28 +1629,6 @@ static void svm_do_nested_pgfault(struct vcpu *v, domain_crash(v->domain); } =20 -static void cf_check svm_fpu_dirty_intercept(void) -{ - struct vcpu *v =3D current; - struct vmcb_struct *vmcb =3D v->arch.hvm.svm.vmcb; - struct vmcb_struct *n1vmcb =3D vcpu_nestedhvm(v).nv_n1vmcx; - - svm_fpu_enter(v); - - if ( vmcb !=3D n1vmcb ) - { - /* Check if l1 guest must make FPU ready for the l2 guest */ - if ( v->arch.hvm.guest_cr[0] & X86_CR0_TS ) - hvm_inject_hw_exception(X86_EXC_NM, X86_EVENT_NO_EC); - else - vmcb_set_cr0(n1vmcb, vmcb_get_cr0(n1vmcb) & ~X86_CR0_TS); - return; - } - - if ( !(v->arch.hvm.guest_cr[0] & X86_CR0_TS) ) - vmcb_set_cr0(vmcb, vmcb_get_cr0(vmcb) & ~X86_CR0_TS); -} - static void svm_vmexit_do_cr_access( struct vmcb_struct *vmcb, struct cpu_user_regs *regs) { @@ -2459,7 +2388,6 @@ static struct hvm_function_table __initdata_cf_clobbe= r svm_function_table =3D { .update_guest_cr =3D svm_update_guest_cr, .update_guest_efer =3D svm_update_guest_efer, .cpuid_policy_changed =3D svm_cpuid_policy_changed, - .fpu_leave =3D svm_fpu_leave, .set_guest_pat =3D svm_set_guest_pat, .get_guest_pat =3D svm_get_guest_pat, .set_tsc_offset =3D svm_set_tsc_offset, @@ -2469,7 +2397,6 @@ static struct hvm_function_table __initdata_cf_clobbe= r svm_function_table =3D { .get_pending_event =3D svm_get_pending_event, .invlpg =3D svm_invlpg, .wbinvd_intercept =3D svm_wbinvd_intercept, - .fpu_dirty_intercept =3D svm_fpu_dirty_intercept, .msr_read_intercept =3D svm_msr_read_intercept, .msr_write_intercept =3D svm_msr_write_intercept, #ifdef CONFIG_VM_EVENT @@ -2783,10 +2710,6 @@ void asmlinkage svm_vmexit_handler(void) } break; =20 - case VMEXIT_EXCEPTION_NM: - svm_fpu_dirty_intercept(); - break; - case VMEXIT_EXCEPTION_PF: { unsigned long va =3D vmcb->ei.exc.cr2; diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index e583ef8548c7..5ed7123d9a69 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -138,9 +138,7 @@ static int construct_vmcb(struct vcpu *v) =20 paging_update_paging_modes(v); =20 - vmcb->_exception_intercepts =3D - HVM_TRAP_MASK | - (v->arch.fully_eager_fpu ? 0 : (1U << X86_EXC_NM)); + vmcb->_exception_intercepts =3D HVM_TRAP_MASK; =20 if ( paging_mode_hap(v->domain) ) { diff --git a/xen/arch/x86/include/asm/hvm/svm-types.h b/xen/arch/x86/includ= e/asm/hvm/svm-types.h index 051b235d8f69..3ede62cade80 100644 --- a/xen/arch/x86/include/asm/hvm/svm-types.h +++ b/xen/arch/x86/include/asm/hvm/svm-types.h @@ -65,12 +65,6 @@ struct nestedsvm { /* Shadow io permission map */ unsigned long *ns_iomap; =20 - /* - * Cached guest_cr[0] of l1 guest while l2 guest runs. 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charset="utf-8" From: Wei Liu Remove lazy FPU support from the #DNA exception handler used by PV guests since fully_eager_fpu is now always true. Signed-off-by: Ross Lagerwall Signed-off-by: Wei Liu --- xen/arch/x86/i387.c | 24 ------------------------ xen/arch/x86/include/asm/i387.h | 1 - xen/arch/x86/pv/misc-hypercalls.c | 3 +-- xen/arch/x86/traps.c | 18 ++++++++++-------- 4 files changed, 11 insertions(+), 35 deletions(-) diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 954ba3b1799b..7da731865f73 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -234,30 +234,6 @@ void vcpu_restore_fpu_nonlazy(struct vcpu *v, bool nee= d_stts) stts(); } =20 -/*=20 - * Restore FPU state when #NM is triggered. - */ -void vcpu_restore_fpu_lazy(struct vcpu *v) -{ - ASSERT(!is_idle_vcpu(v)); - - /* Avoid recursion. */ - clts(); - - if ( v->fpu_dirtied ) - return; - - ASSERT(!v->arch.fully_eager_fpu); - - if ( cpu_has_xsave ) - fpu_xrstor(v, XSTATE_LAZY); - else - fpu_fxrstor(v); - - v->fpu_initialised =3D 1; - v->fpu_dirtied =3D 1; -} - /*=20 * On each context switch, save the necessary FPU info of VCPU being switc= h=20 * out. It dispatches saving operation based on CPU's capability. diff --git a/xen/arch/x86/include/asm/i387.h b/xen/arch/x86/include/asm/i38= 7.h index 652d7ad2deb6..da0c7e945f95 100644 --- a/xen/arch/x86/include/asm/i387.h +++ b/xen/arch/x86/include/asm/i387.h @@ -28,7 +28,6 @@ struct ix87_env { }; =20 void vcpu_restore_fpu_nonlazy(struct vcpu *v, bool need_stts); -void vcpu_restore_fpu_lazy(struct vcpu *v); void vcpu_save_fpu(struct vcpu *v); void save_fpu_enable(void); int vcpu_init_fpu(struct vcpu *v); diff --git a/xen/arch/x86/pv/misc-hypercalls.c b/xen/arch/x86/pv/misc-hyper= calls.c index 7e915d86b724..34a0717540a9 100644 --- a/xen/arch/x86/pv/misc-hypercalls.c +++ b/xen/arch/x86/pv/misc-hypercalls.c @@ -42,8 +42,7 @@ long do_fpu_taskswitch(int set) else { v->arch.pv.ctrlreg[0] &=3D ~X86_CR0_TS; - if ( v->fpu_dirtied ) - clts(); + clts(); } =20 return 0; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index b6b119769722..fb1b94245850 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2045,15 +2045,17 @@ void asmlinkage do_device_not_available(struct cpu_= user_regs *regs) } =20 #ifdef CONFIG_PV - vcpu_restore_fpu_lazy(curr); + BUG_ON(!(curr->arch.pv.ctrlreg[0] & X86_CR0_TS)); =20 - if ( curr->arch.pv.ctrlreg[0] & X86_CR0_TS ) - { - pv_inject_hw_exception(X86_EXC_NM, X86_EVENT_NO_EC); - curr->arch.pv.ctrlreg[0] &=3D ~X86_CR0_TS; - } - else - TRACE_TIME(TRC_PV_MATH_STATE_RESTORE); + /* + * PV ABI QUIRK: Classic Xen kernels (2.6.18 and SLES 11 SP4's + * 3.0) rely on Xen to clear TS. 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Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Ross Lagerwall Subject: [PATCH v1 5/8] x86: Remove fully_eager_fpu Date: Thu, 19 Mar 2026 13:29:21 +0000 Message-ID: <20260319132924.1469809-6-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260319132924.1469809-1-ross.lagerwall@citrix.com> References: <20260319132924.1469809-1-ross.lagerwall@citrix.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P123CA0494.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1ab::13) To DS0PR03MB8272.namprd03.prod.outlook.com (2603:10b6:8:28f::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR03MB8272:EE_|SA5PR03MB989126:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c6808b9-8a3a-4e6e-79e6-08de85bb9618 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: 7Jk04xFgYjszEZVIDtFHs2cmUlo3r3ALY3aqBq4y6jcMUhrCOU8hMTlNpQffq5hG+nCN3xdN3isircb+wyKiLUb89Y7CClwOOEpUEgsA/ZAPEHki2JKUxugY/cMUq3MbjOtaDthOHdB4tN+p/KUKpqUIB3oXygV8rs1mV8stqilFIg6A9km2AsdY1pIc4FR98DIqjQGYCdOB4W8meu+b0TX1I12zyGt1vvarxSNM9JeLzVo8ZtlGeyhLC9EhEaNJBuaT/HyFij3cyVIWt0CHMUvVrJcfQcb5rtEQZkJy2K8Oh4oDSC02zeyPFe8HLV89/OK1rIEe5dLRtyFHxvIFcofD954UsQ4xKxFL4qLxfGruMMUlxV3Q3WoBcStrDEwvO1PXENIyarsi5WCLZIVPAg1pcsgLoy3HCZN8eVUcTz5LalDm1yhpQ8GqBZm3afjw8we9fr83qv5byvLwcrB0ronpYCPC/KyME76j1zzYruFkd2B3XX2rEzNb47ORm23krFyHPn5a+4O+swDOf7NUNVnXudV2HO2819YUIvej38kWMhSedIMbY8FHUsl+EudVlBJ8Y1ev6z4dKpCT5VAwJgEiR0ACoHdHKWV+TZ/ml4tCDtyAkXtg+mB8wTYZE0pLwFgqUrkDlRQCODT9VnA3XBYorrikte7ajcr3E7qyrY9TIG1KZpEfP1W6icK5MCv1wbygqPMsJszh711c183SQ1euTnQyuhkXfGj5nSbeSPM= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR03MB8272.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(376014)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; 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charset="utf-8" Since fully_eager_fpu is always true, remove it and adjust the code accordingly. At the same time, rename vcpu_restore_fpu_nonlazy since it always does the full restore. No functional change intended. Signed-off-by: Ross Lagerwall Reviewed-by: Andrew Cooper --- xen/arch/x86/domain.c | 2 +- xen/arch/x86/hvm/emulate.c | 18 +-------------- xen/arch/x86/i387.c | 35 ++++++++---------------------- xen/arch/x86/include/asm/domain.h | 3 --- xen/arch/x86/include/asm/hvm/hvm.h | 2 -- xen/arch/x86/include/asm/i387.h | 2 +- xen/common/efi/runtime.c | 2 +- 7 files changed, 13 insertions(+), 51 deletions(-) diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 4664264b2f5d..a68b7a583294 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -2125,7 +2125,7 @@ static void __context_switch(void) if ( cpu_has_xsaves && is_hvm_vcpu(n) ) set_msr_xss(n->arch.msrs->xss.raw); } - vcpu_restore_fpu_nonlazy(n, false); + vcpu_restore_fpu(n); nd->arch.ctxt_switch->to(n); } =20 diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index 86b1f7535668..2daea084f15c 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -2630,23 +2630,7 @@ static void cf_check hvmemul_put_fpu( } =20 if ( backout =3D=3D X86EMUL_FPU_fpu ) - { - /* - * To back out changes to the register file - * - in fully eager mode, restore original state immediately, - * - in lazy mode, simply adjust state such that upon next FPU insn - * use by the guest we'll reload the state saved (or freshly loa= ded) - * by hvmemul_get_fpu(). - */ - if ( curr->arch.fully_eager_fpu ) - vcpu_restore_fpu_nonlazy(curr, false); - else - { - curr->fpu_dirtied =3D false; - stts(); - alternative_vcall(hvm_funcs.fpu_leave, curr); - } - } + vcpu_restore_fpu(curr); } =20 static int cf_check hvmemul_tlb_op( diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 7da731865f73..88018397b1ad 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -194,12 +194,8 @@ static inline void fpu_fxsave(struct vcpu *v) /* VCPU FPU Functions */ /*******************************/ /* Restore FPU state whenever VCPU is schduled in. */ -void vcpu_restore_fpu_nonlazy(struct vcpu *v, bool need_stts) +void vcpu_restore_fpu(struct vcpu *v) { - /* Restore nonlazy extended state (i.e. parts not tracked by CR0.TS). = */ - if ( !v->arch.fully_eager_fpu && !v->arch.nonlazy_xstate_used ) - goto maybe_stts; - ASSERT(!is_idle_vcpu(v)); =20 /* Avoid recursion */ @@ -210,27 +206,16 @@ void vcpu_restore_fpu_nonlazy(struct vcpu *v, bool ne= ed_stts) * above) we also need to restore full state, to prevent subsequently * saving state belonging to another vCPU. */ - if ( v->arch.fully_eager_fpu || xstate_all(v) ) - { - if ( cpu_has_xsave ) - fpu_xrstor(v, XSTATE_ALL); - else - fpu_fxrstor(v); - - v->fpu_initialised =3D 1; - v->fpu_dirtied =3D 1; - - /* Xen doesn't need TS set, but the guest might. */ - need_stts =3D is_pv_vcpu(v) && (v->arch.pv.ctrlreg[0] & X86_CR0_TS= ); - } + if ( cpu_has_xsave ) + fpu_xrstor(v, XSTATE_ALL); else - { - fpu_xrstor(v, XSTATE_NONLAZY); - need_stts =3D true; - } + fpu_fxrstor(v); =20 - maybe_stts: - if ( need_stts ) + v->fpu_initialised =3D 1; + v->fpu_dirtied =3D 1; + + /* Xen doesn't need TS set, but the guest might. */ + if ( is_pv_vcpu(v) && (v->arch.pv.ctrlreg[0] & X86_CR0_TS) ) stts(); } =20 @@ -273,8 +258,6 @@ void save_fpu_enable(void) /* Initialize FPU's context save area */ int vcpu_init_fpu(struct vcpu *v) { - v->arch.fully_eager_fpu =3D true; - return xstate_alloc_save_area(v); } =20 diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index ad7f6adb2cb9..bd7b02085ef8 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -671,9 +671,6 @@ struct arch_vcpu * and thus should be saved/restored. */ bool nonlazy_xstate_used; =20 - /* Restore all FPU state (lazy and non-lazy state) on context switch? = */ - bool fully_eager_fpu; - struct vmce vmce; =20 struct paging_vcpu paging; diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index 7d9774df59fe..a9425c8cffe8 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -160,8 +160,6 @@ struct hvm_function_table { =20 void (*cpuid_policy_changed)(struct vcpu *v); =20 - void (*fpu_leave)(struct vcpu *v); - int (*get_guest_pat)(struct vcpu *v, uint64_t *gpat); int (*set_guest_pat)(struct vcpu *v, uint64_t gpat); =20 diff --git a/xen/arch/x86/include/asm/i387.h b/xen/arch/x86/include/asm/i38= 7.h index da0c7e945f95..fe5e4419b6f4 100644 --- a/xen/arch/x86/include/asm/i387.h +++ b/xen/arch/x86/include/asm/i387.h @@ -27,7 +27,7 @@ struct ix87_env { uint16_t fds, _res6; }; =20 -void vcpu_restore_fpu_nonlazy(struct vcpu *v, bool need_stts); +void vcpu_restore_fpu(struct vcpu *v); void vcpu_save_fpu(struct vcpu *v); void save_fpu_enable(void); int vcpu_init_fpu(struct vcpu *v); diff --git a/xen/common/efi/runtime.c b/xen/common/efi/runtime.c index ba27c62132d2..982e42e8f341 100644 --- a/xen/common/efi/runtime.c +++ b/xen/common/efi/runtime.c @@ -157,7 +157,7 @@ void efi_rs_leave(struct efi_rs_state *state) irq_exit(); efi_rs_on_cpu =3D NR_CPUS; spin_unlock(&efi_rs_lock); - vcpu_restore_fpu_nonlazy(curr, true); + vcpu_restore_fpu(curr); } =20 bool efi_rs_using_pgtables(void) --=20 2.53.0 From nobody Mon Mar 23 19:52:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=citrix.com); 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charset="utf-8" With lazy FPU removed, fpu_initialised and fpu_dirty are always set to true in vcpu_restore_fpu() so remove them and adjust the code accordingly. No functional change intended. Signed-off-by: Ross Lagerwall --- xen/arch/x86/domctl.c | 3 +-- xen/arch/x86/hvm/emulate.c | 6 +----- xen/arch/x86/hvm/hvm.c | 15 ++++++--------- xen/arch/x86/hvm/vlapic.c | 3 --- xen/arch/x86/i387.c | 31 ++---------------------------- xen/arch/x86/include/asm/hvm/hvm.h | 1 - xen/arch/x86/include/asm/xstate.h | 11 ----------- xen/arch/x86/xstate.c | 21 +++++--------------- xen/common/domain.c | 2 -- xen/include/xen/sched.h | 4 ---- 10 files changed, 15 insertions(+), 82 deletions(-) diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index 942f41c584d4..d9b08182ac1d 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1409,8 +1409,7 @@ void arch_get_info_guest(struct vcpu *v, vcpu_guest_c= ontext_u c) c(flags =3D v->arch.pv.vgc_flags & ~(VGCF_i387_valid|VGCF_in_kerne= l)); else c(flags =3D 0); - if ( v->fpu_initialised ) - c(flags |=3D VGCF_i387_valid); + c(flags |=3D VGCF_i387_valid); if ( !(v->pause_flags & VPF_down) ) c(flags |=3D VGCF_online); if ( !compat ) diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index 2daea084f15c..48c7320360c7 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -2517,9 +2517,7 @@ static int cf_check hvmemul_get_fpu( { struct vcpu *curr =3D current; =20 - if ( !curr->fpu_dirtied ) - alternative_vcall(hvm_funcs.fpu_dirty_intercept); - else if ( type =3D=3D X86EMUL_FPU_fpu ) + if ( type =3D=3D X86EMUL_FPU_fpu ) { /* Has a fastpath for `current`, so there's no actual map */ const struct xsave_struct *xsave_area =3D VCPU_MAP_XSAVE_AREA(curr= ); @@ -2537,8 +2535,6 @@ static int cf_check hvmemul_get_fpu( * masking of all exceptions by FNSTENV.) */ save_fpu_enable(); - curr->fpu_initialised =3D true; - curr->fpu_dirtied =3D true; if ( (fpu_ctxt->fcw & 0x3f) !=3D 0x3f ) { uint16_t fcw; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4d37a93c57a5..d4ba82845146 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -866,6 +866,7 @@ static int cf_check hvm_save_cpu_ctxt(struct vcpu *v, h= vm_domain_context_t *h) .dr7 =3D v->arch.dr7, .msr_efer =3D v->arch.hvm.guest_efer, }; + const struct xsave_struct *xsave_area; =20 /* * We don't need to save state for a vcpu that is down; the restore @@ -933,15 +934,11 @@ static int cf_check hvm_save_cpu_ctxt(struct vcpu *v,= hvm_domain_context_t *h) ctxt.ldtr_base =3D seg.base; ctxt.ldtr_arbytes =3D seg.attr; =20 - if ( v->fpu_initialised ) - { - const struct xsave_struct *xsave_area =3D VCPU_MAP_XSAVE_AREA(v); - - BUILD_BUG_ON(sizeof(ctxt.fpu_regs) !=3D sizeof(xsave_area->fpu_sse= )); - memcpy(ctxt.fpu_regs, &xsave_area->fpu_sse, sizeof(ctxt.fpu_regs)); - VCPU_UNMAP_XSAVE_AREA(v, xsave_area); - ctxt.flags =3D XEN_X86_FPU_INITIALISED; - } + xsave_area =3D VCPU_MAP_XSAVE_AREA(v); + BUILD_BUG_ON(sizeof(ctxt.fpu_regs) !=3D sizeof(xsave_area->fpu_sse)); + memcpy(ctxt.fpu_regs, &xsave_area->fpu_sse, sizeof(ctxt.fpu_regs)); + VCPU_UNMAP_XSAVE_AREA(v, xsave_area); + ctxt.flags =3D XEN_X86_FPU_INITIALISED; =20 return hvm_save_entry(CPU, v->vcpu_id, h, &ctxt); } diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c index 79697487ba90..885f5d304b2f 100644 --- a/xen/arch/x86/hvm/vlapic.c +++ b/xen/arch/x86/hvm/vlapic.c @@ -276,7 +276,6 @@ static void vlapic_init_sipi_one(struct vcpu *target, u= int32_t icr) switch ( icr & APIC_DM_MASK ) { case APIC_DM_INIT: { - bool fpu_initialised; int rc; =20 /* No work on INIT de-assert for P4-type APIC. */ @@ -289,10 +288,8 @@ static void vlapic_init_sipi_one(struct vcpu *target, = uint32_t icr) hvm_vcpu_down(target); domain_lock(target->domain); /* Reset necessary VCPU state. This does not include FPU state. */ - fpu_initialised =3D target->fpu_initialised; rc =3D vcpu_reset(target); ASSERT(!rc); - target->fpu_initialised =3D fpu_initialised; vlapic_do_init(vcpu_vlapic(target)); domain_unlock(target->domain); break; diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 88018397b1ad..5e893a2aab94 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -110,22 +110,7 @@ static inline void fpu_fxrstor(struct vcpu *v) =20 static inline uint64_t vcpu_xsave_mask(const struct vcpu *v) { - if ( v->fpu_dirtied ) - return v->arch.nonlazy_xstate_used ? XSTATE_ALL : XSTATE_LAZY; - - ASSERT(v->arch.nonlazy_xstate_used); - - /* - * The offsets of components which live in the extended region of - * compact xsave area are not fixed. Xsave area may be overwritten - * when a xsave with v->fpu_dirtied set is followed by one with - * v->fpu_dirtied clear. - * In such case, if hypervisor uses compact xsave area and guest - * has ever used lazy states (checking xcr0_accum excluding - * XSTATE_FP_SSE), vcpu_xsave_mask will return XSTATE_ALL. Otherwise - * return XSTATE_NONLAZY. - */ - return xstate_all(v) ? XSTATE_ALL : XSTATE_NONLAZY; + return v->arch.nonlazy_xstate_used ? XSTATE_ALL : XSTATE_LAZY; } =20 /* Save x87 extended state */ @@ -201,19 +186,11 @@ void vcpu_restore_fpu(struct vcpu *v) /* Avoid recursion */ clts(); =20 - /* - * When saving full state even with !v->fpu_dirtied (see vcpu_xsave_ma= sk() - * above) we also need to restore full state, to prevent subsequently - * saving state belonging to another vCPU. - */ if ( cpu_has_xsave ) fpu_xrstor(v, XSTATE_ALL); else fpu_fxrstor(v); =20 - v->fpu_initialised =3D 1; - v->fpu_dirtied =3D 1; - /* Xen doesn't need TS set, but the guest might. */ if ( is_pv_vcpu(v) && (v->arch.pv.ctrlreg[0] & X86_CR0_TS) ) stts(); @@ -225,7 +202,7 @@ void vcpu_restore_fpu(struct vcpu *v) */ static bool _vcpu_save_fpu(struct vcpu *v) { - if ( !v->fpu_dirtied && !v->arch.nonlazy_xstate_used ) + if ( !v->arch.nonlazy_xstate_used ) return false; =20 ASSERT(!is_idle_vcpu(v)); @@ -238,8 +215,6 @@ static bool _vcpu_save_fpu(struct vcpu *v) else fpu_fxsave(v); =20 - v->fpu_dirtied =3D 0; - return true; } =20 @@ -265,7 +240,6 @@ void vcpu_reset_fpu(struct vcpu *v) { struct xsave_struct *xsave_area =3D VCPU_MAP_XSAVE_AREA(v); =20 - v->fpu_initialised =3D false; *xsave_area =3D (struct xsave_struct) { .xsave_hdr.xstate_bv =3D X86_XCR0_X87, }; @@ -282,7 +256,6 @@ void vcpu_setup_fpu(struct vcpu *v, const void *data) { struct xsave_struct *xsave_area =3D VCPU_MAP_XSAVE_AREA(v); =20 - v->fpu_initialised =3D true; *xsave_area =3D (struct xsave_struct) { .fpu_sse =3D *(const fpusse_t*)data, .xsave_hdr.xstate_bv =3D XSTATE_FP_SSE, diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index a9425c8cffe8..846b91ebefcc 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -184,7 +184,6 @@ struct hvm_function_table { =20 /* Instruction intercepts: non-void return values are X86EMUL codes. */ void (*wbinvd_intercept)(void); - void (*fpu_dirty_intercept)(void); int (*msr_read_intercept)(unsigned int msr, uint64_t *msr_content); int (*msr_write_intercept)(unsigned int msr, uint64_t msr_content); void (*handle_cd)(struct vcpu *v, unsigned long value); diff --git a/xen/arch/x86/include/asm/xstate.h b/xen/arch/x86/include/asm/x= state.h index e3b9745543d7..ca38c43ec1c3 100644 --- a/xen/arch/x86/include/asm/xstate.h +++ b/xen/arch/x86/include/asm/xstate.h @@ -132,17 +132,6 @@ xsave_area_compressed(const struct xsave_struct *xsave= _area) return xsave_area->xsave_hdr.xcomp_bv & XSTATE_COMPACTION_ENABLED; } =20 -static inline bool xstate_all(const struct vcpu *v) -{ - /* - * XSTATE_FP_SSE may be excluded, because the offsets of XSTATE_FP_SSE - * (in the legacy region of xsave area) are fixed, so saving - * XSTATE_FP_SSE will not cause overwriting problem with XSAVES/XSAVEC. - */ - return xsave_area_compressed(v->arch.xsave_area) && - (v->arch.xcr0_accum & XSTATE_LAZY & ~XSTATE_FP_SSE); -} - /* * Fetch a pointer to a vCPU's XSAVE area * diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index e990abc9d18c..11d390cac985 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -994,28 +994,17 @@ int handle_xsetbv(u32 index, u64 new_bv) if ( new_bv & XSTATE_NONLAZY ) curr->arch.nonlazy_xstate_used =3D 1; =20 - mask &=3D curr->fpu_dirtied ? ~XSTATE_FP_SSE : XSTATE_NONLAZY; + mask &=3D ~XSTATE_FP_SSE; if ( mask ) { unsigned long cr0 =3D read_cr0(); + /* Has a fastpath for `current`, so there's no actual map */ + struct xsave_struct *xsave_area =3D VCPU_MAP_XSAVE_AREA(curr); =20 clts(); - if ( curr->fpu_dirtied ) - { - /* Has a fastpath for `current`, so there's no actual map */ - struct xsave_struct *xsave_area =3D VCPU_MAP_XSAVE_AREA(curr); =20 - asm ( "stmxcsr %0" : "=3Dm" (xsave_area->fpu_sse.mxcsr) ); - VCPU_UNMAP_XSAVE_AREA(curr, xsave_area); - } - else if ( xstate_all(curr) ) - { - /* See the comment in i387.c:vcpu_restore_fpu_eager(). */ - mask |=3D XSTATE_LAZY; - curr->fpu_initialised =3D 1; - curr->fpu_dirtied =3D 1; - cr0 &=3D ~X86_CR0_TS; - } + asm ( "stmxcsr %0" : "=3Dm" (xsave_area->fpu_sse.mxcsr) ); + VCPU_UNMAP_XSAVE_AREA(curr, xsave_area); xrstor(curr, mask); if ( cr0 & X86_CR0_TS ) write_cr0(cr0); diff --git a/xen/common/domain.c b/xen/common/domain.c index ab910fcf9306..30cfea30459a 100644 --- a/xen/common/domain.c +++ b/xen/common/domain.c @@ -1824,8 +1824,6 @@ int vcpu_reset(struct vcpu *v) clear_bit(v->vcpu_id, d->poll_mask); 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charset="utf-8" With the removal of lazy FPU, the full state is always restored on context switch so stop tracking whether nonlazy xstate is used. Signed-off-by: Ross Lagerwall Reviewed-by: Andrew Cooper --- xen/arch/x86/domctl.c | 1 - xen/arch/x86/hvm/hvm.c | 1 - xen/arch/x86/i387.c | 12 +----------- xen/arch/x86/include/asm/domain.h | 3 --- xen/arch/x86/include/asm/xstate.h | 6 ++---- xen/arch/x86/xstate.c | 3 --- 6 files changed, 3 insertions(+), 23 deletions(-) diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c index d9b08182ac1d..a9fbb2d405b7 100644 --- a/xen/arch/x86/domctl.c +++ b/xen/arch/x86/domctl.c @@ -1013,7 +1013,6 @@ long arch_do_domctl( =20 v->arch.xcr0 =3D _xcr0; v->arch.xcr0_accum =3D _xcr0_accum; - v->arch.nonlazy_xstate_used =3D _xcr0_accum & XSTATE_NONLA= ZY; compress_xsave_states(v, _xsave_area, evc->size - PV_XSAVE_HDR_SIZE); =20 diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index d4ba82845146..0e7b66d726ae 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -1383,7 +1383,6 @@ static int cf_check hvm_load_cpu_xsave_states( =20 v->arch.xcr0 =3D ctxt->xcr0; v->arch.xcr0_accum =3D ctxt->xcr0_accum; - v->arch.nonlazy_xstate_used =3D ctxt->xcr0_accum & XSTATE_NONLAZY; compress_xsave_states(v, &ctxt->save_area, size - offsetof(struct hvm_hw_cpu_xsave, save_ar= ea)); =20 diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 5e893a2aab94..9acaaf4673df 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -108,25 +108,18 @@ static inline void fpu_fxrstor(struct vcpu *v) /* FPU Save Functions */ /*******************************/ =20 -static inline uint64_t vcpu_xsave_mask(const struct vcpu *v) -{ - return v->arch.nonlazy_xstate_used ? XSTATE_ALL : XSTATE_LAZY; -} - /* Save x87 extended state */ static inline void fpu_xsave(struct vcpu *v) { bool ok; - uint64_t mask =3D vcpu_xsave_mask(v); =20 - ASSERT(mask); /* * XCR0 normally represents what guest OS set. In case of Xen itself, * we set the accumulated feature mask before doing save/restore. */ ok =3D set_xcr0(v->arch.xcr0_accum | XSTATE_FP_SSE); ASSERT(ok); - xsave(v, mask); + xsave(v, XSTATE_ALL); ok =3D set_xcr0(v->arch.xcr0 ?: XSTATE_FP_SSE); ASSERT(ok); } @@ -202,9 +195,6 @@ void vcpu_restore_fpu(struct vcpu *v) */ static bool _vcpu_save_fpu(struct vcpu *v) { - if ( !v->arch.nonlazy_xstate_used ) - return false; - ASSERT(!is_idle_vcpu(v)); =20 /* This can happen, if a paravirtualised guest OS has set its CR0.TS. = */ diff --git a/xen/arch/x86/include/asm/domain.h b/xen/arch/x86/include/asm/d= omain.h index bd7b02085ef8..385a6666dafa 100644 --- a/xen/arch/x86/include/asm/domain.h +++ b/xen/arch/x86/include/asm/domain.h @@ -667,9 +667,6 @@ struct arch_vcpu * it explicitly enables it via xcr0. */ uint64_t xcr0_accum; - /* This variable determines whether nonlazy extended state has been us= ed, - * and thus should be saved/restored. */ - bool nonlazy_xstate_used; =20 struct vmce vmce; =20 diff --git a/xen/arch/x86/include/asm/xstate.h b/xen/arch/x86/include/asm/x= state.h index ca38c43ec1c3..c96d75e38b25 100644 --- a/xen/arch/x86/include/asm/xstate.h +++ b/xen/arch/x86/include/asm/xstate.h @@ -33,12 +33,10 @@ extern uint32_t mxcsr_mask; #define XSTATE_FP_SSE (X86_XCR0_X87 | X86_XCR0_SSE) #define XCNTXT_MASK (X86_XCR0_X87 | X86_XCR0_SSE | X86_XCR0_YMM | \ X86_XCR0_OPMASK | X86_XCR0_ZMM | X86_XCR0_HI_ZMM |= \ - XSTATE_NONLAZY) + X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | X86_XCR0_PKRU= | \ + X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA) =20 #define XSTATE_ALL (~(1ULL << 63)) -#define XSTATE_NONLAZY (X86_XCR0_BNDREGS | X86_XCR0_BNDCSR | X86_XCR0_PKRU= | \ - X86_XCR0_TILE_CFG | X86_XCR0_TILE_DATA) -#define XSTATE_LAZY (XSTATE_ALL & ~XSTATE_NONLAZY) #define XSTATE_XSAVES_ONLY 0 #define XSTATE_COMPACTION_ENABLED (1ULL << 63) =20 diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86/xstate.c index 11d390cac985..658f372b8c51 100644 --- a/xen/arch/x86/xstate.c +++ b/xen/arch/x86/xstate.c @@ -991,9 +991,6 @@ int handle_xsetbv(u32 index, u64 new_bv) curr->arch.xcr0 =3D new_bv; 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Smith" , =?UTF-8?q?Marek=20Marczykowski-G=C3=B3recki?= , Ross Lagerwall Subject: [PATCH v1 8/8] x86: Cleanup cr0.TS flag handling Date: Thu, 19 Mar 2026 13:29:24 +0000 Message-ID: <20260319132924.1469809-9-ross.lagerwall@citrix.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260319132924.1469809-1-ross.lagerwall@citrix.com> References: <20260319132924.1469809-1-ross.lagerwall@citrix.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: LO4P123CA0386.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:18f::13) To DS0PR03MB8272.namprd03.prod.outlook.com (2603:10b6:8:28f::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR03MB8272:EE_|SA5PR03MB989126:EE_ X-MS-Office365-Filtering-Correlation-Id: d151aaed-d82d-476c-06b0-08de85bb9cea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: K+D7OHr7VF72xv+793Yv9oP+I2jIrVZc459Fc6EpgKidupw4IEEzv6OgSf2+TNzdrQtoPrU+deL6ue7SsHs8L1Yw3+Lmkw/TPuiJEOAFv5bGuGZftthwHd89y+pvEoTHSpmaAkcceahPJK4zj9i6a6cGzCtt3Gyk5y3zIgk8LI14x+9KqJBTUU+o6zwqv5BpWrig490W134fhsrFx1WVc5Zp35Sb16L2uc2+cuuHPs6oHoVc1E+mzqw70v/czLp7ftaKE69/ovcMQnh9dU1uP1CTIiHsXuzFiYkZrEOePE95MFYXr+4LOSWcHm/y1xJAi1l6IPNn8brF9b8bpkYAmy11YqbIiwzPGFV+EnpypN58R3SoKBbONTU8ixcKvPsSqNc3/culPR10BEDiSO5KDevOO4vXscAChRPNQzpy+PVs2Ab1DUFU5w0jagGxG9lIYSr2j90FqJJkHE2lF5vCJyPn0CZyWhZxoySKJuFH8MDz1OeU1bvbOxlZxYDc/pvqu9DBjU6IFV8N+7r63rMAQcAJPqh1XUpb/L9FcCMb7OxlB2Wm6yr+wZpzXilGUi98FrxN3h+d3IhKpw13K7VBOPk6C6yhXuOfz+qfG0KPMBFZ/CJ4MWyyi09DHAJwIWpHbb1vvnryK2hn3MQEv9tnVaxHSy+HwdQu+pM3UYacBgkbA12auc5ejGObM48TK5IBntxT+/WnQbrZiUnFOu45yR9C1Efkqwm7IrxAP6da5xU= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DS0PR03MB8272.namprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(376014)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; 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charset="utf-8" With lazy FPU removed, Xen does not need to touch the cr0.TS flag on context switch except when saving/restoring the FPU for a PV guest. Signed-off-by: Ross Lagerwall --- xen/arch/x86/cpu/common.c | 3 --- xen/arch/x86/hvm/emulate.c | 14 ++------------ xen/arch/x86/i387.c | 22 +++------------------- xen/arch/x86/include/asm/i387.h | 1 - xen/common/efi/runtime.c | 2 +- 5 files changed, 6 insertions(+), 36 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 5d0523a78b52..04a049f01c07 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -883,9 +883,6 @@ void cpu_init(void) /* Install correct page table. */ write_ptbase(current); =20 - /* Ensure FPU gets initialised for each domain. */ - stts(); - /* Reset debug registers: */ write_debugreg(0, 0); write_debugreg(1, 0); diff --git a/xen/arch/x86/hvm/emulate.c b/xen/arch/x86/hvm/emulate.c index 48c7320360c7..f3aae158e9f8 100644 --- a/xen/arch/x86/hvm/emulate.c +++ b/xen/arch/x86/hvm/emulate.c @@ -2527,14 +2527,8 @@ static int cf_check hvmemul_get_fpu( * Latch current register state so that we can back out changes * if needed (namely when a memory write fails after register state * has already been updated). - * NB: We don't really need the "enable" part of the called functi= on - * (->fpu_dirtied set implies CR0.TS clear), but the additional - * overhead should be low enough to not warrant introduction of yet - * another slightly different function. However, we need to undo t= he - * ->fpu_dirtied clearing the function does as well as the possible - * masking of all exceptions by FNSTENV.) */ - save_fpu_enable(); + vcpu_save_fpu(curr); if ( (fpu_ctxt->fcw & 0x3f) !=3D 0x3f ) { uint16_t fcw; @@ -2572,12 +2566,8 @@ static void cf_check hvmemul_put_fpu( * Latch current register state so that we can replace FIP/FDP/FOP * (which have values resulting from our own invocation of the FPU * instruction during emulation). - * NB: See also the comment in hvmemul_get_fpu(); we don't need to - * set ->fpu_dirtied here as it is going to be cleared below, and - * we also don't need to reload FCW as we're forcing full state to - * be reloaded anyway. */ - save_fpu_enable(); + vcpu_save_fpu(curr); =20 if ( boot_cpu_has(X86_FEATURE_FDP_EXCP_ONLY) && !(fpu_ctxt->fsw & ~fpu_ctxt->fcw & 0x003f) ) diff --git a/xen/arch/x86/i387.c b/xen/arch/x86/i387.c index 9acaaf4673df..336bc83b6e13 100644 --- a/xen/arch/x86/i387.c +++ b/xen/arch/x86/i387.c @@ -176,9 +176,6 @@ void vcpu_restore_fpu(struct vcpu *v) { ASSERT(!is_idle_vcpu(v)); =20 - /* Avoid recursion */ - clts(); - if ( cpu_has_xsave ) fpu_xrstor(v, XSTATE_ALL); else @@ -193,31 +190,18 @@ void vcpu_restore_fpu(struct vcpu *v) * On each context switch, save the necessary FPU info of VCPU being switc= h=20 * out. It dispatches saving operation based on CPU's capability. */ -static bool _vcpu_save_fpu(struct vcpu *v) +void vcpu_save_fpu(struct vcpu *v) { ASSERT(!is_idle_vcpu(v)); =20 /* This can happen, if a paravirtualised guest OS has set its CR0.TS. = */ - clts(); + if ( is_pv_vcpu(v) ) + clts(); =20 if ( cpu_has_xsave ) fpu_xsave(v); else fpu_fxsave(v); - - return true; -} - -void vcpu_save_fpu(struct vcpu *v) -{ - _vcpu_save_fpu(v); - stts(); -} - -void save_fpu_enable(void) -{ - if ( !_vcpu_save_fpu(current) ) - clts(); } =20 /* Initialize FPU's context save area */ diff --git a/xen/arch/x86/include/asm/i387.h b/xen/arch/x86/include/asm/i38= 7.h index fe5e4419b6f4..0717005d31f0 100644 --- a/xen/arch/x86/include/asm/i387.h +++ b/xen/arch/x86/include/asm/i387.h @@ -29,7 +29,6 @@ struct ix87_env { =20 void vcpu_restore_fpu(struct vcpu *v); void vcpu_save_fpu(struct vcpu *v); -void save_fpu_enable(void); int vcpu_init_fpu(struct vcpu *v); void vcpu_destroy_fpu(struct vcpu *v); =20 diff --git a/xen/common/efi/runtime.c b/xen/common/efi/runtime.c index 982e42e8f341..0f1cc765ec5e 100644 --- a/xen/common/efi/runtime.c +++ b/xen/common/efi/runtime.c @@ -94,7 +94,7 @@ struct efi_rs_state efi_rs_enter(void) return state; =20 state.cr3 =3D read_cr3(); - save_fpu_enable(); + vcpu_save_fpu(current); asm volatile ( "fnclex; fldcw %0" :: "m" (fcw) ); asm volatile ( "ldmxcsr %0" :: "m" (mxcsr) ); =20 --=20 2.53.0