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Tsirkin" , "Eduardo Habkost" , "Anthony PERARD" , xen-devel@lists.xenproject.org, "Thierry Escande" Message-Id: <20260313164649.794591-2-thierry.escande@vates.tech> In-Reply-To: <20260313164649.794591-1-thierry.escande@vates.tech> References: <20260313164649.794591-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.0118508a42d54da1a844b7f27097d1e0?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260313:md Date: Fri, 13 Mar 2026 16:47:07 +0000 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @mandrillapp.com) (identity thierry.escande@vates.tech) X-ZM-MESSAGEID: 1773420446149158500 Content-Type: text/plain; charset="utf-8" From: Alexey Gerasimenko This patch introduces support for ICH9 LPC PCI interrupt routing when running under Xen. This intercepts writes to the PIRQA-D routing registers and propagates routing changes to the Xen device model via xen_set_pci_link_route(). A major difference between i440 and Q35 is the number of PIRQ inputs and PIRQ routers (PCI IRQ links in terms of ACPI) available. i440 has 4 PCI interrupt links, while Q35 has 8 (PIRQA...PIRQH). Currently Xen has support for only 4 PCI links, so we describe only 4 of 8 PCI links in ACPI tables. Also, hvmloader disables PIRQ routing for PIRQE..PIRQH by writing 80h into corresponding PIRQ[n]_ROUT registers. All this PCI interrupt routing stuff largely concerns legacy mechanism from PIC era. It's hardly worth to extend number of PCI links supported as we normally deal with APIC mode and/or MSI interrupts. The only useful thing to do with PIRQE..PIRQH routing currently is to check if guest actually attempts to use it for some reason (despite ACPI PCI routing information provided). In this case, a warning is reported. This has been tested on Linux guests with noapic and pci=3Dnomsi kernel parameters set. Signed-off-by: Alexey Gerasimenko Signed-off-by: Thierry Escande --- hw/i386/pc_piix.c | 2 -- hw/i386/xen/xen-hvm.c | 38 ++++++++++++++++++++++++++++++++++++++ hw/isa/lpc_ich9.c | 16 +++++++++++++--- include/hw/xen/xen.h | 5 +++++ stubs/xen-hw-stub.c | 4 ++++ 5 files changed, 60 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 4d71e0d51a..a65e09e46c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -66,8 +66,6 @@ #include "hw/i386/acpi-build.h" #include "target/i386/cpu.h" =20 -#define XEN_IOAPIC_NUM_PIRQS 128ULL - static GlobalProperty pc_piix_compat_defaults[] =3D { { TYPE_RAMFB_DEVICE, "use-legacy-x86-rom", "true" }, { TYPE_VFIO_PCI_NOHOTPLUG, "use-legacy-x86-rom", "true" }, diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 67d3e836eb..2dba289e09 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -18,6 +18,7 @@ #include "hw/core/hw-error.h" #include "hw/i386/pc.h" #include "hw/core/irq.h" +#include "hw/southbridge/ich9.h" #include "hw/i386/apic-msidef.h" #include "hw/xen/xen-x86.h" #include "qemu/range.h" @@ -87,6 +88,43 @@ int xen_set_pci_link_route(uint8_t link, uint8_t irq) return xendevicemodel_set_pci_link_route(xen_dmod, xen_domid, link, ir= q); } =20 +void xen_ich9_pci_write_config_client(PCIDevice *pci_dev, uint32_t address= , uint32_t val, int len) +{ + static bool pirqe_f_warned =3D false; + int i; + + if (ranges_overlap(address, len, ICH9_LPC_PIRQA_ROUT, 4)) { + /* handle PIRQA..PIRQD routing */ + /* Scan for updates to PCI link routes (0x60-0x63). */ + for (i =3D 0; i < len; i++) { + uint8_t v =3D (val >> (8 * i)) & 0xff; + if (v & 0x80) { + v =3D 0; + } + v &=3D 0xf; + if (((address + i) >=3D ICH9_LPC_PIRQA_ROUT) && + ((address + i) <=3D ICH9_LPC_PIRQD_ROUT)) { + xen_set_pci_link_route(address + i - ICH9_LPC_PIRQA_ROUT, = v); + } + } + } else if (ranges_overlap(address, len, ICH9_LPC_PIRQE_ROUT, 4)) { + while (len--) { + if (range_covers_byte(ICH9_LPC_PIRQE_ROUT, 4, address) && + (val & 0x80) =3D=3D 0) { + /* print warning only once */ + if (!pirqe_f_warned) { + pirqe_f_warned =3D true; + warn_report("WARNING: guest domain attempted to use PI= RQ%c " + "routing which is not supported for Xen/Q3= 5 currently\n", + (char)(address - ICH9_LPC_PIRQE_ROUT + 'E'= )); + break; + } + } + address++, val >>=3D 8; + } + } +} + int xen_is_pirq_msi(uint32_t msi_data) { /* If vector is 0, the msi is remapped into a pirq, passed as diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 51dc680029..8c627f0734 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -46,8 +46,10 @@ #include "hw/acpi/ich9_timer.h" #include "hw/pci/pci_bus.h" #include "hw/core/qdev-properties.h" +#include "hw/xen/xen.h" #include "system/runstate.h" #include "system/system.h" +#include "system/xen.h" #include "hw/core/cpu.h" #include "hw/nvram/fw_cfg.h" #include "qemu/cutils.h" @@ -569,6 +571,9 @@ static void ich9_lpc_config_write(PCIDevice *d, ICH9LPCState *lpc =3D ICH9_LPC_DEVICE(d); uint32_t rcba_old =3D pci_get_long(d->config + ICH9_LPC_RCBA); =20 + if (xen_enabled()){ + xen_ich9_pci_write_config_client(d, addr, val, len); + } pci_default_write_config(d, addr, val, len); if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { @@ -762,9 +767,14 @@ static void ich9_lpc_realize(PCIDevice *d, Error **err= p) irq =3D object_property_get_uint(OBJECT(&lpc->rtc), "irq", &error_fata= l); isa_connect_gpio_out(ISA_DEVICE(&lpc->rtc), 0, irq); =20 - pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS); - pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq); - pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq); + if (xen_enabled()) { + pci_bus_irqs(pci_bus, xen_intx_set_irq, d, XEN_IOAPIC_NUM_PIRQS); + pci_bus_map_irqs(pci_bus, xen_pci_slot_get_pirq); + } else { + pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS); + pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq); + pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq); + } =20 ich9_lpc_pm_init(lpc); } diff --git a/include/hw/xen/xen.h b/include/hw/xen/xen.h index e94c6e5a31..910289b54d 100644 --- a/include/hw/xen/xen.h +++ b/include/hw/xen/xen.h @@ -24,6 +24,8 @@ #define __XEN_INTERFACE_VERSION__ 0x00040e00 #endif =20 +#define XEN_IOAPIC_NUM_PIRQS 128ULL + /* xen-machine.c */ enum xen_mode { XEN_DISABLED =3D 0, /* xen support disabled (default) */ @@ -39,6 +41,9 @@ extern bool xen_is_stubdomain; int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num); int xen_set_pci_link_route(uint8_t link, uint8_t irq); void xen_intx_set_irq(void *opaque, int irq_num, int level); +void xen_ich9_pci_write_config_client(PCIDevice *pci_dev, + uint32_t address, uint32_t val, + int len); void xen_hvm_inject_msi(uint64_t addr, uint32_t data); int xen_is_pirq_msi(uint32_t msi_data); =20 diff --git a/stubs/xen-hw-stub.c b/stubs/xen-hw-stub.c index 6cf0e9a4c1..a74209d01e 100644 --- a/stubs/xen-hw-stub.c +++ b/stubs/xen-hw-stub.c @@ -24,6 +24,10 @@ int xen_set_pci_link_route(uint8_t link, uint8_t irq) return -1; } =20 +void xen_ich9_pci_write_config_client(PCIDevice *pci_dev, uint32_t address= , uint32_t val, int len) +{ +} + int xen_is_pirq_msi(uint32_t msi_data) { return 0; --=20 2.51.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Mon Mar 23 19:52:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Tsirkin" , "Eduardo Habkost" , "Anthony PERARD" , xen-devel@lists.xenproject.org Message-Id: <20260313164649.794591-3-thierry.escande@vates.tech> In-Reply-To: <20260313164649.794591-1-thierry.escande@vates.tech> References: <20260313164649.794591-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.9da3346c299f433282428ef7ed5b675a?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260313:md Date: Fri, 13 Mar 2026 16:47:11 +0000 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity thierry.escande@vates.tech) (identity @mandrillapp.com) X-ZM-MESSAGEID: 1773420448141158500 Content-Type: text/plain; charset="utf-8" This patch intializes HVM pc machine in pc_q35_init() if Xen support is enabled. As done for i440 machine, this also cleanups unrealized flash devices. See commit dd29b5c30c (xen: cleanup unrealized flash devices). Signed-off-by: Thierry Escande --- hw/i386/pc_q35.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index cb23322f5a..89dd736d95 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -35,8 +35,10 @@ #include "hw/core/loader.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/rtc/mc146818rtc.h" +#include "hw/xen/xen-x86.h" #include "system/tcg.h" #include "system/kvm.h" +#include "system/xen.h" #include "hw/i386/kvm/clock.h" #include "hw/pci-host/q35.h" #include "hw/pci/pcie_port.h" @@ -190,6 +192,10 @@ static void pc_q35_init(MachineState *machine) x86ms->below_4g_mem_size =3D machine->ram_size; } =20 + if (xen_enabled()) { + xen_hvm_init_pc(pcms, &machine->ram); + } + pc_machine_init_sgx_epc(pcms); x86_cpus_init(x86ms, pcmc->default_cpu_version); =20 @@ -206,7 +212,11 @@ static void pc_q35_init(MachineState *machine) =20 /* allocate ram and load rom/bios */ memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); - pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); + if (!xen_enabled()) { + pc_memory_init(pcms, system_memory, pci_memory, pci_hole64_size); + } else { + pc_system_flash_cleanup_unused(pcms); + } =20 object_property_add_child(OBJECT(machine), "q35", phb); object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, --=20 2.51.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Mon Mar 23 19:52:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass header.i=thierry.escande@vates.tech; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=vates.tech ARC-Seal: i=1; a=rsa-sha256; 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b=GX5lVS29RUTKr/vbIVOLwFzgCUUFqxSTOIUfJoV4hu8dmQbu4bIFWZvsVBzTHy705 c7CbqOt5zCXc+RADwUEFKsp7IhgxU4LszeIRGWb04GkkMdzeMtWgY3BUhlKenWhGU+ ckx68gKYyJvt/kvLkjh7u432Br5QvCD1DnZAM8zIYYHVDaAtoccCow8c1w24rTJEc+ L1GTcfQu567K9NAIDHe1cuC14Sn2Zsx0fQIQuEIgE0X+1ME6n5Y6Hwni4cg6qzidNe MCD3mW3jj4q8jnINAFrR1TE/7MYUmQNDgZvyairJ0wY4g0Vj460xeC+m9cktaHeHGM KlvQMXMDfLcHg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1773420436; x=1773680936; i=thierry.escande@vates.tech; bh=tBqT15VgX6aHPkE4gLQnkO0oJx1PmUhyS6eAmAg6IcA=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=IKvtfnlQuiiJnkVOazyhGMevNQOw1IbmwXhVJ+rkVMRg8YN18RLN3qm6mN6H5FJzo GVjDkvZRx8JWrq2jL4IiuPKUTWsrmYgO8WeaAV+6wt9Gm5paIBDh9X6u/Pjo5TVVeQ FnHiM6+siNRiJgZ3bC+N4RYkY2aWkPXBt0FWc0woKXD4IlMuE2iJICHJtMM5jnDor7 9xaMX12kSskk4dQyohROhI5GC4IIbnWIDsk3fMl8ConzdyjBI9hgOBpjXYOkFsm++L e6febQyGMYropNNEGkfGa5XnPI261xljXJ+gg8hoxgEDX/hyYIi/qVOvBu0QH5zYBY kv62fwCxdzYOA== From: "Thierry Escande" Subject: =?utf-8?Q?[PATCH=203/4]=20q35:=20Fix=20incorrect=20values=20for=20PCIEXBAR=20masks?= X-Mailer: git-send-email 2.51.0 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1773420435540 To: qemu-devel@nongnu.org Cc: "Alexey Gerasimenko" , "Paolo Bonzini" , "Richard Henderson" , "Michael S. Tsirkin" , "Eduardo Habkost" , "Anthony PERARD" , xen-devel@lists.xenproject.org, "Thierry Escande" Message-Id: <20260313164649.794591-4-thierry.escande@vates.tech> In-Reply-To: <20260313164649.794591-1-thierry.escande@vates.tech> References: <20260313164649.794591-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.e6b761e1b1f7448687105735495f9699?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260313:md Date: Fri, 13 Mar 2026 16:47:16 +0000 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity thierry.escande@vates.tech) (identity @mandrillapp.com) X-ZM-MESSAGEID: 1773420455835154100 Content-Type: text/plain; charset="utf-8" From: Alexey Gerasimenko There are two small issues in PCIEXBAR address mask handling: - wrong bit positions for address mask bits (see PCIEXBAR description in Q35 datasheet) - incorrect usage of 64ADR_MASK Due to this, attempting to write a valid PCIEXBAR address may cause it to shift to another address, causing memory layout corruption where emulated MMIO regions may overlap real (passed through) MMIO ranges. Fix this by providing correct values. Signed-off-by: Alexey Gerasimenko Signed-off-by: Thierry Escande --- hw/pci-host/q35.c | 6 +++--- include/hw/pci-host/q35.h | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index e85e4227b3..7368e3c598 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -306,12 +306,12 @@ static void mch_update_pciexbar(MCHPCIState *mch) break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: length =3D 128 * 1024 * 1024; - addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | - MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; + addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK; break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: length =3D 64 * 1024 * 1024; - addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; + addr_mask |=3D MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK | + MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK; break; case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: qemu_log_mask(LOG_GUEST_ERROR, "Q35: Reserved PCIEXBAR LENGTH\n"); diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index ddafc3f2e3..f31a71010b 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -100,8 +100,8 @@ struct Q35PCIHost { #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xb0000000 #define MCH_HOST_BRIDGE_PCIEXBAR_MAX (0x10000000) /* 256M */ #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 28) -#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26)) -#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25)) +#define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 27)) +#define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 26)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1)) #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1)) --=20 2.51.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech From nobody Mon Mar 23 19:52:07 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Tsirkin" , "Eduardo Habkost" , "Anthony PERARD" , xen-devel@lists.xenproject.org Message-Id: <20260313164649.794591-5-thierry.escande@vates.tech> In-Reply-To: <20260313164649.794591-1-thierry.escande@vates.tech> References: <20260313164649.794591-1-thierry.escande@vates.tech> X-Native-Encoded: 1 X-Report-Abuse: =?UTF-8?Q?Please=20forward=20a=20copy=20of=20this=20message,=20including=20all=20headers,=20to=20abuse@mandrill.com.=20You=20can=20also=20report=20abuse=20here:=20https://mandrillapp.com/contact/abuse=3Fid=3D30504962.bf408e4098ba45c6b365cef3c2c3e264?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20260313:md Date: Fri, 13 Mar 2026 16:47:20 +0000 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @mandrillapp.com) (identity thierry.escande@vates.tech) X-ZM-MESSAGEID: 1773420470176158500 Content-Type: text/plain; charset="utf-8" This change allows to read and write to the extended config space of PCI Express devices by setting the size limit to 4096 bytes. The size limit remains 256 bytes for non PCIe devices. Signed-off-by: Thierry Escande --- hw/xen/xen-hvm-common.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c index 62d88804c4..15090d77cf 100644 --- a/hw/xen/xen-hvm-common.c +++ b/hw/xen/xen-hvm-common.c @@ -396,6 +396,7 @@ static void cpu_ioreq_config(XenIOState *state, ioreq_t= *req) { uint32_t sbdf =3D req->addr >> 32; uint32_t reg =3D req->addr; + uint32_t limit; XenPciDevice *xendev; =20 if (req->size !=3D sizeof(uint8_t) && req->size !=3D sizeof(uint16_t) = && @@ -412,10 +413,12 @@ static void cpu_ioreq_config(XenIOState *state, ioreq= _t *req) continue; } =20 + limit =3D pci_is_express(xendev->pci_dev) ? + PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE; if (!req->data_is_ptr) { if (req->dir =3D=3D IOREQ_READ) { req->data =3D pci_host_config_read_common( - xendev->pci_dev, reg, PCI_CONFIG_SPACE_SIZE, + xendev->pci_dev, reg, limit, req->size); trace_cpu_ioreq_config_read(req, xendev->sbdf, reg, req->size, req->data); @@ -423,7 +426,7 @@ static void cpu_ioreq_config(XenIOState *state, ioreq_t= *req) trace_cpu_ioreq_config_write(req, xendev->sbdf, reg, req->size, req->data); pci_host_config_write_common( - xendev->pci_dev, reg, PCI_CONFIG_SPACE_SIZE, + xendev->pci_dev, reg, limit, req->data, req->size); } } else { @@ -431,7 +434,7 @@ static void cpu_ioreq_config(XenIOState *state, ioreq_t= *req) =20 if (req->dir =3D=3D IOREQ_READ) { tmp =3D pci_host_config_read_common( - xendev->pci_dev, reg, PCI_CONFIG_SPACE_SIZE, + xendev->pci_dev, reg, limit, req->size); trace_cpu_ioreq_config_read(req, xendev->sbdf, reg, req->size, tmp); @@ -441,7 +444,7 @@ static void cpu_ioreq_config(XenIOState *state, ioreq_t= *req) trace_cpu_ioreq_config_write(req, xendev->sbdf, reg, req->size, tmp); pci_host_config_write_common( - xendev->pci_dev, reg, PCI_CONFIG_SPACE_SIZE, + xendev->pci_dev, reg, limit, tmp, req->size); } } --=20 2.51.0 -- Thierry Escande | Vates XCP-ng Developer XCP-ng & Xen Orchestra - Vates solutions web: https://vates.tech