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charset="utf-8" struct cpuinfo_x86 .x86 =3D> .family .x86_vendor =3D> .vendor .x86_model =3D> .model .x86_mask =3D> .stepping No functional change. This work is part of making Xen safe for Intel family 18/19. Signed-off-by: Kevin Lampis Acked-by: Jan Beulich --- Changes in v2: - Switch uint8_t to unsigned int in vpmu_arch_initialise() - Switch int to unsigned int in vpmu_init() - Remove XXX comments --- xen/arch/x86/cpu/centaur.c | 4 ++-- xen/arch/x86/cpu/hygon.c | 4 ++-- xen/arch/x86/cpu/intel_cacheinfo.c | 6 +++--- xen/arch/x86/cpu/mtrr/generic.c | 6 +++--- xen/arch/x86/cpu/mwait-idle.c | 4 ++-- xen/arch/x86/cpu/vpmu.c | 4 ++-- xen/arch/x86/cpu/vpmu_amd.c | 6 +++--- xen/arch/x86/cpu/vpmu_intel.c | 4 ++-- 8 files changed, 19 insertions(+), 19 deletions(-) diff --git a/xen/arch/x86/cpu/centaur.c b/xen/arch/x86/cpu/centaur.c index d2e7c8ec99..9123b05dc1 100644 --- a/xen/arch/x86/cpu/centaur.c +++ b/xen/arch/x86/cpu/centaur.c @@ -41,7 +41,7 @@ static void init_c3(struct cpuinfo_x86 *c) } } =20 - if (c->x86 =3D=3D 0x6 && c->x86_model >=3D 0xf) { + if (c->family =3D=3D 0x6 && c->model >=3D 0xf) { c->x86_cache_alignment =3D c->x86_clflush_size * 2; __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); } @@ -52,7 +52,7 @@ static void init_c3(struct cpuinfo_x86 *c) =20 static void cf_check init_centaur(struct cpuinfo_x86 *c) { - if (c->x86 =3D=3D 6) + if (c->family =3D=3D 6) init_c3(c); } =20 diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c index b99d83ed4d..7a9fc25d31 100644 --- a/xen/arch/x86/cpu/hygon.c +++ b/xen/arch/x86/cpu/hygon.c @@ -41,12 +41,12 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c) =20 /* Probe for NSCB on Zen2 CPUs when not virtualised */ if (!cpu_has_hypervisor && !cpu_has_nscb && c =3D=3D &boot_cpu_data && - c->x86 =3D=3D 0x18) + c->family =3D=3D 0x18) detect_zen2_null_seg_behaviour(); =20 /* * TODO: Check heuristic safety with Hygon first - if (c->x86 =3D=3D 0x18) + if (c->family =3D=3D 0x18) amd_init_spectral_chicken(); */ =20 diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_ca= cheinfo.c index e88faa7545..a81d0764fb 100644 --- a/xen/arch/x86/cpu/intel_cacheinfo.c +++ b/xen/arch/x86/cpu/intel_cacheinfo.c @@ -168,15 +168,15 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves =3D=3D 0 || c->x86 =3D=3D 15) && c->cpuid_level > 1= && - c->x86_vendor !=3D X86_VENDOR_SHANGHAI) + if ((num_cache_leaves =3D=3D 0 || c->family =3D=3D 15) && c->cpuid_level = > 1 && + c->vendor !=3D X86_VENDOR_SHANGHAI) { /* supports eax=3D2 call */ unsigned int i, j, n, regs[4]; unsigned char *dp =3D (unsigned char *)regs; int only_trace =3D 0; =20 - if (num_cache_leaves !=3D 0 && c->x86 =3D=3D 15) + if (num_cache_leaves !=3D 0 && c->family =3D=3D 15) only_trace =3D 1; =20 /* Number of times to iterate */ diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generi= c.c index c587e9140e..190be7f1b4 100644 --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -218,9 +218,9 @@ static void __init print_mtrr_state(const char *level) printk("%s %u disabled\n", level, i); } =20 - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD && - boot_cpu_data.x86 >=3D 0xf) || - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) { + if ((boot_cpu_data.vendor =3D=3D X86_VENDOR_AMD && + boot_cpu_data.family >=3D 0xf) || + boot_cpu_data.vendor =3D=3D X86_VENDOR_HYGON) { uint64_t syscfg, tom2; =20 rdmsrl(MSR_K8_SYSCFG, syscfg); diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index 5962ec1db9..6776eeb9ac 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1637,7 +1637,7 @@ static int __init mwait_idle_probe(void) lapic_timer_reliable_states =3D LAPIC_TIMER_ALWAYS_RELIABLE; =20 pr_debug(PREFIX "v" MWAIT_IDLE_VERSION " model %#x\n", - boot_cpu_data.x86_model); + boot_cpu_data.model); =20 pr_debug(PREFIX "lapic_timer_reliable_states %#x\n", lapic_timer_reliable_states); @@ -1816,7 +1816,7 @@ bool __init mwait_pc10_supported(void) { unsigned int ecx, edx, dummy; =20 - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || + if (boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || !cpu_has_monitor || boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) return false; diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c index c28192ea26..470f5ec98d 100644 --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -398,7 +398,7 @@ int vpmu_load(struct vcpu *v, bool from_guest) static int vpmu_arch_initialise(struct vcpu *v) { struct vpmu_struct *vpmu =3D vcpu_vpmu(v); - uint8_t vendor =3D current_cpu_data.x86_vendor; + unsigned int vendor =3D current_cpu_data.vendor; int ret; =20 BUILD_BUG_ON(sizeof(struct xen_pmu_intel_ctxt) > XENPMU_CTXT_PAD_SZ); @@ -815,7 +815,7 @@ static struct notifier_block cpu_nfb =3D { =20 static int __init cf_check vpmu_init(void) { - int vendor =3D current_cpu_data.x86_vendor; + unsigned int vendor =3D current_cpu_data.vendor; const struct arch_vpmu_ops *ops =3D NULL; =20 if ( !opt_vpmu_enabled ) diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c index d1f6bd5495..943a0f4ebe 100644 --- a/xen/arch/x86/cpu/vpmu_amd.c +++ b/xen/arch/x86/cpu/vpmu_amd.c @@ -532,7 +532,7 @@ static const struct arch_vpmu_ops *__init common_init(v= oid) if ( !num_counters ) { printk(XENLOG_WARNING "VPMU: Unsupported CPU family %#x\n", - current_cpu_data.x86); + current_cpu_data.family); return ERR_PTR(-EINVAL); } =20 @@ -557,7 +557,7 @@ static const struct arch_vpmu_ops *__init common_init(v= oid) =20 const struct arch_vpmu_ops *__init amd_vpmu_init(void) { - switch ( current_cpu_data.x86 ) + switch ( current_cpu_data.family ) { case 0x15: case 0x17: @@ -585,7 +585,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void) =20 const struct arch_vpmu_ops *__init hygon_vpmu_init(void) { - switch ( current_cpu_data.x86 ) + switch ( current_cpu_data.family ) { case 0x18: num_counters =3D F15H_NUM_COUNTERS; diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 1e3b06ef8e..ed9f62b936 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -917,7 +917,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) return ERR_PTR(-EINVAL); } =20 - if ( current_cpu_data.x86 !=3D 6 ) + if ( current_cpu_data.family !=3D 6 ) { printk(XENLOG_WARNING "VPMU: only family 6 is supported\n"); return ERR_PTR(-EINVAL); @@ -958,7 +958,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt; =20 /* TODO: It's clearly incorrect for this to quirk all Intel Fam6 CPUs.= */ - pmc_quirk =3D current_cpu_data.x86 =3D=3D 6; + pmc_quirk =3D current_cpu_data.family =3D=3D 6; =20 if ( sizeof(struct xen_pmu_data) + sizeof(uint64_t) * fixed_pmc_cnt + sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt > PAGE_SIZE ) --=20 2.51.1