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charset="utf-8" The lr_mask bitmap tracks which List Registers (LRs) are in use for virtual interrupt injection. Previously, lr_mask always used uint64_t (8 bytes) to support the maximum number of LRs across both GIC versions. However, GICv2 and GICv3 have different hardware limits: - GICv3: ICH_VTR_EL2[3:0] encodes LR count -> max 16 LRs (4 bits) - GICv2: GICH_VTR[5:0] encodes LR count -> max 64 LRs (6 bits) This patch introduces conditional compilation to optimize lr_mask size: - CONFIG_GICV3=3Dy: Use uint16_t (2 bytes) - sufficient for 16 LRs - CONFIG_GICV3=3Dn: Use uint64_t (8 bytes) - required for 64 LRs With this, parameter 'lr' in gicv3_ich_read_lr(), gicv3_ich_write_lr() cannot have a value > 15. Thus, it should not possible to hit the BUG() in the default case. Signed-off-by: Ayan Kumar Halder --- xen/arch/arm/gic-vgic.c | 11 ++++++++++- xen/arch/arm/gic.c | 10 +++++++++- xen/arch/arm/include/asm/domain.h | 4 ++++ xen/arch/arm/include/asm/gic.h | 8 ++++++++ 4 files changed, 31 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch/arm/gic-vgic.c index ea48c5375a..80d3beb225 100644 --- a/xen/arch/arm/gic-vgic.c +++ b/xen/arch/arm/gic-vgic.c @@ -16,8 +16,13 @@ #include #include =20 +#ifdef CONFIG_GICV3 #define lr_all_full() \ - (this_cpu(lr_mask) =3D=3D (-1ULL >> (64 - gic_get_nr_lrs()))) + (this_cpu(lr_mask) =3D=3D ((uint16_t)-1 >> (16 - gic_get_nr_lrs()))) +#else +#define lr_all_full() \ + (this_cpu(lr_mask) =3D=3D ((uint64_t)-1 >> (64 - gic_get_nr_lrs()))) +#endif =20 #undef GIC_DEBUG =20 @@ -102,7 +107,11 @@ static unsigned int gic_find_unused_lr(struct vcpu *v, struct pending_irq *p, unsigned int lr) { +#ifdef CONFIG_GICV3 + uint16_t *lr_mask =3D &this_cpu(lr_mask); +#else uint64_t *lr_mask =3D &this_cpu(lr_mask); +#endif =20 ASSERT(spin_is_locked(&v->arch.vgic.lock)); =20 diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index ee75258fc3..e1121a5bb3 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -29,7 +29,11 @@ #include #include =20 +#ifdef CONFIG_GICV3 +DEFINE_PER_CPU(uint16_t, lr_mask); +#else DEFINE_PER_CPU(uint64_t, lr_mask); +#endif =20 #undef GIC_DEBUG =20 @@ -48,7 +52,7 @@ void register_gic_ops(const struct gic_hw_operations *ops) =20 static void clear_cpu_lr_mask(void) { - this_cpu(lr_mask) =3D 0ULL; + this_cpu(lr_mask) =3D 0; } =20 enum gic_version gic_hw_version(void) @@ -382,7 +386,11 @@ static void maintenance_interrupt(int irq, void *dev_i= d) =20 void gic_dump_info(struct vcpu *v) { +#ifdef CONFIG_GICV3 + printk("GICH_LRs (vcpu %d) mask=3D%"PRIx16"\n", v->vcpu_id, v->arch.lr= _mask); +#else printk("GICH_LRs (vcpu %d) mask=3D%"PRIx64"\n", v->vcpu_id, v->arch.lr= _mask); +#endif gic_hw_ops->dump_state(v); } =20 diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/d= omain.h index 758ad807e4..8654ef89ef 100644 --- a/xen/arch/arm/include/asm/domain.h +++ b/xen/arch/arm/include/asm/domain.h @@ -228,7 +228,11 @@ struct arch_vcpu =20 /* Holds gic context data */ union gic_state_data gic; +#ifdef CONFIG_GICV3 + uint16_t lr_mask; +#else uint64_t lr_mask; +#endif =20 struct vgic_cpu vgic; =20 diff --git a/xen/arch/arm/include/asm/gic.h b/xen/arch/arm/include/asm/gic.h index 8e713aa477..e1559ec98c 100644 --- a/xen/arch/arm/include/asm/gic.h +++ b/xen/arch/arm/include/asm/gic.h @@ -237,7 +237,15 @@ enum gic_version { GIC_V3, }; =20 +/* + * GICv3 supports up to 16 LRs (4 bits in ICH_VTR_EL2), can use uint16_t + * GICv2 supports up to 64 LRs (6 bits in GICH_VTR), requires uint64_t + */ +#ifdef CONFIG_GICV3 +DECLARE_PER_CPU(uint16_t, lr_mask); +#else DECLARE_PER_CPU(uint64_t, lr_mask); +#endif =20 extern enum gic_version gic_hw_version(void); =20 --=20 2.25.1