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charset="utf-8" struct cpuinfo_x86 .x86 =3D> .family .x86_vendor =3D> .vendor .x86_model =3D> .model .x86_mask =3D> .stepping No functional change. This work is part of making Xen safe for Intel family 18/19. Signed-off-by: Kevin Lampis --- Changes since v1: - mcheck_init() check for family !=3D 5 instead of 6 and 15 - mce_firstbank() match vfm range - mce_is_broadcast() add vendor check as well as >=3D INTEL_CORE_YONAH This supersedes the individual posting https://lore.kernel.org/xen-devel/20260302191900.672460-1-kevin.lampis@citr= ix.com/ --- xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 2 +- xen/arch/x86/cpu/mcheck/mcaction.c | 2 +- xen/arch/x86/cpu/mcheck/mce.c | 35 +++++++++++--------------- xen/arch/x86/cpu/mcheck/mce.h | 2 +- xen/arch/x86/cpu/mcheck/mce_amd.c | 16 ++++++------ xen/arch/x86/cpu/mcheck/mce_intel.c | 5 +--- xen/arch/x86/cpu/mcheck/non-fatal.c | 2 +- xen/arch/x86/cpu/mcheck/vmce.c | 8 +++--- 8 files changed, 32 insertions(+), 40 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c b/xen/arch/x86/cpu/mche= ck/amd_nonfatal.c index 7d48c9ab5f..fb52639e13 100644 --- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c +++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c @@ -191,7 +191,7 @@ static void cf_check mce_amd_work_fn(void *data) =20 void __init amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c) { - if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) + if (!(c->vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) return; =20 /* Assume we are on K8 or newer AMD or Hygon CPU here */ diff --git a/xen/arch/x86/cpu/mcheck/mcaction.c b/xen/arch/x86/cpu/mcheck/m= caction.c index bf7a0de965..236424569a 100644 --- a/xen/arch/x86/cpu/mcheck/mcaction.c +++ b/xen/arch/x86/cpu/mcheck/mcaction.c @@ -101,7 +101,7 @@ mc_memerr_dhandler(struct mca_binfo *binfo, * not always precise. In that case, fallback to broa= dcast. */ global->mc_domid !=3D bank->mc_domid || - (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + (boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && (!(global->mc_gstatus & MCG_STATUS_LMCE) || !(d->vcpu[mc_vcpuid]->arch.vmce.mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN))) ) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 9a91807cfb..901a71157a 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -23,6 +23,7 @@ #include #include #include +#include =20 #include "mce.h" #include "barrier.h" @@ -334,7 +335,7 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks= *bankmask, mca_init_global(mc_flags, mig); /* A hook here to get global extended msrs */ if ( IS_ENABLED(CONFIG_INTEL) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL ) intel_get_extended_msrs(mig, mci); } } @@ -564,8 +565,7 @@ bool mce_available(const struct cpuinfo_x86 *c) */ unsigned int mce_firstbank(struct cpuinfo_x86 *c) { - return c->x86 =3D=3D 6 && - c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->x86_model < 0x1a; + return c->vfm >=3D INTEL_PENTIUM_PRO && c->vfm < INTEL_NEHALEM_EP; } =20 static int show_mca_info(int inited, struct cpuinfo_x86 *c) @@ -596,7 +596,7 @@ static int show_mca_info(int inited, struct cpuinfo_x86= *c) case mcheck_amd_famXX: case mcheck_hygon: printk("%s%s Fam%xh machine check reporting enabled\n", - prefix, type_str[inited], c->x86); + prefix, type_str[inited], c->family); break; =20 case mcheck_none: @@ -766,7 +766,7 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) else if ( cpu_bank_alloc(cpu) ) panic("Insufficient memory for MCE bank allocations\n"); =20 - switch ( c->x86_vendor ) + switch ( c->vendor ) { #ifdef CONFIG_AMD case X86_VENDOR_AMD: @@ -777,13 +777,8 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) =20 #ifdef CONFIG_INTEL case X86_VENDOR_INTEL: - switch ( c->x86 ) - { - case 6: - case 15: + if ( c->family !=3D 5 ) inited =3D intel_mcheck_init(c, bsp); - break; - } break; #endif =20 @@ -882,7 +877,7 @@ static void x86_mcinfo_apei_save( memset(&m, 0, sizeof(struct mce)); =20 m.cpu =3D mc_global->mc_coreid; - m.cpuvendor =3D xen2linux_vendor(boot_cpu_data.x86_vendor); + m.cpuvendor =3D xen2linux_vendor(boot_cpu_data.vendor); m.cpuid =3D cpuid_eax(1); m.socketid =3D mc_global->mc_socketid; m.apicid =3D mc_global->mc_apicid; @@ -983,10 +978,10 @@ static void cf_check __maybe_unused do_mc_get_cpu_inf= o(void *v) &xcp->mc_apicid, &xcp->mc_ncores, &xcp->mc_ncores_active, &xcp->mc_nthreads); xcp->mc_cpuid_level =3D c->cpuid_level; - xcp->mc_family =3D c->x86; - xcp->mc_vendor =3D xen2linux_vendor(c->x86_vendor); - xcp->mc_model =3D c->x86_model; - xcp->mc_step =3D c->x86_mask; + xcp->mc_family =3D c->family; + xcp->mc_vendor =3D xen2linux_vendor(c->vendor); + xcp->mc_model =3D c->model; + xcp->mc_step =3D c->stepping; xcp->mc_cache_size =3D c->x86_cache_size; xcp->mc_cache_alignment =3D c->x86_cache_alignment; memcpy(xcp->mc_vendorid, c->x86_vendor_id, sizeof xcp->mc_vendorid); @@ -1142,7 +1137,7 @@ static bool __maybe_unused x86_mc_msrinject_verify(st= ruct xen_mc_msrinject *mci) =20 if ( IS_MCA_BANKREG(reg, mci->mcinj_cpunr) ) { - if ( c->x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( c->vendor =3D=3D X86_VENDOR_AMD ) { /* * On AMD we can set MCi_STATUS_WREN in the @@ -1177,15 +1172,15 @@ static bool __maybe_unused x86_mc_msrinject_verify(= struct xen_mc_msrinject *mci) case MSR_F10_MC4_MISC1: case MSR_F10_MC4_MISC2: case MSR_F10_MC4_MISC3: - if ( c->x86_vendor !=3D X86_VENDOR_AMD ) + if ( c->vendor !=3D X86_VENDOR_AMD ) reason =3D "only supported on AMD"; - else if ( c->x86 < 0x10 ) + else if ( c->family < 0x10 ) reason =3D "only supported on AMD Fam10h+"; break; =20 /* MSRs that the HV will take care of */ case MSR_K8_HWCR: - if ( c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( c->vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) reason =3D "HV will operate HWCR"; else reason =3D "only supported on AMD or Hygon"; diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 920b075355..3b61b12487 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -137,7 +137,7 @@ void x86_mcinfo_dump(struct mc_info *mi); =20 static inline int mce_vendor_bank_msr(const struct vcpu *v, uint32_t msr) { - switch (boot_cpu_data.x86_vendor) { + switch (boot_cpu_data.vendor) { case X86_VENDOR_INTEL: if (msr >=3D MSR_IA32_MC0_CTL2 && msr < MSR_IA32_MCx_CTL2(v->arch.vmce.mcg_cap & MCG_CAP_COUNT) ) diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mc= e_amd.c index 25c29eb3d2..2d17832d9c 100644 --- a/xen/arch/x86/cpu/mcheck/mce_amd.c +++ b/xen/arch/x86/cpu/mcheck/mce_amd.c @@ -160,17 +160,17 @@ mcequirk_lookup_amd_quirkdata(const struct cpuinfo_x8= 6 *c) { unsigned int i; =20 - BUG_ON(c->x86_vendor !=3D X86_VENDOR_AMD); + BUG_ON(c->vendor !=3D X86_VENDOR_AMD); =20 for ( i =3D 0; i < ARRAY_SIZE(mce_amd_quirks); i++ ) { - if ( c->x86 !=3D mce_amd_quirks[i].cpu_family ) + if ( c->family !=3D mce_amd_quirks[i].cpu_family ) continue; if ( (mce_amd_quirks[i].cpu_model !=3D ANY) && - (mce_amd_quirks[i].cpu_model !=3D c->x86_model) ) + (mce_amd_quirks[i].cpu_model !=3D c->model) ) continue; if ( (mce_amd_quirks[i].cpu_stepping !=3D ANY) && - (mce_amd_quirks[i].cpu_stepping !=3D c->x86_mask) ) + (mce_amd_quirks[i].cpu_stepping !=3D c->stepping) ) continue; return mce_amd_quirks[i].quirk; } @@ -291,13 +291,13 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp) uint32_t i; enum mcequirk_amd_flags quirkflag =3D 0; =20 - if ( c->x86_vendor !=3D X86_VENDOR_HYGON ) + if ( c->vendor !=3D X86_VENDOR_HYGON ) quirkflag =3D mcequirk_lookup_amd_quirkdata(c); =20 /* Assume that machine check support is available. * The minimum provided support is at least the K8. */ if ( bsp ) - mce_handler_init(c->x86 =3D=3D 0xf ? &k8_callbacks : &k10_callback= s); + mce_handler_init(c->family =3D=3D 0xf ? &k8_callbacks : &k10_callb= acks); =20 for ( i =3D 0; i < this_cpu(nr_mce_banks); i++ ) { @@ -311,7 +311,7 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp) } } =20 - if ( c->x86 =3D=3D 0xf ) + if ( c->family =3D=3D 0xf ) return mcheck_amd_k8; =20 if ( quirkflag =3D=3D MCEQUIRK_F10_GART ) @@ -337,6 +337,6 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp) ppin_msr =3D MSR_AMD_PPIN; } =20 - return c->x86_vendor =3D=3D X86_VENDOR_HYGON ? + return c->vendor =3D=3D X86_VENDOR_HYGON ? mcheck_hygon : mcheck_amd_famXX; } diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/= mce_intel.c index 839a0e5ba9..4d6b7d588e 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -711,10 +711,7 @@ static bool mce_is_broadcast(struct cpuinfo_x86 *c) * DisplayFamily_DisplayModel encoding of 06H_EH and above, * a MCA signal is broadcast to all logical processors in the system */ - if ( c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->x86 =3D=3D 6 && - c->x86_model >=3D 0xe ) - return true; - return false; + return c->vendor =3D=3D X86_VENDOR_INTEL && c->vfm >=3D INTEL_CORE_YON= AH; } =20 static bool intel_enable_lmce(void) diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/= non-fatal.c index a9ee9bb94f..4e7c64abef 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -23,7 +23,7 @@ static int __init cf_check init_nonfatal_mce_checker(void) /* * Check for non-fatal errors every MCE_RATE s */ - switch (c->x86_vendor) { + switch (c->vendor) { #ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 1a7e92506a..84776aeec8 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -45,7 +45,7 @@ void vmce_init_vcpu(struct vcpu *v) int i; =20 /* global MCA MSRs init */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL ) v->arch.vmce.mcg_cap =3D INTEL_GUEST_MCG_CAP; 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charset="utf-8" struct cpuinfo_x86 .x86 =3D> .family .x86_vendor =3D> .vendor .x86_model =3D> .model .x86_mask =3D> .stepping No functional change. This work is part of making Xen safe for Intel family 18/19. Signed-off-by: Kevin Lampis Acked-by: Jan Beulich --- Inside do_get_hw_residencies() there is an explicit check for `c->family !=3D 6` Do we need to add family 18/19 support here? --- xen/arch/x86/acpi/cpu_idle.c | 20 ++++++++++---------- xen/arch/x86/acpi/cpufreq/acpi.c | 2 +- xen/arch/x86/acpi/cpufreq/cpufreq.c | 4 ++-- xen/arch/x86/acpi/cpufreq/powernow.c | 4 ++-- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 0b3d0631dd..1d2ef776fe 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -178,10 +178,11 @@ static void cf_check do_get_hw_residencies(void *arg) struct cpuinfo_x86 *c =3D ¤t_cpu_data; struct hw_residencies *hw_res =3D arg; =20 - if ( c->x86_vendor !=3D X86_VENDOR_INTEL || c->x86 !=3D 6 ) + /* XXX Does this need to be extented to include fam 18/19? */ + if ( c->vendor !=3D X86_VENDOR_INTEL || c->family !=3D 6 ) return; =20 - switch ( c->x86_model ) + switch ( c->model ) { /* 4th generation Intel Core (Haswell) */ case 0x45: @@ -915,7 +916,7 @@ void cf_check acpi_dead_idle(void) mwait(cx->address, 0); } } - else if ( (current_cpu_data.x86_vendor & + else if ( (current_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && cx->entry_method =3D=3D ACPI_CSTATE_EM_SYSIO ) { @@ -1042,8 +1043,8 @@ static void acpi_processor_power_init_bm_check(struct= acpi_processor_flags *flag flags->bm_check =3D 0; if ( num_online_cpus() =3D=3D 1 ) flags->bm_check =3D 1; - else if ( (c->x86_vendor =3D=3D X86_VENDOR_INTEL) || - ((c->x86_vendor =3D=3D X86_VENDOR_AMD) && (c->x86 =3D=3D 0x1= 5)) ) + else if ( (c->vendor =3D=3D X86_VENDOR_INTEL) || + ((c->vendor =3D=3D X86_VENDOR_AMD) && (c->family =3D=3D 0x15= )) ) { /* * Today all MP CPUs that support C3 share cache. @@ -1059,8 +1060,7 @@ static void acpi_processor_power_init_bm_check(struct= acpi_processor_flags *flag * is not required while entering C3 type state on * P4, Core and beyond CPUs */ - if ( c->x86_vendor =3D=3D X86_VENDOR_INTEL && - (c->x86 > 0x6 || (c->x86 =3D=3D 6 && c->x86_model >=3D 14)) ) + if ( c->vendor =3D=3D X86_VENDOR_INTEL && c->vfm >=3D INTEL_CORE_YONAH= ) flags->bm_control =3D 0; } =20 @@ -1416,12 +1416,12 @@ static void amd_cpuidle_init(struct acpi_processor_= power *power) if ( vendor_override < 0 ) return; =20 - switch ( c->x86 ) + switch ( c->family ) { case 0x1a: case 0x19: case 0x18: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_HYGON ) { default: vendor_override =3D -1; @@ -1648,7 +1648,7 @@ static int cf_check cpu_callback( break; =20 case CPU_ONLINE: - if ( (boot_cpu_data.x86_vendor & + if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && processor_powers[cpu] ) amd_cpuidle_init(processor_powers[cpu]); diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/a= cpi.c index d0ca660db1..de67f1aee2 100644 --- a/xen/arch/x86/acpi/cpufreq/acpi.c +++ b/xen/arch/x86/acpi/cpufreq/acpi.c @@ -454,7 +454,7 @@ static int cf_check acpi_cpufreq_cpu_init(struct cpufre= q_policy *policy) =20 /* Check for APERF/MPERF support in hardware * also check for boost support */ - if (c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->cpuid_level >=3D 6) + if (c->vendor =3D=3D X86_VENDOR_INTEL && c->cpuid_level >=3D 6) on_selected_cpus(cpumask_of(cpu), feature_detect, policy, 1); =20 /* diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufre= q/cpufreq.c index 5740c0d438..9ef62b3538 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -133,7 +133,7 @@ static int __init cf_check cpufreq_driver_init(void) =20 ret =3D -ENOENT; =20 - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: for ( i =3D 0; i < cpufreq_xen_cnt; i++ ) @@ -252,7 +252,7 @@ __initcall(cpufreq_driver_late_init); int cpufreq_cpu_init(unsigned int cpu) { /* Currently we only handle Intel, AMD and Hygon processor */ - if ( boot_cpu_data.x86_vendor & + if ( boot_cpu_data.vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYGON) ) return cpufreq_add_cpu(cpu); =20 diff --git a/xen/arch/x86/acpi/cpufreq/powernow.c b/xen/arch/x86/acpi/cpufr= eq/powernow.c index beab6cac36..55166eac72 100644 --- a/xen/arch/x86/acpi/cpufreq/powernow.c +++ b/xen/arch/x86/acpi/cpufreq/powernow.c @@ -143,7 +143,7 @@ static void amd_fixup_frequency(struct xen_processor_px= *px) int index =3D px->control & 0x00000007; const struct cpuinfo_x86 *c =3D ¤t_cpu_data; =20 - if ((c->x86 !=3D 0x10 || c->x86_model >=3D 10) && c->x86 !=3D 0x11) + if ((c->family !=3D 0x10 || c->model >=3D 10) && c->family !=3D 0x11) return; =20 val =3D rdmsr(MSR_PSTATE_DEF_BASE + index); @@ -157,7 +157,7 @@ static void amd_fixup_frequency(struct xen_processor_px= *px) =20 fid =3D val & 0x3f; did =3D (val >> 6) & 7; - if (c->x86 =3D=3D 0x10) + if (c->family =3D=3D 0x10) px->core_frequency =3D (100 * (fid + 16)) >> did; else px->core_frequency =3D (100 * (fid + 8)) >> did; --=20 2.51.1 From nobody Mon Apr 13 02:02:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" struct cpuinfo_x86 .x86 =3D> .family .x86_vendor =3D> .vendor .x86_model =3D> .model .x86_mask =3D> .stepping No functional change. This work is part of making Xen safe for Intel family 18/19. Signed-off-by: Kevin Lampis --- I couldn't find any information about these Intel family 6 processors: model 0x5d: /* SoFIA 3G Granite/ES2.1 */ model 0x65: /* SoFIA LTE AOSP */ model 0x6e: /* Cougar Mountain */ Should I add them to intel-family.h? --- xen/arch/x86/hvm/hvm.c | 2 +- xen/arch/x86/hvm/svm/svm.c | 6 +- xen/arch/x86/hvm/vmx/vmcs.c | 4 +- xen/arch/x86/hvm/vmx/vmx.c | 278 ++++++++++++++++++------------------ 4 files changed, 144 insertions(+), 146 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4d37a93c57..6ad52e1197 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3850,7 +3850,7 @@ void hvm_ud_intercept(struct cpu_user_regs *regs) { struct vcpu *cur =3D current; bool should_emulate =3D - cur->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.x86_vendor; + cur->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.vendor; struct hvm_emulate_ctxt ctxt; =20 hvm_emulate_init_once(&ctxt, opt_hvm_fep ? NULL : is_cross_vendor, reg= s); diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 18ba837738..1320abe392 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -590,7 +590,7 @@ static void cf_check svm_cpuid_policy_changed(struct vc= pu *v) u32 bitmap =3D vmcb_get_exception_intercepts(vmcb); =20 if ( opt_hvm_fep || - (v->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.x86_vendor)= ) + (v->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.vendor) ) bitmap |=3D (1U << X86_EXC_UD); else bitmap &=3D ~(1U << X86_EXC_UD); @@ -1057,7 +1057,7 @@ static void svm_guest_osvw_init(struct domain *d) * be conservative here and therefore we tell the guest that erratum 2= 98 * is present (because we really don't know). */ - if ( osvw_length =3D=3D 0 && boot_cpu_data.x86 =3D=3D 0x10 ) + if ( osvw_length =3D=3D 0 && boot_cpu_data.family =3D=3D 0x10 ) svm->osvw.status |=3D 1; =20 spin_unlock(&osvw_lock); @@ -1791,7 +1791,7 @@ static int cf_check svm_msr_read_intercept( if ( !rdmsr_safe(msr, msr_content) ) break; =20 - if ( boot_cpu_data.x86 =3D=3D 0xf ) + if ( boot_cpu_data.family =3D=3D 0xf ) { /* * Win2k8 x64 reads this MSR on revF chips, where it wasn't diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c index c2e7f9aed3..d3b1730f1d 100644 --- a/xen/arch/x86/hvm/vmx/vmcs.c +++ b/xen/arch/x86/hvm/vmx/vmcs.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -2163,8 +2164,7 @@ int __init vmx_vmcs_init(void) =20 if ( opt_ept_ad < 0 ) /* Work around Erratum AVR41 on Avoton processors. */ - opt_ept_ad =3D !(boot_cpu_data.x86 =3D=3D 6 && - boot_cpu_data.x86_model =3D=3D 0x4d); + opt_ept_ad =3D !(boot_cpu_data.vfm =3D=3D INTEL_ATOM_SILVERMONT_D); =20 ret =3D _vmx_cpu_up(true); =20 diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 82c55f49ae..c332d5078d 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -502,72 +503,75 @@ static const struct lbr_info *__ro_after_init model_s= pecific_lbr; =20 static const struct lbr_info *__init get_model_specific_lbr(void) { - switch ( boot_cpu_data.x86 ) + switch ( boot_cpu_data.vfm ) { - case 6: - switch ( boot_cpu_data.x86_model ) - { - /* Core2 Duo */ - case 0x0f: - /* Enhanced Core */ - case 0x17: - /* Xeon 7400 */ - case 0x1d: - return c2_lbr; - /* Nehalem */ - case 0x1a: case 0x1e: case 0x1f: case 0x2e: - /* Westmere */ - case 0x25: case 0x2c: case 0x2f: - /* Sandy Bridge */ - case 0x2a: case 0x2d: - /* Ivy Bridge */ - case 0x3a: case 0x3e: - /* Haswell */ - case 0x3c: case 0x3f: case 0x45: case 0x46: - /* Broadwell */ - case 0x3d: case 0x47: case 0x4f: case 0x56: - return nh_lbr; - /* Skylake */ - case 0x4e: case 0x5e: - /* Xeon Scalable */ - case 0x55: - /* Cannon Lake */ - case 0x66: - /* Goldmont Plus */ - case 0x7a: - /* Ice Lake */ - case 0x6a: case 0x6c: case 0x7d: case 0x7e: - /* Tiger Lake */ - case 0x8c: case 0x8d: - /* Tremont */ - case 0x86: - /* Kaby Lake */ - case 0x8e: case 0x9e: - /* Comet Lake */ - case 0xa5: case 0xa6: - return sk_lbr; - /* Atom */ - case 0x1c: case 0x26: case 0x27: case 0x35: case 0x36: - return at_lbr; - /* Silvermont */ - case 0x37: case 0x4a: case 0x4d: case 0x5a: case 0x5d: - /* Airmont */ - case 0x4c: - return sm_lbr; - /* Goldmont */ - case 0x5c: case 0x5f: - return gm_lbr; - } - break; - - case 15: - switch ( boot_cpu_data.x86_model ) - { - /* Pentium4/Xeon with em64t */ - case 3: case 4: case 6: - return p4_lbr; - } - break; + case INTEL_CORE2_DUNNINGTON: + case INTEL_CORE2_MEROM: + case INTEL_CORE2_PENRYN: + return c2_lbr; + + case INTEL_NEHALEM: + case INTEL_NEHALEM_EP: + case INTEL_NEHALEM_EX: + case INTEL_NEHALEM_G: + case INTEL_WESTMERE: + case INTEL_WESTMERE_EP: + case INTEL_WESTMERE_EX: + case INTEL_SANDYBRIDGE: + case INTEL_SANDYBRIDGE_X: + case INTEL_IVYBRIDGE: + case INTEL_IVYBRIDGE_X: + case INTEL_HASWELL: + case INTEL_HASWELL_G: + case INTEL_HASWELL_L: + case INTEL_HASWELL_X: + case INTEL_BROADWELL: + case INTEL_BROADWELL_D: + case INTEL_BROADWELL_G: + case INTEL_BROADWELL_X: + return nh_lbr; + + case INTEL_SKYLAKE: + case INTEL_SKYLAKE_L: + case INTEL_SKYLAKE_X: + case INTEL_CANNONLAKE_L: + case INTEL_ATOM_GOLDMONT_PLUS: + case INTEL_ICELAKE: + case INTEL_ICELAKE_D: + case INTEL_ICELAKE_L: + case INTEL_ICELAKE_X: + case INTEL_TIGERLAKE: + case INTEL_TIGERLAKE_L: + case INTEL_ATOM_TREMONT_D: + case INTEL_KABYLAKE: + case INTEL_KABYLAKE_L: + case INTEL_COMETLAKE: + case INTEL_COMETLAKE_L: + return sk_lbr; + + case INTEL_ATOM_BONNELL: + case INTEL_ATOM_BONNELL_MID: + case INTEL_ATOM_SALTWELL: + case INTEL_ATOM_SALTWELL_MID: + case INTEL_ATOM_SALTWELL_TABLET: + return at_lbr; + + case INTEL_ATOM_SILVERMONT: + case INTEL_ATOM_SILVERMONT_MID: + case INTEL_ATOM_SILVERMONT_D: + case INTEL_ATOM_SILVERMONT_MID2: + //case 0x5d: // XXX + case INTEL_ATOM_AIRMONT: + return sm_lbr; + + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_D: + return gm_lbr; + + case INTEL_P4_PRESCOTT: + case INTEL_P4_PRESCOTT_2M: + case INTEL_P4_CEDARMILL: + return p4_lbr; } =20 return NULL; @@ -804,7 +808,7 @@ static void cf_check vmx_cpuid_policy_changed(struct vc= pu *v) int rc =3D 0; =20 if ( opt_hvm_fep || - (v->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.x86_vendor)= ) + (v->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.vendor) ) v->arch.hvm.vmx.exception_bitmap |=3D (1U << X86_EXC_UD); else v->arch.hvm.vmx.exception_bitmap &=3D ~(1U << X86_EXC_UD); @@ -3073,71 +3077,71 @@ static bool __init has_if_pschange_mc(void) * IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at * this time. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return false; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.vfm ) { /* * Core processors since at least Nehalem are vulnerable. */ - case 0x1f: /* Auburndale / Havendale */ - case 0x1e: /* Nehalem */ - case 0x1a: /* Nehalem EP */ - case 0x2e: /* Nehalem EX */ - case 0x25: /* Westmere */ - case 0x2c: /* Westmere EP */ - case 0x2f: /* Westmere EX */ - case 0x2a: /* SandyBridge */ - case 0x2d: /* SandyBridge EP/EX */ - case 0x3a: /* IvyBridge */ - case 0x3e: /* IvyBridge EP/EX */ - case 0x3c: /* Haswell */ - case 0x3f: /* Haswell EX/EP */ - case 0x45: /* Haswell D */ - case 0x46: /* Haswell H */ - case 0x3d: /* Broadwell */ - case 0x47: /* Broadwell H */ - case 0x4f: /* Broadwell EP/EX */ - case 0x56: /* Broadwell D */ - case 0x4e: /* Skylake M */ - case 0x5e: /* Skylake D */ - case 0x55: /* Skylake-X / Cascade Lake */ - case 0x7d: /* Ice Lake */ - case 0x7e: /* Ice Lake */ - case 0x8e: /* Kaby / Coffee / Whiskey Lake M */ - case 0x9e: /* Kaby / Coffee / Whiskey Lake D */ - case 0xa5: /* Comet Lake H/S */ - case 0xa6: /* Comet Lake U */ + case INTEL_NEHALEM_G: + case INTEL_NEHALEM: + case INTEL_NEHALEM_EP: + case INTEL_NEHALEM_EX: + case INTEL_WESTMERE: + case INTEL_WESTMERE_EP: + case INTEL_WESTMERE_EX: + case INTEL_SANDYBRIDGE: + case INTEL_SANDYBRIDGE_X: + case INTEL_IVYBRIDGE: + case INTEL_IVYBRIDGE_X: + case INTEL_HASWELL: + case INTEL_HASWELL_X: + case INTEL_HASWELL_L: + case INTEL_HASWELL_G: + case INTEL_BROADWELL: + case INTEL_BROADWELL_G: + case INTEL_BROADWELL_X: + case INTEL_BROADWELL_D: + case INTEL_SKYLAKE_L: + case INTEL_SKYLAKE: + case INTEL_SKYLAKE_X: + case INTEL_ICELAKE: + case INTEL_ICELAKE_L: + case INTEL_KABYLAKE_L: + case INTEL_KABYLAKE: + case INTEL_COMETLAKE: + case INTEL_COMETLAKE_L: return true; =20 /* * Atom processors are not vulnerable. */ - case 0x1c: /* Pineview */ - case 0x26: /* Lincroft */ - case 0x27: /* Penwell */ - case 0x35: /* Cloverview */ - case 0x36: /* Cedarview */ - case 0x37: /* Baytrail / Valleyview (Silvermont) */ - case 0x4d: /* Avaton / Rangely (Silvermont) */ - case 0x4c: /* Cherrytrail / Brasswell */ - case 0x4a: /* Merrifield */ - case 0x5a: /* Moorefield */ - case 0x5c: /* Goldmont */ - case 0x5d: /* SoFIA 3G Granite/ES2.1 */ - case 0x65: /* SoFIA LTE AOSP */ - case 0x5f: /* Denverton */ - case 0x6e: /* Cougar Mountain */ - case 0x75: /* Lightning Mountain */ - case 0x7a: /* Gemini Lake */ - case 0x86: /* Jacobsville */ + case INTEL_ATOM_BONNELL: + case INTEL_ATOM_BONNELL_MID: + case INTEL_ATOM_SALTWELL_MID: + case INTEL_ATOM_SALTWELL_TABLET: + case INTEL_ATOM_SALTWELL: + case INTEL_ATOM_SILVERMONT: + case INTEL_ATOM_SILVERMONT_D: + case INTEL_ATOM_AIRMONT: + case INTEL_ATOM_SILVERMONT_MID: + case INTEL_ATOM_SILVERMONT_MID2: + case INTEL_ATOM_GOLDMONT: + //case 0x5d: /* SoFIA 3G Granite/ES2.1 */ // XXX ??? + //case 0x65: /* SoFIA LTE AOSP */ // XXX ??? + case INTEL_ATOM_GOLDMONT_D: + //case 0x6e: /* Cougar Mountain */ // XXX ??? + case INTEL_ATOM_AIRMONT_NP: + case INTEL_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_TREMONT_D: return false; =20 default: printk("Unrecognised CPU model %#x - assuming vulnerable to IF_PSC= HANGE_MC\n", - boot_cpu_data.x86_model); + boot_cpu_data.model); return true; } } @@ -3431,23 +3435,20 @@ static void __init lbr_tsx_fixup_check(void) * fixed up as well. */ if ( cpu_has_hle || cpu_has_rtm || - boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.vfm ) { - case 0x3c: /* HSM182, HSD172 - 4th gen Core */ - case 0x3f: /* HSE117 - Xeon E5 v3 */ - case 0x45: /* HSM182 - 4th gen Core */ - case 0x46: /* HSM182, HSD172 - 4th gen Core (GT3) */ - case 0x3d: /* BDM127 - 5th gen Core */ - case 0x47: /* BDD117 - 5th gen Core (GT3) - BDW117 - Xeon E3-1200 v4 */ - case 0x4f: /* BDF85 - Xeon E5-2600 v4 - BDH75 - Core-i7 for LGA2011-v3 Socket - BDX88 - Xeon E7-x800 v4 */ - case 0x56: /* BDE105 - Xeon D-1500 */ + case INTEL_HASWELL: + case INTEL_HASWELL_X: + case INTEL_HASWELL_L: + case INTEL_HASWELL_G: + case INTEL_BROADWELL: + case INTEL_BROADWELL_G: + case INTEL_BROADWELL_X: + case INTEL_BROADWELL_D: break; default: return; @@ -3476,19 +3477,16 @@ static void __init ler_to_fixup_check(void) * that are not equal to bit[47]. Attempting to context switch this v= alue * may cause a #GP. Software should sign extend the MSR. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || + boot_cpu_data.family !=3D 6 ) return; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.vfm ) { - case 0x3d: /* BDM131 - 5th gen Core */ - case 0x47: /* BDD??? - 5th gen Core (H-Processor line) - BDW120 - Xeon E3-1200 v4 */ - case 0x4f: /* BDF93 - Xeon E5-2600 v4 - BDH80 - Core-i7 for LGA2011-v3 Socket - BDX93 - Xeon E7-x800 v4 */ - case 0x56: /* BDE??? - Xeon D-1500 */ + case INTEL_BROADWELL: + case INTEL_BROADWELL_G: + case INTEL_BROADWELL_X: + case INTEL_BROADWELL_D: ler_to_fixup_needed =3D true; break; } --=20 2.51.1 From nobody Mon Apr 13 02:02:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; 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charset="utf-8" struct cpuinfo_x86 .x86 =3D> .family .x86_vendor =3D> .vendor .x86_model =3D> .model .x86_mask =3D> .stepping No functional change. This work is part of making Xen safe for Intel family 18/19. Signed-off-by: Kevin Lampis Acked-by: Jan Beulich --- Inside core2_vpmu_init() there is a check for family =3D=3D 6. Should this be extended to family 18/19? --- xen/arch/x86/cpu/centaur.c | 4 ++-- xen/arch/x86/cpu/hygon.c | 4 ++-- xen/arch/x86/cpu/intel_cacheinfo.c | 6 +++--- xen/arch/x86/cpu/mtrr/generic.c | 6 +++--- xen/arch/x86/cpu/mwait-idle.c | 4 ++-- xen/arch/x86/cpu/vpmu.c | 4 ++-- xen/arch/x86/cpu/vpmu_amd.c | 6 +++--- xen/arch/x86/cpu/vpmu_intel.c | 6 ++++-- 8 files changed, 21 insertions(+), 19 deletions(-) diff --git a/xen/arch/x86/cpu/centaur.c b/xen/arch/x86/cpu/centaur.c index d2e7c8ec99..9123b05dc1 100644 --- a/xen/arch/x86/cpu/centaur.c +++ b/xen/arch/x86/cpu/centaur.c @@ -41,7 +41,7 @@ static void init_c3(struct cpuinfo_x86 *c) } } =20 - if (c->x86 =3D=3D 0x6 && c->x86_model >=3D 0xf) { + if (c->family =3D=3D 0x6 && c->model >=3D 0xf) { c->x86_cache_alignment =3D c->x86_clflush_size * 2; __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); } @@ -52,7 +52,7 @@ static void init_c3(struct cpuinfo_x86 *c) =20 static void cf_check init_centaur(struct cpuinfo_x86 *c) { - if (c->x86 =3D=3D 6) + if (c->family =3D=3D 6) init_c3(c); } =20 diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c index b99d83ed4d..7a9fc25d31 100644 --- a/xen/arch/x86/cpu/hygon.c +++ b/xen/arch/x86/cpu/hygon.c @@ -41,12 +41,12 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c) =20 /* Probe for NSCB on Zen2 CPUs when not virtualised */ if (!cpu_has_hypervisor && !cpu_has_nscb && c =3D=3D &boot_cpu_data && - c->x86 =3D=3D 0x18) + c->family =3D=3D 0x18) detect_zen2_null_seg_behaviour(); =20 /* * TODO: Check heuristic safety with Hygon first - if (c->x86 =3D=3D 0x18) + if (c->family =3D=3D 0x18) amd_init_spectral_chicken(); */ =20 diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_ca= cheinfo.c index e88faa7545..a81d0764fb 100644 --- a/xen/arch/x86/cpu/intel_cacheinfo.c +++ b/xen/arch/x86/cpu/intel_cacheinfo.c @@ -168,15 +168,15 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves =3D=3D 0 || c->x86 =3D=3D 15) && c->cpuid_level > 1= && - c->x86_vendor !=3D X86_VENDOR_SHANGHAI) + if ((num_cache_leaves =3D=3D 0 || c->family =3D=3D 15) && c->cpuid_level = > 1 && + c->vendor !=3D X86_VENDOR_SHANGHAI) { /* supports eax=3D2 call */ unsigned int i, j, n, regs[4]; unsigned char *dp =3D (unsigned char *)regs; int only_trace =3D 0; =20 - if (num_cache_leaves !=3D 0 && c->x86 =3D=3D 15) + if (num_cache_leaves !=3D 0 && c->family =3D=3D 15) only_trace =3D 1; =20 /* Number of times to iterate */ diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generi= c.c index c587e9140e..190be7f1b4 100644 --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -218,9 +218,9 @@ static void __init print_mtrr_state(const char *level) printk("%s %u disabled\n", level, i); } =20 - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD && - boot_cpu_data.x86 >=3D 0xf) || - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) { + if ((boot_cpu_data.vendor =3D=3D X86_VENDOR_AMD && + boot_cpu_data.family >=3D 0xf) || + boot_cpu_data.vendor =3D=3D X86_VENDOR_HYGON) { uint64_t syscfg, tom2; =20 rdmsrl(MSR_K8_SYSCFG, syscfg); diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index 5962ec1db9..6776eeb9ac 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1637,7 +1637,7 @@ static int __init mwait_idle_probe(void) lapic_timer_reliable_states =3D LAPIC_TIMER_ALWAYS_RELIABLE; =20 pr_debug(PREFIX "v" MWAIT_IDLE_VERSION " model %#x\n", - boot_cpu_data.x86_model); + boot_cpu_data.model); =20 pr_debug(PREFIX "lapic_timer_reliable_states %#x\n", lapic_timer_reliable_states); @@ -1816,7 +1816,7 @@ bool __init mwait_pc10_supported(void) { unsigned int ecx, edx, dummy; =20 - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || + if (boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || !cpu_has_monitor || boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) return false; diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c index c28192ea26..64328bdf3f 100644 --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -398,7 +398,7 @@ int vpmu_load(struct vcpu *v, bool from_guest) static int vpmu_arch_initialise(struct vcpu *v) { struct vpmu_struct *vpmu =3D vcpu_vpmu(v); - uint8_t vendor =3D current_cpu_data.x86_vendor; + uint8_t vendor =3D current_cpu_data.vendor; int ret; =20 BUILD_BUG_ON(sizeof(struct xen_pmu_intel_ctxt) > XENPMU_CTXT_PAD_SZ); @@ -815,7 +815,7 @@ static struct notifier_block cpu_nfb =3D { =20 static int __init cf_check vpmu_init(void) { - int vendor =3D current_cpu_data.x86_vendor; + int vendor =3D current_cpu_data.vendor; const struct arch_vpmu_ops *ops =3D NULL; =20 if ( !opt_vpmu_enabled ) diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c index d1f6bd5495..943a0f4ebe 100644 --- a/xen/arch/x86/cpu/vpmu_amd.c +++ b/xen/arch/x86/cpu/vpmu_amd.c @@ -532,7 +532,7 @@ static const struct arch_vpmu_ops *__init common_init(v= oid) if ( !num_counters ) { printk(XENLOG_WARNING "VPMU: Unsupported CPU family %#x\n", - current_cpu_data.x86); + current_cpu_data.family); return ERR_PTR(-EINVAL); } =20 @@ -557,7 +557,7 @@ static const struct arch_vpmu_ops *__init common_init(v= oid) =20 const struct arch_vpmu_ops *__init amd_vpmu_init(void) { - switch ( current_cpu_data.x86 ) + switch ( current_cpu_data.family ) { case 0x15: case 0x17: @@ -585,7 +585,7 @@ const struct arch_vpmu_ops *__init amd_vpmu_init(void) =20 const struct arch_vpmu_ops *__init hygon_vpmu_init(void) { - switch ( current_cpu_data.x86 ) + switch ( current_cpu_data.family ) { case 0x18: num_counters =3D F15H_NUM_COUNTERS; diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c index 1e3b06ef8e..c623554e37 100644 --- a/xen/arch/x86/cpu/vpmu_intel.c +++ b/xen/arch/x86/cpu/vpmu_intel.c @@ -917,7 +917,9 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) return ERR_PTR(-EINVAL); } =20 - if ( current_cpu_data.x86 !=3D 6 ) + /* XXX Does this need to be changed to include family 18/19? + * Is the core2_ function name misleading? */ + if ( current_cpu_data.family !=3D 6 ) { printk(XENLOG_WARNING "VPMU: only family 6 is supported\n"); return ERR_PTR(-EINVAL); @@ -958,7 +960,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void) sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt; =20 /* TODO: It's clearly incorrect for this to quirk all Intel Fam6 CPUs.= */ - pmc_quirk =3D current_cpu_data.x86 =3D=3D 6; + pmc_quirk =3D current_cpu_data.family =3D=3D 6; =20 if ( sizeof(struct xen_pmu_data) + sizeof(uint64_t) * fixed_pmc_cnt + sizeof(struct xen_pmu_cntr_pair) * arch_pmc_cnt > PAGE_SIZE ) --=20 2.51.1 From nobody Mon Apr 13 02:02:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" struct cpuinfo_x86 .x86 =3D> .family .x86_vendor =3D> .vendor .x86_model =3D> .model .x86_mask =3D> .stepping No functional change. This work is part of making Xen safe for Intel family 18/19. Signed-off-by: Kevin Lampis Acked-by: Jan Beulich --- xen/arch/x86/alternative.c | 8 ++++---- xen/arch/x86/apic.c | 2 +- xen/arch/x86/cpuid.c | 2 +- xen/arch/x86/dom0_build.c | 4 ++-- xen/arch/x86/domain.c | 12 ++++++------ xen/arch/x86/e820.c | 2 +- xen/arch/x86/i8259.c | 2 +- xen/arch/x86/irq.c | 4 ++-- xen/arch/x86/mpparse.c | 6 +++--- xen/arch/x86/msr.c | 4 ++-- xen/arch/x86/nmi.c | 12 ++++++------ xen/arch/x86/platform_hypercall.c | 8 ++++---- xen/arch/x86/pv/domain.c | 2 +- xen/arch/x86/setup.c | 6 +++--- xen/arch/x86/traps-setup.c | 4 ++-- xen/arch/x86/tsx.c | 4 ++-- xen/drivers/passthrough/amd/iommu_init.c | 6 +++--- 17 files changed, 44 insertions(+), 44 deletions(-) diff --git a/xen/arch/x86/alternative.c b/xen/arch/x86/alternative.c index 9f844241bc..5ed0c26725 100644 --- a/xen/arch/x86/alternative.c +++ b/xen/arch/x86/alternative.c @@ -89,7 +89,7 @@ static bool init_or_livepatch_read_mostly toolchain_nops_= are_ideal; =20 static void __init arch_init_ideal_nops(void) { - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: /* @@ -97,10 +97,10 @@ static void __init arch_init_ideal_nops(void) * actually perform better with the "k8_nops" than with the SDM- * recommended NOPs. */ - if ( boot_cpu_data.x86 !=3D 6 ) + if ( boot_cpu_data.family !=3D 6 ) break; =20 - switch ( boot_cpu_data.x86_model ) + switch ( boot_cpu_data.model ) { case 0x0f ... 0x1b: case 0x1d ... 0x25: @@ -111,7 +111,7 @@ static void __init arch_init_ideal_nops(void) break; =20 case X86_VENDOR_AMD: - if ( boot_cpu_data.x86 <=3D 0xf ) + if ( boot_cpu_data.family <=3D 0xf ) ideal_nops =3D k8_nops; break; } diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index fb38be7ec3..d69ef9e16a 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -406,7 +406,7 @@ void __init init_bsp_APIC(void) value |=3D APIC_SPIV_APIC_ENABLED; =20 /* This bit is reserved on P4/Xeon and should be cleared */ - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && (boot_cpu_da= ta.x86 =3D=3D 15)) + if ((boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL) && (boot_cpu_data.f= amily =3D=3D 15)) value &=3D ~APIC_SPIV_FOCUS_DISABLED; else value |=3D APIC_SPIV_FOCUS_DISABLED; diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 5decfad8cd..6e9b15c9c3 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -437,7 +437,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, =20 case 0xa: /* TODO: Rework vPMU control in terms of toolstack choices. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || !vpmu_available(v) ) *res =3D EMPTY_LEAF; else diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c index 0b467fd4a4..864dd9e53e 100644 --- a/xen/arch/x86/dom0_build.c +++ b/xen/arch/x86/dom0_build.c @@ -572,10 +572,10 @@ int __init dom0_setup_permissions(struct domain *d) rc |=3D iomem_deny_access(d, mfn, mfn); } /* HyperTransport range. */ - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) { mfn =3D paddr_to_pfn(1UL << - (boot_cpu_data.x86 < 0x17 ? 40 : paddr_bits)); + (boot_cpu_data.family < 0x17 ? 40 : paddr_bits)= ); rc |=3D iomem_deny_access(d, mfn - paddr_to_pfn(3UL << 32), mfn - = 1); } =20 diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 8eb1509782..b36e113724 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -319,7 +319,7 @@ void domain_cpu_policy_changed(struct domain *d) if ( cpu_has_htt ) edx |=3D cpufeat_mask(X86_FEATURE_HTT); =20 - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: /* @@ -372,7 +372,7 @@ void domain_cpu_policy_changed(struct domain *d) { uint64_t mask =3D cpuidmask_defaults._6c; =20 - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_AMD ) mask &=3D (~0ULL << 32) | p->basic.raw[6].c; =20 d->arch.pv.cpuidmasks->_6c =3D mask; @@ -387,7 +387,7 @@ void domain_cpu_policy_changed(struct domain *d) * wholesale from the policy, but clamp the features in 7[0].e= bx * per usual. */ - if ( boot_cpu_data.x86_vendor & + if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) mask =3D (((uint64_t)p->feat.max_subleaf << 32) | ((uint32_t)mask & p->feat._7b0)); @@ -400,7 +400,7 @@ void domain_cpu_policy_changed(struct domain *d) uint64_t mask =3D cpuidmask_defaults.Da1; uint32_t eax =3D p->xstate.Da1; =20 - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL ) mask &=3D (~0ULL << 32) | eax; =20 d->arch.pv.cpuidmasks->Da1 =3D mask; @@ -427,7 +427,7 @@ void domain_cpu_policy_changed(struct domain *d) if ( !(p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) edx &=3D ~CPUID_COMMON_1D_FEATURES; =20 - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: mask &=3D ((uint64_t)edx << 32) | ecx; @@ -457,7 +457,7 @@ void domain_cpu_policy_changed(struct domain *d) cpu_policy_updated(v); =20 /* If PMU version is zero then the guest doesn't have VPMU */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && p->basic.pmu_version =3D=3D 0 ) vpmu_destroy(v); } diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c index ca577c0bde..872208ab37 100644 --- a/xen/arch/x86/e820.c +++ b/xen/arch/x86/e820.c @@ -426,7 +426,7 @@ static uint64_t __init mtrr_top_of_ram(void) =20 /* By default we check only Intel systems. */ if ( e820_mtrr_clip =3D=3D -1 ) - e820_mtrr_clip =3D boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTE= L; + e820_mtrr_clip =3D boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL; =20 if ( !e820_mtrr_clip ) return 0; diff --git a/xen/arch/x86/i8259.c b/xen/arch/x86/i8259.c index 5c7e21a751..d2a08661f8 100644 --- a/xen/arch/x86/i8259.c +++ b/xen/arch/x86/i8259.c @@ -419,7 +419,7 @@ void __init init_IRQ(void) * the interrupt. */ cpumask_copy(desc->arch.cpu_mask, - (boot_cpu_data.x86_vendor & + (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ? &cpumask_all : cpumask_of(cpu= ))); desc->arch.vector =3D LEGACY_VECTOR(irq); diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c index cc2934bfca..739fc04bd1 100644 --- a/xen/arch/x86/irq.c +++ b/xen/arch/x86/irq.c @@ -2011,8 +2011,8 @@ void do_IRQ(struct cpu_user_regs *regs) * interrupts have been delivered to CPUs * different than the BSP. */ - (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | - X86_VENDOR_HYGON))) && + (boot_cpu_data.vendor & (X86_VENDOR_AMD | + X86_VENDOR_HYGON))) && bogus_8259A_irq(vector - FIRST_LEGACY_VECTOR)) ) { printk("CPU%u: No irq handler for vector %02x (IRQ %d%s)\n= ", diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c index c1171f7a3a..1b41aa573f 100644 --- a/xen/arch/x86/mpparse.c +++ b/xen/arch/x86/mpparse.c @@ -511,9 +511,9 @@ static inline void __init construct_default_ISA_mptable= (int mpc_default_type) /* Either an integrated APIC or a discrete 82489DX. */ processor.mpc_apicver =3D mpc_default_type > 4 ? 0x10 : 0x01; processor.mpc_cpuflag =3D CPU_ENABLED; - processor.mpc_cpufeature =3D (boot_cpu_data.x86 << 8) | - (boot_cpu_data.x86_model << 4) | - boot_cpu_data.x86_mask; + processor.mpc_cpufeature =3D (boot_cpu_data.family << 8) | + (boot_cpu_data.model << 4) | + boot_cpu_data.stepping; processor.mpc_featureflag =3D boot_cpu_data.x86_capability[FEATURESET_1d]; processor.mpc_reserved[0] =3D 0; diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index ad75a2e108..6a97be59d5 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -170,7 +170,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) =20 case MSR_IA32_PLATFORM_ID: if ( !(cp->x86_vendor & X86_VENDOR_INTEL) || - !(boot_cpu_data.x86_vendor & X86_VENDOR_INTEL) ) + !(boot_cpu_data.vendor & X86_VENDOR_INTEL) ) goto gp_fault; rdmsrl(MSR_IA32_PLATFORM_ID, *val); break; @@ -190,7 +190,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) * the guest. */ if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || - !(boot_cpu_data.x86_vendor & + !(boot_cpu_data.vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || rdmsr_safe(MSR_AMD_PATCHLEVEL, val) ) goto gp_fault; diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index a0c9194ff0..447fac19d3 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -216,12 +216,12 @@ void disable_lapic_nmi_watchdog(void) { if (nmi_active <=3D 0) return; - switch (boot_cpu_data.x86_vendor) { + switch (boot_cpu_data.vendor) { case X86_VENDOR_AMD: wrmsrns(MSR_K7_EVNTSEL0, 0); break; case X86_VENDOR_INTEL: - switch (boot_cpu_data.x86) { + switch (boot_cpu_data.family) { case 6: wrmsrns(MSR_P6_EVNTSEL(0), 0); break; @@ -362,7 +362,7 @@ static void setup_p4_watchdog(void) clear_msr_range(0x3F1, 2); /* MSR 0x3F0 seems to have a default value of 0xFC00, but current docs doesn't fully define it, so leave it alone for now. */ - if (boot_cpu_data.x86_model >=3D 0x3) { + if (boot_cpu_data.model >=3D 0x3) { /* MSR_P4_IQ_ESCR0/1 (0x3ba/0x3bb) removed */ clear_msr_range(0x3A0, 26); clear_msr_range(0x3BC, 3); @@ -387,16 +387,16 @@ void setup_apic_nmi_watchdog(void) if ( nmi_watchdog =3D=3D NMI_NONE ) return; =20 - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_AMD: setup_k7_watchdog(); break; =20 case X86_VENDOR_INTEL: - switch (boot_cpu_data.x86) { + switch (boot_cpu_data.family) { case 6: - setup_p6_watchdog((boot_cpu_data.x86_model < 14)=20 + setup_p6_watchdog((boot_cpu_data.model < 14) ? P6_EVENT_CPU_CLOCKS_NOT_HALTED : CORE_EVENT_CPU_CLOCKS_NOT_HALTED); break; diff --git a/xen/arch/x86/platform_hypercall.c b/xen/arch/x86/platform_hype= rcall.c index cd4f0ae5e5..0431f875af 100644 --- a/xen/arch/x86/platform_hypercall.c +++ b/xen/arch/x86/platform_hypercall.c @@ -104,7 +104,7 @@ static bool msr_read_allowed(unsigned int msr) * the platform doesn't actually support this MSR. */ case MSR_TEMPERATURE_TARGET: - return boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + return boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && host_cpu_policy.basic.digital_temp_sensor; =20 case MSR_PACKAGE_THERM_STATUS: @@ -688,9 +688,9 @@ ret_t do_platform_op( const struct cpuinfo_x86 *c =3D &cpu_data[ver->xen_cpuid]; =20 memcpy(ver->vendor_id, c->x86_vendor_id, sizeof(ver->vendor_id= )); - ver->family =3D c->x86; - ver->model =3D c->x86_model; - ver->stepping =3D c->x86_mask; + ver->family =3D c->family; + ver->model =3D c->model; + ver->stepping =3D c->stepping; } =20 ver->max_present =3D cpumask_last(&cpu_present_map); diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index d16583a745..0fd05c7059 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -174,7 +174,7 @@ static int __init cf_check pge_init(void) { if ( opt_global_pages =3D=3D -1 ) opt_global_pages =3D !cpu_has_hypervisor || - !(boot_cpu_data.x86_vendor & + !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)); =20 return 0; diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 27c63d1d97..e5f1b4b787 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1407,7 +1407,7 @@ void asmlinkage __init noreturn __start_xen(void) * supervisor shadow stacks are now safe to use. */ bool cpu_has_bug_shstk_fracture =3D - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && !boot_cpu_has(X86_FEATURE_CET_SSS); =20 /* @@ -2038,10 +2038,10 @@ void asmlinkage __init noreturn __start_xen(void) =20 /* Do not enable SMEP/SMAP in PV shim on AMD and Hygon by default */ if ( opt_smep =3D=3D -1 ) - opt_smep =3D !pv_shim || !(boot_cpu_data.x86_vendor & + opt_smep =3D !pv_shim || !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)); if ( opt_smap =3D=3D -1 ) - opt_smap =3D !pv_shim || !(boot_cpu_data.x86_vendor & + opt_smap =3D !pv_shim || !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)); =20 if ( !opt_smep ) diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index d77be8f839..1aff0327dc 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -243,10 +243,10 @@ static void __init init_ler(void) * Intel Pentium 4 is the only known CPU to not use the architectural = MSR * indicies. */ - switch ( boot_cpu_data.x86_vendor ) + switch ( boot_cpu_data.vendor ) { case X86_VENDOR_INTEL: - if ( boot_cpu_data.x86 =3D=3D 0xf ) + if ( boot_cpu_data.family =3D=3D 0xf ) { msr =3D MSR_P4_LER_FROM_LIP; break; diff --git a/xen/arch/x86/tsx.c b/xen/arch/x86/tsx.c index fe9f0ab4f7..38371487b9 100644 --- a/xen/arch/x86/tsx.c +++ b/xen/arch/x86/tsx.c @@ -148,8 +148,8 @@ void tsx_init(void) { printk(XENLOG_ERR "FIRMWARE BUG: CPU %02x-%02x-%02x, ucode 0x%08x: RT= M_ALWAYS_ABORT vs RTM mismatch\n", - boot_cpu_data.x86, boot_cpu_data.x86_model, - boot_cpu_data.x86_mask, this_cpu(cpu_sig).rev); + boot_cpu_data.family, boot_cpu_data.model, + boot_cpu_data.stepping, this_cpu(cpu_sig).rev); =20 setup_clear_cpu_cap(X86_FEATURE_RTM_ALWAYS_ABORT); setup_clear_cpu_cap(X86_FEATURE_TSX_FORCE_ABORT); diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthr= ough/amd/iommu_init.c index 00d2c46cbc..d77dd85112 100644 --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -840,9 +840,9 @@ static void amd_iommu_erratum_746_workaround(struct amd= _iommu *iommu) { u32 value; =20 - if ( (boot_cpu_data.x86 !=3D 0x15) || - (boot_cpu_data.x86_model < 0x10) || - (boot_cpu_data.x86_model > 0x1f) ) + if ( (boot_cpu_data.family !=3D 0x15) || + (boot_cpu_data.model < 0x10) || + (boot_cpu_data.model > 0x1f) ) return; =20 pci_conf_write32(iommu->sbdf, 0xf0, 0x90); --=20 2.51.1 From nobody Mon Apr 13 02:02:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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charset="utf-8" Signed-off-by: Kevin Lampis --- With the first patch for intel.c this now compiles. https://lore.kernel.org/xen-devel/20251124111942.1325635-1-kevin.lampis@cit= rix.com/ --- xen/arch/x86/include/asm/cpufeature.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index dcd223d84f..09b1118cea 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -43,19 +43,15 @@ #ifndef __ASSEMBLER__ =20 struct cpuinfo_x86 { - /* TODO: Phase out the x86 prefixed names. */ union { struct { union { - uint8_t x86_model; uint8_t model; }; union { - uint8_t x86; uint8_t family; }; union { - uint8_t x86_vendor; uint8_t vendor; }; uint8_t _rsvd; /* Use of this needs coordinating w= ith VFM_MAKE() */ @@ -63,7 +59,6 @@ struct cpuinfo_x86 { uint32_t vfm; /* Vendor Family Model */ }; union { - uint8_t x86_mask; uint8_t stepping; }; =20 --=20 2.51.1