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[92.22.18.152]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483a3dfd3d6sm22028005e9.3.2026.02.20.02.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Feb 2026 02:42:58 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ecca221b-0e48-11f1-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1771584179; x=1772188979; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=pzVoneESGXvvOzUPiX+drad6Xn+qjY6oGfG1hwkXseU=; b=AI+ny7woVjInNpSXAJnkFdU29byAMU1N4AP1dP7WLCNQDTrPb7gHuxHyNQs/6ur73m NDytLLeCBJjrbwuIflSI0tdXSG4w2uOuM3FQLRa8jaDxQWHDokmwJfMlgxw+L1X8RtEe 1QOdGCpUNjNLH4f8d+dS2iQf8PgJ9nj9DIJUQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1771584179; x=1772188979; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=pzVoneESGXvvOzUPiX+drad6Xn+qjY6oGfG1hwkXseU=; b=alkfgjYqKTBq70x5i1AZCD7Sm13ATEa/FwV0l9cPjgI7DCgXIjGk+hf/sPhx6xpVKu E8AaNNkYLvCTHmNxf4BwwkwV/uWGQ77FJFqSd4okWlEw5UXqORfw2ITB3gTClP5zBoJd /DLbi8Gs2yVEAgbg/31uoR5OJ/gyj2P8kx5e5R2xYt9Lhx/oPKC1PHS/AefHz/E0rZiz DHYOXMKfipetl4wahbBE7xO0t3PeXSUmQR0gdOYMap0EMSwWopy9+rwh7hDdKXk1vanw 5KrPheVlNzxPWaBU8plrvYIWpO7skmA1JYA+CpJFdZodcIE4HkLSStaTM88o/4yn0s14 Kt4Q== X-Gm-Message-State: AOJu0YwnY64pnlPjdw+jrnKuMW0vJtL2q2nhb9/3JOyaP7F/WYfgGWAN pg29GdAWdvtoxm42mcrInz1TbQGQIC5FxLyG/XjWh0A3V3Q0sfndHRFEM+/yzxVZhJztQbA58ve eIhZdibQvn4aN X-Gm-Gg: AZuq6aJyPWfrW0xgdlmn8O1w61X5ek1O/5xRCf0HComhnyHV2txtOy+7Iej+esBGs+5 KZyFL68Qj9fGBm8wRV2MEh07/f0gVcMEJhO6hO5JN7rw4gVogUNbBIcA1MOohh+hxkUcG4gAh2s ugMt5Ovf1WhG1FZuZYRKQGtn/06Q4776oIMxm5YhBilDIpsnvZAOhjSe3rBqWHWJEEZohb+DI8m +kCs/jgl4zSgM6N7sltli2vZrYo+dyObOkTy09Wd9tiYjWzNiMej45l5FijA5PeNEW6TXCI9ugI 5zSiZTyHGoscYx6VDVgUvNOCAB+MlIEgE/oeafAfRIp70XzBEfDkRQF1eRSRO+2ib/3pXjkqh3a BvB56GGElxg4JB2wPQE8C2VJDRRtIFlHRTsSh+jsLKBGuuX6+RtGKbOl0jjXGCvejD6+7um1ANL /J8pkHuNNkTIzVgkNtUqeOtvaTKN4ixYvBX1u+hJmbH0XKjgUjQeTuBQhVx1lDEn0eUKMM8bc= X-Received: by 2002:a05:600c:4744:b0:47e:e7e5:ff32 with SMTP id 5b1f17b1804b1-4839e66d920mr89358325e9.34.1771584178584; Fri, 20 Feb 2026 02:42:58 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: andrew.cooper3@citrix.com, jbeulich@suse.com, roger.pau@citrix.com, kevin.lampis@citrix.com Subject: [PATCH] x86/cpu/intel: Limit the non-architectural constant_tsc model checks Date: Fri, 20 Feb 2026 10:42:57 +0000 Message-Id: <20260220104257.3405712-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1771584216737158500 Content-Type: text/plain; charset="utf-8" From: Sohil Mehta X86_FEATURE_CONSTANT_TSC is a Linux-defined, synthesized feature flag. It is used across several vendors. Intel CPUs will set the feature when the architectural CPUID.80000007.EDX[1] bit is set. There are also some Intel CPUs that have the X86_FEATURE_CONSTANT_TSC behavior but don't enumerate it with the architectural bit. Those currently have a model range check. Today, virtually all of the CPUs that have the CPUID bit *also* match the "model >=3D 0x0e" check. This is confusing. Instead of an open-ended check, pick some models (INTEL_IVYBRIDGE and P4_WILLAMETTE) as the end of goofy CPUs that should enumerate the bit but don't. These models are relatively arbitrary but conservative pick for this. This makes it obvious that later CPUs (like Family 18+) no longer need to synthesize X86_FEATURE_CONSTANT_TSC. Signed-off-by: Sohil Mehta Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20250219184133.816753-14-sohil.mehta@intel.= com Link: https://git.kernel.org/tip/fadb6f569b10bf668677add876ed50586931b8f3 [Port to Xen] Signed-off-by: Kevin Lampis Signed-off-by: Andrew Cooper Acked-by: Roger Pau Monn=C3=A9 --- xen/arch/x86/cpu/intel.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 584588e406f2..18b3c79dc97f 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -637,14 +637,13 @@ static void cf_check init_intel(struct cpuinfo_x86 *c) /* Work around errata */ Intel_errata_workarounds(c); =20 - if ((c->x86 =3D=3D 0xf && c->x86_model >=3D 0x03) || - (c->x86 =3D=3D 0x6 && c->x86_model >=3D 0x0e)) - __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); if (cpu_has(c, X86_FEATURE_ITSC)) { __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability); __set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability); - } + } else if ((c->vfm >=3D INTEL_P4_PRESCOTT && c->vfm <=3D INTEL_P4_CEDARMI= LL) || + (c->vfm >=3D INTEL_CORE_YONAH && c->vfm <=3D INTEL_IVYBRIDGE)) + __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); =20 if ((opt_cpu_info && !(c->apicid & (c->x86_num_siblings - 1))) || c =3D=3D &boot_cpu_data ) base-commit: 52e801093b6d9f72944328925588b227d7114f8e --=20 2.39.5