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none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1771402924; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nmkFHBBGmW1gFmVNGJrsFCQB+9CCXKUbJdAXWGghiNM=; b=gPtQAbrJ0W7jHHybeb0/Ufmin0ifKbAt6AzDrXFVFWbzpGlMPQ513v+jLWpWyygbuuKCBW zvWvrj/Au4wcSx6zt5y3JgpiB1DHq5jfCdDlc598xegpKWZY05VaShPPyaNUEujUBe8Aoi gqO7WjvpxpLP4DNzZVL0nxAEg1zRuAM= From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-hyperv@vger.kernel.org, kvm@vger.kernel.org Cc: Juergen Gross , "K. Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Paolo Bonzini , Vitaly Kuznetsov , Sean Christopherson , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH v3 05/16] x86/msr: Minimize usage of native_*() msr access functions Date: Wed, 18 Feb 2026 09:21:22 +0100 Message-ID: <20260218082133.400602-6-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; MID_CONTAINS_FROM(1.00)[]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[20]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; URIBL_BLOCKED(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email,zytor.com:email]; FUZZY_RATELIMITED(0.00)[rspamd.com]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spam-Level: X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1771402942379154100 Content-Type: text/plain; charset="utf-8" In order to prepare for some MSR access function reorg work, switch most users of native_{read|write}_msr[_safe]() to the more generic rdmsr*()/wrmsr*() variants. For now this will have some intermediate performance impact with paravirtualization configured when running on bare metal, but this is a prereq change for the planned direct inlining of the rdmsr/wrmsr instructions with this configuration. The main reason for this switch is the planned move of the MSR trace function invocation from the native_*() functions to the generic rdmsr*()/wrmsr*() variants. Without this switch the users of the native_*() functions would lose the related tracing entries. Note that the Xen related MSR access functions will not be switched, as these will be handled after the move of the trace hooks. Signed-off-by: Juergen Gross Acked-by: Sean Christopherson Acked-by: Wei Liu Reviewed-by: H. Peter Anvin (Intel) --- arch/x86/hyperv/ivm.c | 2 +- arch/x86/kernel/cpu/mshyperv.c | 7 +++++-- arch/x86/kernel/kvmclock.c | 2 +- arch/x86/kvm/svm/svm.c | 16 ++++++++-------- arch/x86/xen/pmu.c | 4 ++-- 5 files changed, 17 insertions(+), 14 deletions(-) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 651771534cae..1b2222036a0b 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -327,7 +327,7 @@ int hv_snp_boot_ap(u32 apic_id, unsigned long start_ip,= unsigned int cpu) asm volatile("movl %%ds, %%eax;" : "=3Da" (vmsa->ds.selector)); hv_populate_vmcb_seg(vmsa->ds, vmsa->gdtr.base); =20 - vmsa->efer =3D native_read_msr(MSR_EFER); + rdmsrq(MSR_EFER, vmsa->efer); =20 vmsa->cr4 =3D native_read_cr4(); vmsa->cr3 =3D __native_read_cr3(); diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 579fb2c64cfd..9bebb1a1ebee 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -111,9 +111,12 @@ void hv_para_set_sint_proxy(bool enable) */ u64 hv_para_get_synic_register(unsigned int reg) { + u64 val; + if (WARN_ON(!ms_hyperv.paravisor_present || !hv_is_synic_msr(reg))) return ~0ULL; - return native_read_msr(reg); + rdmsrq(reg, val); + return val; } =20 /* @@ -123,7 +126,7 @@ void hv_para_set_synic_register(unsigned int reg, u64 v= al) { if (WARN_ON(!ms_hyperv.paravisor_present || !hv_is_synic_msr(reg))) return; - native_write_msr(reg, val); + wrmsrq(reg, val); } =20 u64 hv_get_msr(unsigned int reg) diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index b5991d53fc0e..1002bdd45c0f 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -197,7 +197,7 @@ static void kvm_setup_secondary_clock(void) void kvmclock_disable(void) { if (msr_kvm_system_time) - native_write_msr(msr_kvm_system_time, 0); + wrmsrq(msr_kvm_system_time, 0); } =20 static void __init kvmclock_init_mem(void) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 8f8bc863e214..1c0e7cae9e49 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -389,12 +389,12 @@ static void svm_init_erratum_383(void) return; =20 /* Use _safe variants to not break nested virtualization */ - if (native_read_msr_safe(MSR_AMD64_DC_CFG, &val)) + if (rdmsrq_safe(MSR_AMD64_DC_CFG, &val)) return; =20 val |=3D (1ULL << 47); =20 - native_write_msr_safe(MSR_AMD64_DC_CFG, val); + wrmsrq_safe(MSR_AMD64_DC_CFG, val); =20 erratum_383_found =3D true; } @@ -554,9 +554,9 @@ static int svm_enable_virtualization_cpu(void) u64 len, status =3D 0; int err; =20 - err =3D native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); + err =3D rdmsrq_safe(MSR_AMD64_OSVW_ID_LENGTH, &len); if (!err) - err =3D native_read_msr_safe(MSR_AMD64_OSVW_STATUS, &status); + err =3D rdmsrq_safe(MSR_AMD64_OSVW_STATUS, &status); =20 if (err) osvw_status =3D osvw_len =3D 0; @@ -2029,7 +2029,7 @@ static bool is_erratum_383(void) if (!erratum_383_found) return false; =20 - if (native_read_msr_safe(MSR_IA32_MC0_STATUS, &value)) + if (rdmsrq_safe(MSR_IA32_MC0_STATUS, &value)) return false; =20 /* Bit 62 may or may not be set for this mce */ @@ -2040,11 +2040,11 @@ static bool is_erratum_383(void) =20 /* Clear MCi_STATUS registers */ for (i =3D 0; i < 6; ++i) - native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0); + wrmsrq_safe(MSR_IA32_MCx_STATUS(i), 0); =20 - if (!native_read_msr_safe(MSR_IA32_MCG_STATUS, &value)) { + if (!rdmsrq_safe(MSR_IA32_MCG_STATUS, &value)) { value &=3D ~(1ULL << 2); - native_write_msr_safe(MSR_IA32_MCG_STATUS, value); + wrmsrq_safe(MSR_IA32_MCG_STATUS, value); } =20 /* Flush tlb to evict multi-match entries */ diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 8f89ce0b67e3..d49a3bdc448b 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -323,7 +323,7 @@ static u64 xen_amd_read_pmc(int counter) u64 val; =20 msr =3D amd_counters_base + (counter * amd_msr_step); - native_read_msr_safe(msr, &val); + rdmsrq_safe(msr, &val); return val; } =20 @@ -349,7 +349,7 @@ static u64 xen_intel_read_pmc(int counter) else msr =3D MSR_IA32_PERFCTR0 + counter; =20 - native_read_msr_safe(msr, &val); + rdmsrq_safe(msr, &val); return val; } =20 --=20 2.53.0