From nobody Tue Mar 3 05:11:12 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=quarantine dis=quarantine) header.from=suse.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1771402998279784.6558049930558; Wed, 18 Feb 2026 00:23:18 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1235333.1538325 (Exim 4.92) (envelope-from ) id 1vscps-0001gm-Dt; Wed, 18 Feb 2026 08:23:04 +0000 Received: by outflank-mailman (output) from mailman id 1235333.1538325; Wed, 18 Feb 2026 08:23:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vscps-0001ge-AO; Wed, 18 Feb 2026 08:23:04 +0000 Received: by outflank-mailman (input) for mailman id 1235333; Wed, 18 Feb 2026 08:23:02 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vscpq-0001cj-Pa for xen-devel@lists.xenproject.org; Wed, 18 Feb 2026 08:23:02 +0000 Received: from smtp-out1.suse.de (smtp-out1.suse.de [2a07:de40:b251:101:10:150:64:1]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 098ffe0e-0ca3-11f1-9ccf-f158ae23cfc8; Wed, 18 Feb 2026 09:23:00 +0100 (CET) Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 59ECA3E6F0; Wed, 18 Feb 2026 08:23:00 +0000 (UTC) Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 109203EA65; Wed, 18 Feb 2026 08:23:00 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id FfbiAuR2lWlFHwAAD6G6ig (envelope-from ); Wed, 18 Feb 2026 08:23:00 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 098ffe0e-0ca3-11f1-9ccf-f158ae23cfc8 Authentication-Results: smtp-out1.suse.de; none From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH v3 15/16] x86/msr: Reduce number of low level MSR access helpers Date: Wed, 18 Feb 2026 09:21:32 +0100 Message-ID: <20260218082133.400602-16-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260218082133.400602-1-jgross@suse.com> References: <20260218082133.400602-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 59ECA3E6F0 X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Action: no action X-Spam-Score: -4.00 X-Spam-Level: X-Spam-Flag: NO X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-ZM-MESSAGEID: 1771403001085154100 Content-Type: text/plain; charset="utf-8" Some MSR access helpers are redundant now, so remove the no longer needed ones. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 15 ++------------- arch/x86/xen/enlighten_pv.c | 4 ++-- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 66f57265f2f8..84e82c0bb9b1 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -272,22 +272,11 @@ static __always_inline void native_wrmsr(u32 msr, u32= low, u32 high) native_wrmsrq(msr, (u64)high << 32 | low); } =20 -static inline u64 native_read_msr(u32 msr) -{ - return native_rdmsrq(msr); -} - static inline int native_read_msr_safe(u32 msr, u64 *val) { return __rdmsr(msr, val, EX_TYPE_RDMSR_SAFE) ? -EIO : 0; } =20 -/* Can be uninlined because referenced by paravirt */ -static inline void notrace native_write_msr(u32 msr, u64 val) -{ - native_wrmsrq(msr, val); -} - /* Can be uninlined because referenced by paravirt */ static inline int notrace native_write_msr_safe(u32 msr, u64 val) { @@ -312,7 +301,7 @@ static inline u64 native_read_pmc(int counter) #else static __always_inline u64 read_msr(u32 msr) { - return native_read_msr(msr); + return native_rdmsrq(msr); } =20 static __always_inline int read_msr_safe(u32 msr, u64 *p) @@ -322,7 +311,7 @@ static __always_inline int read_msr_safe(u32 msr, u64 *= p) =20 static __always_inline void write_msr(u32 msr, u64 val) { - native_write_msr(msr, val); + native_wrmsrq(msr, val); } =20 static __always_inline int write_msr_safe(u32 msr, u64 val) diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index fed312a17033..612a512e2a67 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1091,7 +1091,7 @@ static u64 xen_do_read_msr(u32 msr, int *err) if (err) *err =3D native_read_msr_safe(msr, &val); else - val =3D native_read_msr(msr); + val =3D native_rdmsrq(msr); =20 switch (msr) { case MSR_IA32_APICBASE: @@ -1150,7 +1150,7 @@ static void xen_do_write_msr(u32 msr, u64 val, int *e= rr) if (err) *err =3D native_write_msr_safe(msr, val); else - native_write_msr(msr, val); + native_wrmsrq(msr, val); } } =20 --=20 2.53.0