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charset="utf-8" This is the file with the most dramatic effect in terms of DCE, so single it out here. On an AMD-only build: add/remove: 0/1 grow/shrink: 0/5 up/down: 0/-2968 (-2968) Function old new delta opt_gds_mit 1 - -1 symbols_offsets 30776 30772 -4 symbols_sorted_offsets 60712 60704 -8 parse_spec_ctrl 2321 2307 -14 symbols_names 108031 108016 -15 init_speculation_mitigations 9714 6788 -2926 Total: Before=3D3876849, After=3D3873881, chg -0.08% Signed-off-by: Alejandro Vallejo --- xen/arch/x86/spec_ctrl.c | 42 ++++++++++++++++------------------------ 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index dd0413e1fc..246d8895f1 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -388,7 +388,7 @@ int8_t __ro_after_init opt_xpti_domu =3D -1; =20 static __init void xpti_init_default(void) { - if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || + if ( (cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || cpu_has_rdcl_no ) { if ( opt_xpti_hwdom < 0 ) @@ -712,7 +712,7 @@ static bool __init check_smt_enabled(void) * At the time of writing, it is almost completely undocumented, so is= n't * virtualised reliably. */ - if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && + if ( (cpu_vendor() & X86_VENDOR_INTEL) && boot_cpu_data.family !=3D 0xf && !cpu_has_hypervisor && !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, &val) ) return (MASK_EXTR(val, MSR_CTC_CORE_MASK) !=3D @@ -738,11 +738,10 @@ static bool __init retpoline_calculations(void) unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; bool safe =3D false; =20 - if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) return true; =20 - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return false; =20 /* @@ -938,8 +937,7 @@ static bool __init retpoline_calculations(void) */ static bool __init rsb_is_full_width(void) { - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return true; =20 switch ( boot_cpu_data.model ) @@ -966,8 +964,7 @@ static bool __init should_use_eager_fpu(void) * Assume all unrecognised processors are ok. This is only known to * affect Intel Family 6 processors. */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return false; =20 switch ( boot_cpu_data.model ) @@ -1033,7 +1030,7 @@ static bool __init should_use_eager_fpu(void) */ static void __init srso_calculations(bool hw_smt_enabled) { - if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) return; =20 /* @@ -1099,7 +1096,7 @@ static void __init srso_calculations(bool hw_smt_enab= led) */ static bool __init has_div_vuln(void) { - if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) return false; =20 if ( boot_cpu_data.family !=3D 0x17 && boot_cpu_data.family !=3D 0x18 ) @@ -1137,7 +1134,7 @@ static void __init ibpb_calculations(void) return; } =20 - if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) { /* * AMD/Hygon CPUs to date (June 2022) don't flush the RAS. Future @@ -1222,8 +1219,7 @@ static __init void l1tf_calculations(void) l1d_maxphysaddr =3D paddr_bits; =20 /* L1TF is only known to affect Intel Family 6 processors at this time= . */ - if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && - boot_cpu_data.family =3D=3D 6 ) + if ( (cpu_vendor() & X86_VENDOR_INTEL) && boot_cpu_data.family =3D=3D = 6 ) { switch ( boot_cpu_data.model ) { @@ -1358,8 +1354,7 @@ static __init void l1tf_calculations(void) static __init void mds_calculations(void) { /* MDS is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return; =20 /* Any processor advertising MDS_NO should be not vulnerable to MDS. */ @@ -1469,8 +1464,7 @@ static __init void mds_calculations(void) static void __init rfds_calculations(void) { /* RFDS is only known to affect Intel Family 6 processors at this time= . */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return; =20 /* @@ -1535,7 +1529,7 @@ static void __init tsa_calculations(void) unsigned int curr_rev, min_rev; =20 /* TSA is only known to affect AMD processors at this time. */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_AMD ) + if ( !(cpu_vendor() & X86_VENDOR_AMD) ) return; =20 /* If we're virtualised, don't attempt to synthesise anything. */ @@ -1659,8 +1653,7 @@ static void __init gds_calculations(void) bool cpu_has_bug_gds, mitigated =3D false; =20 /* GDS is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return; =20 cpu_has_bug_gds =3D cpu_has_gds(); @@ -1754,8 +1747,7 @@ static void __init gds_calculations(void) static bool __init cpu_has_bug_bhi(void) { /* BHI is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return false; =20 if ( boot_cpu_has(X86_FEATURE_BHI_NO) ) @@ -1878,7 +1870,7 @@ static void __init its_calculations(void) return; =20 /* ITS is only known to affect Intel processors at this time. */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) ) return; =20 /* @@ -2181,7 +2173,7 @@ void __init init_speculation_mitigations(void) * before going idle is less overhead than flushing on PV entry. */ if ( !opt_rsb_pv && hw_smt_enabled && - (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) = && + (cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && (boot_cpu_data.family =3D=3D 0x17 || boot_cpu_data.family =3D= =3D 0x18) ) setup_force_cpu_cap(X86_FEATURE_SC_RSB_IDLE); } --=20 2.43.0