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charset="utf-8" While in principle it's possible to have a vendor virtualising another, this is fairly tricky in practice. Not doing so enables certain optimisations with regards to vendor checks in later patches. Signed-off-by: Alejandro Vallejo --- Patch 1 from the cross-vendor series. Do not merge here. It's simply for consistency. --- xen/lib/x86/policy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xen/lib/x86/policy.c b/xen/lib/x86/policy.c index f033d22785..079c42a29b 100644 --- a/xen/lib/x86/policy.c +++ b/xen/lib/x86/policy.c @@ -15,7 +15,8 @@ int x86_cpu_policies_are_compatible(const struct cpu_poli= cy *host, #define FAIL_MSR(m) \ do { e.msr =3D (m); goto out; } while ( 0 ) =20 - if ( guest->basic.max_leaf > host->basic.max_leaf ) + if ( (guest->x86_vendor !=3D host->x86_vendor) || + (guest->basic.max_leaf > host->basic.max_leaf) ) FAIL_CPUID(0, NA); =20 if ( guest->feat.max_subleaf > host->feat.max_subleaf ) --=20 2.43.0 From nobody Mon Feb 9 21:01:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; 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charset="utf-8" This enables very aggressive DCE passes on single-vendor builds in later patches, as it will allow most vendor checks to become statically chosen branches. A lot of statics go away and a lot more inlining will be allowed. A prerequisite for such optimisation is to expand Kconfig to have the full set of vendors. Adds Hygon, Centaur, Shanghai and the unknown-vendor path. Have Hygon select AMD, and Centaur|Shanghai select Intel. Not a functional change. Signed-off-by: Alejandro Vallejo --- rfc -> v1: * s/depends on/select/ * s/UNKNOWN_CPU/UNKNOWN_CPU_VENDOR/ * Removed "if unsure, say Y" --- xen/arch/x86/Kconfig.cpu | 43 +++++++++++++++++++++++++++++++++++++++ xen/arch/x86/cpu/Makefile | 6 +++--- 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/xen/arch/x86/Kconfig.cpu b/xen/arch/x86/Kconfig.cpu index 5fb18db1aa..f895cfe97a 100644 --- a/xen/arch/x86/Kconfig.cpu +++ b/xen/arch/x86/Kconfig.cpu @@ -19,4 +19,47 @@ config INTEL May be turned off in builds targetting other vendors. Otherwise, must be enabled for Xen to work suitably on Intel platforms. =20 +config HYGON + bool "Support Hygon CPUs" + select AMD + default y + help + Detection, tunings and quirks for Hygon platforms. + + May be turned off in builds targetting other vendors. Otherwise, + must be enabled for Xen to work suitably on Hygon platforms. + + +config CENTAUR + bool "Support Centaur CPUs" + select INTEL + default y + help + Detection, tunings and quirks for Centaur platforms. + + May be turned off in builds targetting other vendors. Otherwise, + must be enabled for Xen to work suitably on Centaur platforms. + +config SHANGHAI + bool "Support Shanghai CPUs" + select INTEL + default y + help + Detection, tunings and quirks for Shanghai platforms. + + May be turned off in builds targetting other vendors. Otherwise, + must be enabled for Xen to work suitably on Shanghai platforms. + +config UNKNOWN_CPU_VENDOR + bool "Support unknown CPU vendors" + default y + help + This option prevents a panic on boot when the host CPU vendor isn't + supported by going into a legacy compatibility mode and not applying + any relevant tunings or quirks. + + Not selecting this options while selecting multiple vendors doesn't have + any major effect on code size, but selecting a single vendor with this + option cleared produces a much smaller build. + endmenu diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile index 7cfe28b7ec..84b060aa41 100644 --- a/xen/arch/x86/cpu/Makefile +++ b/xen/arch/x86/cpu/Makefile @@ -3,13 +3,13 @@ obj-y +=3D microcode/ obj-y +=3D mtrr/ =20 obj-y +=3D amd.o -obj-y +=3D centaur.o +obj-$(CONFIG_CENTAUR) +=3D centaur.o obj-y +=3D common.o -obj-y +=3D hygon.o obj-y +=3D intel.o +obj-$(CONFIG_HYGON) +=3D hygon.o obj-y +=3D intel_cacheinfo.o obj-$(CONFIG_INTEL) +=3D mwait-idle.o -obj-y +=3D shanghai.o +obj-$(CONFIG_SHANGHAI) +=3D shanghai.o obj-y +=3D vpmu.o obj-$(CONFIG_AMD) +=3D vpmu_amd.o obj-$(CONFIG_INTEL) +=3D vpmu_intel.o --=20 2.43.0 From nobody Mon Feb 9 21:01:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Introduces various optimisations that rely on constant folding, Value Range Propagation (VRP), and Dead Code Elimination (DCE) to aggressively eliminate code surrounding the uses of the function. * For single-vendor+no-unknown-vendor builds returns a compile-time constant. * For all other cases it ANDs the result with the mask of compiled vendors, with the effect of performing DCE in switch cases, removing dead conditionals, etc. It's difficult to reason about codegen in general in a project this big, but in this case the ANDed constant combines with the values typically checked against, folding into a comparison against zero. Thus, it's better for codegen to AND its result with the desired compared-against vendor, rather than using (in)equality operators. That way the comparison is always against zero. "cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)" turns into (cpu_vendor() & X86_VENDOR_AMD) in AMD-only builds (AND + cmp with zero). Whereas this... "cpu_vendor() =3D=3D X86_VENDOR_AMD" forces cpu_vendor() to be ANDed and then compared to a non-zero value. Later patches take the opportunity and make this refactor as cpu_vendor() is introduced throughout the tree. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/common.c | 6 +++++- xen/arch/x86/guest/xen/xen.c | 4 ++++ xen/arch/x86/include/asm/cpufeature.h | 27 +++++++++++++++++++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index ebe2baf8b9..6f4e723172 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -328,7 +328,11 @@ void __init early_cpu_init(bool verbose) *(u32 *)&c->x86_vendor_id[4] =3D edx; =20 c->x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx); - switch (c->x86_vendor) { + if ( c->x86_vendor !=3D cpu_vendor() ) + panic("CPU vendor not compiled-in: %s", + x86_cpuid_vendor_to_str(c->x86_vendor)); + + switch (cpu_vendor()) { case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); actual_cpu =3D intel_cpu_dev; break; case X86_VENDOR_AMD: actual_cpu =3D amd_cpu_dev; break; diff --git a/xen/arch/x86/guest/xen/xen.c b/xen/arch/x86/guest/xen/xen.c index 77a3a8742a..ec558bcbdb 100644 --- a/xen/arch/x86/guest/xen/xen.c +++ b/xen/arch/x86/guest/xen/xen.c @@ -57,6 +57,10 @@ void asmlinkage __init early_hypercall_setup(void) cpuid(0, &eax, &ebx, &ecx, &edx); =20 boot_cpu_data.x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx= ); + + if ( cpu_vendor() !=3D boot_cpu_data.x86_vendor ) + panic("CPU vendor not compiled-in: %s", + x86_cpuid_vendor_to_str(boot_cpu_data.x86_vendor)); } =20 switch ( boot_cpu_data.x86_vendor ) diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/a= sm/cpufeature.h index dcd223d84f..10309e40b6 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -14,6 +14,7 @@ #include #include #include +#include #else #include #endif @@ -116,6 +117,32 @@ static inline bool boot_cpu_has(unsigned int feat) =20 #define CPUID_PM_LEAF 6 =20 +#define X86_ENABLED_VENDORS \ + ((IS_ENABLED(CONFIG_INTEL) ? X86_VENDOR_INTEL : 0) | \ + (IS_ENABLED(CONFIG_AMD) ? X86_VENDOR_AMD : 0) | \ + (IS_ENABLED(CONFIG_CENTAUR) ? X86_VENDOR_CENTAUR : 0) | \ + (IS_ENABLED(CONFIG_SHANGHAI) ? X86_VENDOR_SHANGHAI : 0) | \ + (IS_ENABLED(CONFIG_HYGON) ? X86_VENDOR_HYGON : 0)) + +static always_inline uint8_t cpu_vendor(void) +{ + uint8_t vendor =3D boot_cpu_data.vendor; + + /* + * const-ify the CPU vendor if we compiled for a single vendor and the= re's + * no boot path for an unknown vendor. + */ + if ( !IS_ENABLED(CONFIG_UNKNOWN_CPU_VENDOR) && + (ISOLATE_LSB(X86_ENABLED_VENDORS) =3D=3D X86_ENABLED_VENDORS) ) + return X86_ENABLED_VENDORS; + + /* + * This allows the compiler to know more in its VRP pass about the val= id + * range of `vendor`. It enhances DCE by eliminating impossible vendor= s. + */ + return vendor & X86_ENABLED_VENDORS; +} + /* CPUID level 0x00000001.edx */ #define cpu_has_fpu 1 #define cpu_has_de 1 --=20 2.43.0 From nobody Mon Feb 9 21:01:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1770394598; cv=pass; d=zohomail.com; s=zohoarc; b=EzN/oQpFLUqKRUZhJ5Gqa8ZoyP5fwt+7pde5InX8N7tueb4ktVddaWDupY/b748EQpDfv8vJqZdyfyZWUoqEHY5DpuUKMzUa+Yv8P8I+MDEL0Zoj9snl/9w0a01WIeds57C2l3WnU9lb5tLFFJK55YQch4QjQpU3IXtEGUniL0Y= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1770394598; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Many handlers are vendor-specific and are currently gated on runtime checks. If we migrate those to cpu_vendor() they will effectively cause the ellision of handling code for CPU vendors not compiled in. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/msr.c | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index ad75a2e108..34033c1982 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -157,8 +157,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) * The MSR has existed on all Intel parts since before the 64bit d= ays, * and is implemented by other vendors. */ - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR | - X86_VENDOR_SHANGHAI)) ) + if ( !(cpu_vendor() & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR | + X86_VENDOR_SHANGHAI)) ) goto gp_fault; =20 *val =3D IA32_FEATURE_CONTROL_LOCK; @@ -169,8 +169,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) break; =20 case MSR_IA32_PLATFORM_ID: - if ( !(cp->x86_vendor & X86_VENDOR_INTEL) || - !(boot_cpu_data.x86_vendor & X86_VENDOR_INTEL) ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) ) goto gp_fault; rdmsrl(MSR_IA32_PLATFORM_ID, *val); break; @@ -189,9 +188,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) * from Xen's last microcode load, which can be forwarded straight= to * the guest. */ - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || - !(boot_cpu_data.x86_vendor & - (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || + if ( !(cpu_vendor() & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || rdmsr_safe(MSR_AMD_PATCHLEVEL, val) ) goto gp_fault; break; @@ -236,7 +233,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) */ case MSR_IA32_PERF_STATUS: case MSR_IA32_PERF_CTL: - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR)) ) + if ( !(cpu_vendor() & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR)) ) goto gp_fault; =20 *val =3D 0; @@ -245,7 +242,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) goto gp_fault; =20 case MSR_IA32_THERM_STATUS: - if ( cp->x86_vendor !=3D X86_VENDOR_INTEL ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) ) goto gp_fault; *val =3D 0; break; @@ -302,7 +299,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) case MSR_K8_IORR_MASK1: case MSR_K8_TSEG_BASE: case MSR_K8_TSEG_MASK: - if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) goto gp_fault; if ( !is_hardware_domain(d) ) return X86EMUL_UNHANDLEABLE; @@ -314,14 +311,14 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_= t *val) break; =20 case MSR_K8_HWCR: - if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) goto gp_fault; *val =3D 0; break; =20 case MSR_FAM10H_MMIO_CONF_BASE: if ( !is_hardware_domain(d) || - !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || + !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || rdmsr_safe(msr, val) ) goto gp_fault; =20 @@ -338,7 +335,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) break; =20 case MSR_AMD64_DE_CFG: - if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) goto gp_fault; *val =3D AMD64_DE_CFG_LFENCE_SERIALISE; break; @@ -461,7 +458,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * for backwards compatiblity, the OS should write 0 to it before * trying to access the current microcode version. */ - if ( cp->x86_vendor !=3D X86_VENDOR_INTEL || val !=3D 0 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || val !=3D 0 ) goto gp_fault; break; =20 @@ -470,8 +467,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * See note on MSR_IA32_UCODE_WRITE below, which may or may not ap= ply * to AMD CPUs as well (at least the architectural/CPUID part does= ). */ - if ( is_pv_domain(d) || - cp->x86_vendor !=3D X86_VENDOR_AMD ) + if ( is_pv_domain(d) || !(cpu_vendor() & X86_VENDOR_AMD) ) goto gp_fault; break; =20 @@ -482,8 +478,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * for such attempts. Also the MSR is architectural and not qualif= ied * by any CPUID bit. */ - if ( is_pv_domain(d) || - cp->x86_vendor !=3D X86_VENDOR_INTEL ) + if ( is_pv_domain(d) || !(cpu_vendor() & X86_VENDOR_INTEL) ) goto gp_fault; break; =20 @@ -553,7 +548,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * a cpufreq controller dom0 which has full access. */ case MSR_IA32_PERF_CTL: - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR)) ) + if ( !(cpu_vendor() & (X86_VENDOR_INTEL | X86_VENDOR_CENTAUR)) ) goto gp_fault; =20 if ( likely(!is_cpufreq_controller(d)) || wrmsr_safe(msr, val) =3D= =3D 0 ) @@ -663,7 +658,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t = val) * OpenBSD 6.7 will panic if writing to DE_CFG triggers a #GP: * https://www.illumos.org/issues/12998 - drop writes. */ - if ( !(cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) goto gp_fault; break; =20 --=20 2.43.0 From nobody Mon Feb 9 21:01:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" This is the file with the most dramatic effect in terms of DCE, so single it out here. On an AMD-only build: add/remove: 0/1 grow/shrink: 0/5 up/down: 0/-2968 (-2968) Function old new delta opt_gds_mit 1 - -1 symbols_offsets 30776 30772 -4 symbols_sorted_offsets 60712 60704 -8 parse_spec_ctrl 2321 2307 -14 symbols_names 108031 108016 -15 init_speculation_mitigations 9714 6788 -2926 Total: Before=3D3876849, After=3D3873881, chg -0.08% Signed-off-by: Alejandro Vallejo --- xen/arch/x86/spec_ctrl.c | 42 ++++++++++++++++------------------------ 1 file changed, 17 insertions(+), 25 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index dd0413e1fc..246d8895f1 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -388,7 +388,7 @@ int8_t __ro_after_init opt_xpti_domu =3D -1; =20 static __init void xpti_init_default(void) { - if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || + if ( (cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || cpu_has_rdcl_no ) { if ( opt_xpti_hwdom < 0 ) @@ -712,7 +712,7 @@ static bool __init check_smt_enabled(void) * At the time of writing, it is almost completely undocumented, so is= n't * virtualised reliably. */ - if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && + if ( (cpu_vendor() & X86_VENDOR_INTEL) && boot_cpu_data.family !=3D 0xf && !cpu_has_hypervisor && !rdmsr_safe(MSR_INTEL_CORE_THREAD_COUNT, &val) ) return (MASK_EXTR(val, MSR_CTC_CORE_MASK) !=3D @@ -738,11 +738,10 @@ static bool __init retpoline_calculations(void) unsigned int ucode_rev =3D this_cpu(cpu_sig).rev; bool safe =3D false; =20 - if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) return true; =20 - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return false; =20 /* @@ -938,8 +937,7 @@ static bool __init retpoline_calculations(void) */ static bool __init rsb_is_full_width(void) { - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return true; =20 switch ( boot_cpu_data.model ) @@ -966,8 +964,7 @@ static bool __init should_use_eager_fpu(void) * Assume all unrecognised processors are ok. This is only known to * affect Intel Family 6 processors. */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return false; =20 switch ( boot_cpu_data.model ) @@ -1033,7 +1030,7 @@ static bool __init should_use_eager_fpu(void) */ static void __init srso_calculations(bool hw_smt_enabled) { - if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) return; =20 /* @@ -1099,7 +1096,7 @@ static void __init srso_calculations(bool hw_smt_enab= led) */ static bool __init has_div_vuln(void) { - if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) return false; =20 if ( boot_cpu_data.family !=3D 0x17 && boot_cpu_data.family !=3D 0x18 ) @@ -1137,7 +1134,7 @@ static void __init ibpb_calculations(void) return; } =20 - if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) { /* * AMD/Hygon CPUs to date (June 2022) don't flush the RAS. Future @@ -1222,8 +1219,7 @@ static __init void l1tf_calculations(void) l1d_maxphysaddr =3D paddr_bits; =20 /* L1TF is only known to affect Intel Family 6 processors at this time= . */ - if ( boot_cpu_data.vendor =3D=3D X86_VENDOR_INTEL && - boot_cpu_data.family =3D=3D 6 ) + if ( (cpu_vendor() & X86_VENDOR_INTEL) && boot_cpu_data.family =3D=3D = 6 ) { switch ( boot_cpu_data.model ) { @@ -1358,8 +1354,7 @@ static __init void l1tf_calculations(void) static __init void mds_calculations(void) { /* MDS is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return; =20 /* Any processor advertising MDS_NO should be not vulnerable to MDS. */ @@ -1469,8 +1464,7 @@ static __init void mds_calculations(void) static void __init rfds_calculations(void) { /* RFDS is only known to affect Intel Family 6 processors at this time= . */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return; =20 /* @@ -1535,7 +1529,7 @@ static void __init tsa_calculations(void) unsigned int curr_rev, min_rev; =20 /* TSA is only known to affect AMD processors at this time. */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_AMD ) + if ( !(cpu_vendor() & X86_VENDOR_AMD) ) return; =20 /* If we're virtualised, don't attempt to synthesise anything. */ @@ -1659,8 +1653,7 @@ static void __init gds_calculations(void) bool cpu_has_bug_gds, mitigated =3D false; =20 /* GDS is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return; =20 cpu_has_bug_gds =3D cpu_has_gds(); @@ -1754,8 +1747,7 @@ static void __init gds_calculations(void) static bool __init cpu_has_bug_bhi(void) { /* BHI is only known to affect Intel Family 6 processors at this time.= */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.family !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.family !=3D 6= ) return false; =20 if ( boot_cpu_has(X86_FEATURE_BHI_NO) ) @@ -1878,7 +1870,7 @@ static void __init its_calculations(void) return; =20 /* ITS is only known to affect Intel processors at this time. */ - if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) ) return; =20 /* @@ -2181,7 +2173,7 @@ void __init init_speculation_mitigations(void) * before going idle is less overhead than flushing on PV entry. */ if ( !opt_rsb_pv && hw_smt_enabled && - (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) = && + (cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && (boot_cpu_data.family =3D=3D 0x17 || boot_cpu_data.family =3D= =3D 0x18) ) setup_force_cpu_cap(X86_FEATURE_SC_RSB_IDLE); } --=20 2.43.0 From nobody Mon Feb 9 21:01:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" In the single-vendor case (with no unknown vendor) all switches turn to a branchless straight line through the single compiled-in case. In the multivendor case where some vendors are disabled the VRP pass ensures those branches are eliminated. It's hard to tell the VRP pass zero is also unreachable when CONFIG_UNKNOWN_CPU_VENDORS is disabled, so default cases tend to remain. Signed-off-by: Alejandro Vallejo --- The removals of ifdefs are proof of VRP doing the work of DCE. --- xen/arch/x86/acpi/cpufreq/cpufreq.c | 12 +++--------- xen/arch/x86/alternative.c | 2 +- xen/arch/x86/cpu-policy.c | 6 +++--- xen/arch/x86/cpu/mcheck/mce.c | 6 +----- xen/arch/x86/cpu/mcheck/mce.h | 2 +- xen/arch/x86/cpu/mcheck/non-fatal.c | 6 +----- xen/arch/x86/cpu/mcheck/vmce.c | 12 ++---------- xen/arch/x86/cpu/vpmu.c | 6 +----- xen/arch/x86/domain.c | 4 ++-- xen/arch/x86/guest/xen/xen.c | 2 +- xen/arch/x86/nmi.c | 4 ++-- xen/arch/x86/traps-setup.c | 2 +- 12 files changed, 19 insertions(+), 45 deletions(-) diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufre= q/cpufreq.c index 5740c0d438..4ee03ecc65 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -133,7 +133,7 @@ static int __init cf_check cpufreq_driver_init(void) =20 ret =3D -ENOENT; =20 - switch ( boot_cpu_data.x86_vendor ) + switch( cpu_vendor() ) { case X86_VENDOR_INTEL: for ( i =3D 0; i < cpufreq_xen_cnt; i++ ) @@ -141,12 +141,10 @@ static int __init cf_check cpufreq_driver_init(void) switch ( cpufreq_xen_opts[i] ) { case CPUFREQ_xen: - ret =3D IS_ENABLED(CONFIG_INTEL) ? - acpi_cpufreq_register() : -ENODEV; + ret =3D acpi_cpufreq_register(); break; case CPUFREQ_hwp: - ret =3D IS_ENABLED(CONFIG_INTEL) ? - hwp_register_driver() : -ENODEV; + ret =3D hwp_register_driver(); break; case CPUFREQ_none: ret =3D 0; @@ -165,7 +163,6 @@ static int __init cf_check cpufreq_driver_init(void) =20 case X86_VENDOR_AMD: case X86_VENDOR_HYGON: -#ifdef CONFIG_AMD for ( i =3D 0; i < cpufreq_xen_cnt; i++ ) { switch ( cpufreq_xen_opts[i] ) @@ -191,9 +188,6 @@ static int __init cf_check cpufreq_driver_init(void) if ( !ret || ret =3D=3D -EBUSY ) break; } -#else - ret =3D -ENODEV; -#endif /* CONFIG_AMD */ break; =20 default: diff --git a/xen/arch/x86/alternative.c b/xen/arch/x86/alternative.c index 9f844241bc..c723417807 100644 --- a/xen/arch/x86/alternative.c +++ b/xen/arch/x86/alternative.c @@ -89,7 +89,7 @@ static bool init_or_livepatch_read_mostly toolchain_nops_= are_ideal; =20 static void __init arch_init_ideal_nops(void) { - switch ( boot_cpu_data.x86_vendor ) + switch ( cpu_vendor() ) { case X86_VENDOR_INTEL: /* diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 5273fe0ae4..62aff61d8c 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -279,7 +279,7 @@ static void recalculate_misc(struct cpu_policy *p) =20 p->extd.raw[0x8].d =3D 0; =20 - switch ( p->x86_vendor ) + switch ( cpu_vendor() ) { case X86_VENDOR_INTEL: p->basic.l2_nr_queries =3D 1; /* Fixed to 1 query. */ @@ -420,7 +420,7 @@ static void __init guest_common_default_leaves(struct c= pu_policy *p) =20 static void __init guest_common_max_feature_adjustments(uint32_t *fs) { - switch ( boot_cpu_data.vendor ) + switch ( cpu_vendor() ) { case X86_VENDOR_INTEL: /* @@ -514,7 +514,7 @@ static void __init guest_common_max_feature_adjustments= (uint32_t *fs) =20 static void __init guest_common_default_feature_adjustments(uint32_t *fs) { - switch ( boot_cpu_data.vendor ) + switch ( cpu_vendor() ) { case X86_VENDOR_INTEL: /* diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 9277781bff..4b295aeeb5 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -766,16 +766,13 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) else if ( cpu_bank_alloc(cpu) ) panic("Insufficient memory for MCE bank allocations\n"); =20 - switch ( c->x86_vendor ) + switch ( cpu_vendor() ) { -#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: inited =3D amd_mcheck_init(c, bsp); break; -#endif =20 -#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: switch ( c->x86 ) { @@ -785,7 +782,6 @@ void mcheck_init(struct cpuinfo_x86 *c, bool bsp) break; } break; -#endif =20 default: break; diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 920b075355..4828c74d47 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -137,7 +137,7 @@ void x86_mcinfo_dump(struct mc_info *mi); =20 static inline int mce_vendor_bank_msr(const struct vcpu *v, uint32_t msr) { - switch (boot_cpu_data.x86_vendor) { + switch (cpu_vendor()) { case X86_VENDOR_INTEL: if (msr >=3D MSR_IA32_MC0_CTL2 && msr < MSR_IA32_MCx_CTL2(v->arch.vmce.mcg_cap & MCG_CAP_COUNT) ) diff --git a/xen/arch/x86/cpu/mcheck/non-fatal.c b/xen/arch/x86/cpu/mcheck/= non-fatal.c index a9ee9bb94f..3a0399c121 100644 --- a/xen/arch/x86/cpu/mcheck/non-fatal.c +++ b/xen/arch/x86/cpu/mcheck/non-fatal.c @@ -23,20 +23,16 @@ static int __init cf_check init_nonfatal_mce_checker(vo= id) /* * Check for non-fatal errors every MCE_RATE s */ - switch (c->x86_vendor) { -#ifdef CONFIG_AMD + switch (cpu_vendor()) { case X86_VENDOR_AMD: case X86_VENDOR_HYGON: /* Assume we are on K8 or newer AMD or Hygon CPU here */ amd_nonfatal_mcheck_init(c); break; -#endif =20 -#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: intel_nonfatal_mcheck_init(c); break; -#endif =20 default: /* unhandled vendor isn't really an error */ diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 1a7e92506a..0c1bfb691b 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -136,22 +136,18 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint3= 2_t msr, uint64_t *val) break; =20 default: - switch ( boot_cpu_data.x86_vendor ) + switch ( cpu_vendor() ) { -#ifdef CONFIG_INTEL case X86_VENDOR_CENTAUR: case X86_VENDOR_SHANGHAI: case X86_VENDOR_INTEL: ret =3D vmce_intel_rdmsr(v, msr, val); break; -#endif =20 -#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: ret =3D vmce_amd_rdmsr(v, msr, val); break; -#endif =20 default: ret =3D 0; @@ -273,20 +269,16 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t ms= r, uint64_t val) break; =20 default: - switch ( boot_cpu_data.x86_vendor ) + switch ( cpu_vendor() ) { -#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: ret =3D vmce_intel_wrmsr(v, msr, val); break; -#endif =20 -#ifdef CONFIG_AMD case X86_VENDOR_AMD: case X86_VENDOR_HYGON: ret =3D vmce_amd_wrmsr(v, msr, val); break; -#endif =20 default: ret =3D 0; diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c index c28192ea26..b1ad4ebcf6 100644 --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -815,7 +815,7 @@ static struct notifier_block cpu_nfb =3D { =20 static int __init cf_check vpmu_init(void) { - int vendor =3D current_cpu_data.x86_vendor; + int vendor =3D cpu_vendor(); const struct arch_vpmu_ops *ops =3D NULL; =20 if ( !opt_vpmu_enabled ) @@ -832,7 +832,6 @@ static int __init cf_check vpmu_init(void) =20 switch ( vendor ) { -#ifdef CONFIG_AMD case X86_VENDOR_AMD: ops =3D amd_vpmu_init(); break; @@ -840,13 +839,10 @@ static int __init cf_check vpmu_init(void) case X86_VENDOR_HYGON: ops =3D hygon_vpmu_init(); break; -#endif =20 -#ifdef CONFIG_INTEL case X86_VENDOR_INTEL: ops =3D core2_vpmu_init(); break; -#endif =20 default: printk(XENLOG_WARNING "VPMU: Unknown CPU vendor: %d. " diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 8b2f33f1a0..10a558e515 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -319,7 +319,7 @@ void domain_cpu_policy_changed(struct domain *d) if ( cpu_has_htt ) edx |=3D cpufeat_mask(X86_FEATURE_HTT); =20 - switch ( boot_cpu_data.x86_vendor ) + switch( cpu_vendor() ) { case X86_VENDOR_INTEL: /* @@ -427,7 +427,7 @@ void domain_cpu_policy_changed(struct domain *d) if ( !(p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) edx &=3D ~CPUID_COMMON_1D_FEATURES; =20 - switch ( boot_cpu_data.x86_vendor ) + switch( cpu_vendor() ) { case X86_VENDOR_INTEL: mask &=3D ((uint64_t)edx << 32) | ecx; diff --git a/xen/arch/x86/guest/xen/xen.c b/xen/arch/x86/guest/xen/xen.c index ec558bcbdb..590a4bad82 100644 --- a/xen/arch/x86/guest/xen/xen.c +++ b/xen/arch/x86/guest/xen/xen.c @@ -63,7 +63,7 @@ void asmlinkage __init early_hypercall_setup(void) x86_cpuid_vendor_to_str(boot_cpu_data.x86_vendor)); } =20 - switch ( boot_cpu_data.x86_vendor ) + switch ( cpu_vendor() ) { case X86_VENDOR_INTEL: case X86_VENDOR_CENTAUR: diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c index a0c9194ff0..a3ba59ce0b 100644 --- a/xen/arch/x86/nmi.c +++ b/xen/arch/x86/nmi.c @@ -216,7 +216,7 @@ void disable_lapic_nmi_watchdog(void) { if (nmi_active <=3D 0) return; - switch (boot_cpu_data.x86_vendor) { + switch(cpu_vendor()) { case X86_VENDOR_AMD: wrmsrns(MSR_K7_EVNTSEL0, 0); break; @@ -387,7 +387,7 @@ void setup_apic_nmi_watchdog(void) if ( nmi_watchdog =3D=3D NMI_NONE ) return; =20 - switch ( boot_cpu_data.x86_vendor ) + switch( cpu_vendor() ) { case X86_VENDOR_AMD: setup_k7_watchdog(); diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index d77be8f839..7d7554a7ba 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -243,7 +243,7 @@ static void __init init_ler(void) * Intel Pentium 4 is the only known CPU to not use the architectural = MSR * indicies. */ - switch ( boot_cpu_data.x86_vendor ) + switch( cpu_vendor() ) { case X86_VENDOR_INTEL: if ( boot_cpu_data.x86 =3D=3D 0xf ) --=20 2.43.0 From nobody Mon Feb 9 21:01:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" Open code the vendor check through the policy as a one-off. The emulator embeds amd_like() in macros and is called in MANY places. Using a local variable (cp->x86_vendor) makes it a lot smaller (300-400 bytes smaller). So treat this as the exception it is and let it use the policy rather than boot_cpu_data. Also keep the current behaviour of using the policy vendor when compiled for userspace, where cross-vendor configurations are expected. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/x86_emulate/private.h | 10 +++++++++- xen/arch/x86/x86_emulate/x86_emulate.c | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/= private.h index 24c79c4e8f..95f2015c44 100644 --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -15,6 +15,7 @@ # include =20 # include +# include # include # include # include @@ -30,8 +31,15 @@ void BUG(void); # define X86EMUL_NO_SIMD # endif =20 +/* intentionally avoid cpu_vendor(), as it produces much worse codegen */ +# define x86emul_cpu(cp) ((X86_ENABLED_VENDORS =3D=3D \ + ISOLATE_LSB(X86_ENABLED_VENDORS)) \ + ? X86_ENABLED_VENDORS \ + : ((cp)->x86_vendor & X86_ENABLED_VENDORS)) + #else /* !__XEN__ */ # include "x86-emulate.h" +# define x86emul_cpu(cp) ((cp)->x86_vendor) #endif =20 #ifdef __i386__ @@ -520,7 +528,7 @@ in_protmode( static inline bool _amd_like(const struct cpu_policy *cp) { - return cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON); + return x86emul_cpu(cp) & (X86_VENDOR_AMD | X86_VENDOR_HYGON); } =20 static inline bool diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emul= ate/x86_emulate.c index 7751a67130..308ec3579f 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -3104,7 +3104,7 @@ x86_emulate( * in fact risking to make guest OSes vulnerable to the equivalent= of * XSA-7 (CVE-2012-0217). */ - generate_exception_if(cp->x86_vendor =3D=3D X86_VENDOR_INTEL && + generate_exception_if((x86emul_cpu(cp) & X86_VENDOR_INTEL) && op_bytes =3D=3D 8 && !is_canonical_address(_= regs.rcx), X86_EXC_GP, 0); #endif --=20 2.43.0 From nobody Mon Feb 9 21:01:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" ... but keep the current behaviour of using the policy vendor when compiled for userspace, where cross-vendor configurations are expected. Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/x86_emulate/private.h | 6 +++++- xen/arch/x86/x86_emulate/x86_emulate.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/x86_emulate/private.h b/xen/arch/x86/x86_emulate/= private.h index 24c79c4e8f..1b6fc48ab6 100644 --- a/xen/arch/x86/x86_emulate/private.h +++ b/xen/arch/x86/x86_emulate/private.h @@ -15,6 +15,7 @@ # include =20 # include +# include # include # include # include @@ -30,8 +31,11 @@ void BUG(void); # define X86EMUL_NO_SIMD # endif =20 +# define x86emul_cpu(cp) ({ (void)(cp); cpu_vendor(); }) + #else /* !__XEN__ */ # include "x86-emulate.h" +# define x86emul_cpu(cp) ((cp)->x86_vendor) #endif =20 #ifdef __i386__ @@ -520,7 +524,7 @@ in_protmode( static inline bool _amd_like(const struct cpu_policy *cp) { - return cp->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON); + return x86emul_cpu(cp) & (X86_VENDOR_AMD | X86_VENDOR_HYGON); } =20 static inline bool diff --git a/xen/arch/x86/x86_emulate/x86_emulate.c b/xen/arch/x86/x86_emul= ate/x86_emulate.c index 7751a67130..fcd8cbccc9 100644 --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -3104,7 +3104,7 @@ x86_emulate( * in fact risking to make guest OSes vulnerable to the equivalent= of * XSA-7 (CVE-2012-0217). */ - generate_exception_if(cp->x86_vendor =3D=3D X86_VENDOR_INTEL && + generate_exception_if((x86emul_cpu(cp) =3D=3D X86_VENDOR_INTEL) && op_bytes =3D=3D 8 && !is_canonical_address(_= regs.rcx), X86_EXC_GP, 0); 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charset="utf-8" Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/acpi/cpu_idle.c | 16 +++++++--------- xen/arch/x86/acpi/cpufreq/acpi.c | 2 +- xen/arch/x86/acpi/cpufreq/cpufreq.c | 3 +-- 3 files changed, 9 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 0b3d0631dd..0a49b2730b 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -178,7 +178,7 @@ static void cf_check do_get_hw_residencies(void *arg) struct cpuinfo_x86 *c =3D ¤t_cpu_data; struct hw_residencies *hw_res =3D arg; =20 - if ( c->x86_vendor !=3D X86_VENDOR_INTEL || c->x86 !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || c->x86 !=3D 6 ) return; =20 switch ( c->x86_model ) @@ -915,8 +915,7 @@ void cf_check acpi_dead_idle(void) mwait(cx->address, 0); } } - else if ( (current_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && + else if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) && cx->entry_method =3D=3D ACPI_CSTATE_EM_SYSIO ) { /* Intel prefers not to use SYSIO */ @@ -1042,8 +1041,8 @@ static void acpi_processor_power_init_bm_check(struct= acpi_processor_flags *flag flags->bm_check =3D 0; if ( num_online_cpus() =3D=3D 1 ) flags->bm_check =3D 1; - else if ( (c->x86_vendor =3D=3D X86_VENDOR_INTEL) || - ((c->x86_vendor =3D=3D X86_VENDOR_AMD) && (c->x86 =3D=3D 0x1= 5)) ) + else if ( (cpu_vendor() & X86_VENDOR_INTEL) || + ((cpu_vendor() & X86_VENDOR_AMD) && c->x86 =3D=3D 0x15) ) { /* * Today all MP CPUs that support C3 share cache. @@ -1059,7 +1058,7 @@ static void acpi_processor_power_init_bm_check(struct= acpi_processor_flags *flag * is not required while entering C3 type state on * P4, Core and beyond CPUs */ - if ( c->x86_vendor =3D=3D X86_VENDOR_INTEL && + if ( (cpu_vendor() & X86_VENDOR_INTEL) && (c->x86 > 0x6 || (c->x86 =3D=3D 6 && c->x86_model >=3D 14)) ) flags->bm_control =3D 0; } @@ -1421,7 +1420,7 @@ static void amd_cpuidle_init(struct acpi_processor_po= wer *power) case 0x1a: case 0x19: case 0x18: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_HYGON ) + if ( !(cpu_vendor() & X86_VENDOR_HYGON) ) { default: vendor_override =3D -1; @@ -1648,8 +1647,7 @@ static int cf_check cpu_callback( break; =20 case CPU_ONLINE: - if ( (boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) && processor_powers[cpu] ) amd_cpuidle_init(processor_powers[cpu]); break; diff --git a/xen/arch/x86/acpi/cpufreq/acpi.c b/xen/arch/x86/acpi/cpufreq/a= cpi.c index d0ca660db1..a5e5c223b3 100644 --- a/xen/arch/x86/acpi/cpufreq/acpi.c +++ b/xen/arch/x86/acpi/cpufreq/acpi.c @@ -454,7 +454,7 @@ static int cf_check acpi_cpufreq_cpu_init(struct cpufre= q_policy *policy) =20 /* Check for APERF/MPERF support in hardware * also check for boost support */ - if (c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->cpuid_level >=3D 6) + if ((cpu_vendor() & X86_VENDOR_INTEL) && c->cpuid_level >=3D 6) on_selected_cpus(cpumask_of(cpu), feature_detect, policy, 1); =20 /* diff --git a/xen/arch/x86/acpi/cpufreq/cpufreq.c b/xen/arch/x86/acpi/cpufre= q/cpufreq.c index 4ee03ecc65..d731a21644 100644 --- a/xen/arch/x86/acpi/cpufreq/cpufreq.c +++ b/xen/arch/x86/acpi/cpufreq/cpufreq.c @@ -246,8 +246,7 @@ __initcall(cpufreq_driver_late_init); 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charset="utf-8" Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/pv/domain.c | 2 +- xen/arch/x86/pv/emul-priv-op.c | 27 ++++++++++++--------------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/pv/domain.c b/xen/arch/x86/pv/domain.c index d16583a745..7084274dff 100644 --- a/xen/arch/x86/pv/domain.c +++ b/xen/arch/x86/pv/domain.c @@ -174,7 +174,7 @@ static int __init cf_check pge_init(void) { if ( opt_global_pages =3D=3D -1 ) opt_global_pages =3D !cpu_has_hypervisor || - !(boot_cpu_data.x86_vendor & + !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)); =20 return 0; diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c index 1d9e57ad27..02b6e8f01f 100644 --- a/xen/arch/x86/pv/emul-priv-op.c +++ b/xen/arch/x86/pv/emul-priv-op.c @@ -243,8 +243,7 @@ static bool pci_cfg_ok(struct domain *currd, unsigned i= nt start, } start |=3D CF8_ADDR_LO(currd->arch.pci_cf8); /* AMD extended configuration space access? */ - if ( CF8_ADDR_HI(currd->arch.pci_cf8) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD && + if ( CF8_ADDR_HI(currd->arch.pci_cf8) && (cpu_vendor() & X86_VENDOR_AM= D) && boot_cpu_data.x86 >=3D 0x10 && boot_cpu_data.x86 < 0x17 ) { uint64_t msr_val; @@ -869,8 +868,7 @@ static uint64_t guest_efer(const struct domain *d) */ if ( is_pv_32bit_domain(d) ) val &=3D ~(EFER_LME | EFER_LMA | - (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL - ? EFER_SCE : 0)); + ((cpu_vendor() & X86_VENDOR_INTEL) ? EFER_SCE : 0)); return val; } =20 @@ -958,7 +956,7 @@ static int cf_check read_msr( case MSR_K8_PSTATE5: case MSR_K8_PSTATE6: case MSR_K8_PSTATE7: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD ) + if ( !(cpu_vendor() & X86_VENDOR_AMD) ) break; if ( unlikely(is_cpufreq_controller(currd)) ) goto normal; @@ -966,7 +964,7 @@ static int cf_check read_msr( return X86EMUL_OKAY; =20 case MSR_FAM10H_MMIO_CONF_BASE: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD || + if ( !(cpu_vendor() & X86_VENDOR_AMD) || boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >=3D 0x17 ) break; /* fall through */ @@ -991,13 +989,13 @@ static int cf_check read_msr( case MSR_P6_EVNTSEL(0) ... MSR_P6_EVNTSEL(3): case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR2: case MSR_CORE_PERF_FIXED_CTR_CTRL ... MSR_CORE_PERF_GLOBAL_OVF_CTRL: - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( cpu_vendor() & X86_VENDOR_INTEL ) { vpmu_msr =3D true; /* fall through */ case MSR_AMD_FAM15H_EVNTSEL0 ... MSR_AMD_FAM15H_PERFCTR5: case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: - if ( vpmu_msr || (boot_cpu_data.x86_vendor & + if ( vpmu_msr || (cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) { if ( vpmu_do_rdmsr(reg, val) ) @@ -1100,8 +1098,7 @@ static int cf_check write_msr( case MSR_K8_PSTATE6: case MSR_K8_PSTATE7: case MSR_K8_HWCR: - if ( !(boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) break; if ( likely(!is_cpufreq_controller(currd)) || wrmsr_safe(reg, val) =3D=3D 0 ) @@ -1119,7 +1116,7 @@ static int cf_check write_msr( break; =20 case MSR_FAM10H_MMIO_CONF_BASE: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_AMD || + if ( !(cpu_vendor() & X86_VENDOR_AMD) || boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 >=3D 0x17 ) break; if ( !is_hwdom_pinned_vcpu(curr) ) @@ -1148,7 +1145,7 @@ static int cf_check write_msr( =20 case MSR_IA32_MPERF: case MSR_IA32_APERF: - if ( !(boot_cpu_data.x86_vendor & + if ( !(cpu_vendor() & (X86_VENDOR_INTEL | X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) break; if ( likely(!is_cpufreq_controller(currd)) || @@ -1158,7 +1155,7 @@ static int cf_check write_msr( =20 case MSR_IA32_THERM_CONTROL: case MSR_IA32_ENERGY_PERF_BIAS: - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) ) break; if ( !is_hwdom_pinned_vcpu(curr) || wrmsr_safe(reg, val) =3D=3D 0 ) return X86EMUL_OKAY; @@ -1168,12 +1165,12 @@ static int cf_check write_msr( case MSR_P6_EVNTSEL(0) ... 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charset="utf-8" Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 2 +- xen/arch/x86/cpu/mcheck/mcaction.c | 2 +- xen/arch/x86/cpu/mcheck/mce.c | 17 ++++++++--------- xen/arch/x86/cpu/mcheck/mce_amd.c | 7 +++---- xen/arch/x86/cpu/mcheck/mce_intel.c | 7 +++---- xen/arch/x86/cpu/mcheck/vmce.c | 4 ++-- 6 files changed, 18 insertions(+), 21 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c b/xen/arch/x86/cpu/mche= ck/amd_nonfatal.c index 7d48c9ab5f..ebe13911ba 100644 --- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c +++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c @@ -191,7 +191,7 @@ static void cf_check mce_amd_work_fn(void *data) =20 void __init amd_nonfatal_mcheck_init(struct cpuinfo_x86 *c) { - if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) + if (!(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) return; =20 /* Assume we are on K8 or newer AMD or Hygon CPU here */ diff --git a/xen/arch/x86/cpu/mcheck/mcaction.c b/xen/arch/x86/cpu/mcheck/m= caction.c index bf7a0de965..b7fc5056d8 100644 --- a/xen/arch/x86/cpu/mcheck/mcaction.c +++ b/xen/arch/x86/cpu/mcheck/mcaction.c @@ -101,7 +101,7 @@ mc_memerr_dhandler(struct mca_binfo *binfo, * not always precise. In that case, fallback to broa= dcast. */ global->mc_domid !=3D bank->mc_domid || - (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + ((cpu_vendor() & X86_VENDOR_INTEL) && (!(global->mc_gstatus & MCG_STATUS_LMCE) || !(d->vcpu[mc_vcpuid]->arch.vmce.mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN))) ) diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c index 4b295aeeb5..91c5033edb 100644 --- a/xen/arch/x86/cpu/mcheck/mce.c +++ b/xen/arch/x86/cpu/mcheck/mce.c @@ -333,8 +333,7 @@ mcheck_mca_logout(enum mca_source who, struct mca_banks= *bankmask, ASSERT(mig); mca_init_global(mc_flags, mig); /* A hook here to get global extended msrs */ - if ( IS_ENABLED(CONFIG_INTEL) && - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( cpu_vendor() & X86_VENDOR_INTEL ) intel_get_extended_msrs(mig, mci); } } @@ -564,8 +563,8 @@ bool mce_available(const struct cpuinfo_x86 *c) */ unsigned int mce_firstbank(struct cpuinfo_x86 *c) { - return c->x86 =3D=3D 6 && - c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->x86_model < 0x1a; + return (cpu_vendor() & X86_VENDOR_INTEL) && + c->x86 =3D=3D 6 && c->x86_model < 0x1a; } =20 static int show_mca_info(int inited, struct cpuinfo_x86 *c) @@ -862,7 +861,7 @@ static void x86_mcinfo_apei_save( memset(&m, 0, sizeof(struct mce)); =20 m.cpu =3D mc_global->mc_coreid; - m.cpuvendor =3D boot_cpu_data.x86_vendor; + m.cpuvendor =3D cpu_vendor(); m.cpuid =3D cpuid_eax(1); m.socketid =3D mc_global->mc_socketid; m.apicid =3D mc_global->mc_apicid; @@ -964,7 +963,7 @@ static void cf_check __maybe_unused do_mc_get_cpu_info(= void *v) &xcp->mc_ncores_active, &xcp->mc_nthreads); xcp->mc_cpuid_level =3D c->cpuid_level; xcp->mc_family =3D c->x86; - xcp->mc_vendor =3D c->x86_vendor; + xcp->mc_vendor =3D cpu_vendor(); xcp->mc_model =3D c->x86_model; xcp->mc_step =3D c->x86_mask; xcp->mc_cache_size =3D c->x86_cache_size; @@ -1122,7 +1121,7 @@ static bool __maybe_unused x86_mc_msrinject_verify(st= ruct xen_mc_msrinject *mci) =20 if ( IS_MCA_BANKREG(reg, mci->mcinj_cpunr) ) { - if ( c->x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( (cpu_vendor() & X86_VENDOR_AMD) ) { /* * On AMD we can set MCi_STATUS_WREN in the @@ -1157,7 +1156,7 @@ static bool __maybe_unused x86_mc_msrinject_verify(st= ruct xen_mc_msrinject *mci) case MSR_F10_MC4_MISC1: case MSR_F10_MC4_MISC2: case MSR_F10_MC4_MISC3: - if ( c->x86_vendor !=3D X86_VENDOR_AMD ) + if ( !(cpu_vendor() & X86_VENDOR_AMD) ) reason =3D "only supported on AMD"; else if ( c->x86 < 0x10 ) reason =3D "only supported on AMD Fam10h+"; @@ -1165,7 +1164,7 @@ static bool __maybe_unused x86_mc_msrinject_verify(st= ruct xen_mc_msrinject *mci) =20 /* MSRs that the HV will take care of */ case MSR_K8_HWCR: - if ( c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) reason =3D "HV will operate HWCR"; else reason =3D "only supported on AMD or Hygon"; diff --git a/xen/arch/x86/cpu/mcheck/mce_amd.c b/xen/arch/x86/cpu/mcheck/mc= e_amd.c index 25c29eb3d2..b4d09fd6c1 100644 --- a/xen/arch/x86/cpu/mcheck/mce_amd.c +++ b/xen/arch/x86/cpu/mcheck/mce_amd.c @@ -160,7 +160,7 @@ mcequirk_lookup_amd_quirkdata(const struct cpuinfo_x86 = *c) { unsigned int i; =20 - BUG_ON(c->x86_vendor !=3D X86_VENDOR_AMD); + BUG_ON(!(cpu_vendor() & X86_VENDOR_AMD)); =20 for ( i =3D 0; i < ARRAY_SIZE(mce_amd_quirks); i++ ) { @@ -291,7 +291,7 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp) uint32_t i; enum mcequirk_amd_flags quirkflag =3D 0; =20 - if ( c->x86_vendor !=3D X86_VENDOR_HYGON ) + if ( !(cpu_vendor() & X86_VENDOR_HYGON) ) quirkflag =3D mcequirk_lookup_amd_quirkdata(c); =20 /* Assume that machine check support is available. @@ -337,6 +337,5 @@ amd_mcheck_init(const struct cpuinfo_x86 *c, bool bsp) ppin_msr =3D MSR_AMD_PPIN; } =20 - return c->x86_vendor =3D=3D X86_VENDOR_HYGON ? - mcheck_hygon : mcheck_amd_famXX; + return (cpu_vendor() & X86_VENDOR_HYGON) ? mcheck_hygon : mcheck_amd_f= amXX; } diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/= mce_intel.c index 839a0e5ba9..90dbb60236 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -711,8 +711,8 @@ static bool mce_is_broadcast(struct cpuinfo_x86 *c) * DisplayFamily_DisplayModel encoding of 06H_EH and above, * a MCA signal is broadcast to all logical processors in the system */ - if ( c->x86_vendor =3D=3D X86_VENDOR_INTEL && c->x86 =3D=3D 6 && - c->x86_model >=3D 0xe ) + if ( (cpu_vendor() & X86_VENDOR_INTEL) && + c->x86 =3D=3D 6 && c->x86_model >=3D 0xe ) return true; return false; } @@ -1018,7 +1018,6 @@ int vmce_intel_wrmsr(struct vcpu *v, uint32_t msr, ui= nt64_t val) =20 int vmce_intel_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) { - const struct cpu_policy *cp =3D v->domain->arch.cpu_policy; unsigned int bank =3D msr - MSR_IA32_MC0_CTL2; =20 switch ( msr ) @@ -1036,7 +1035,7 @@ int vmce_intel_rdmsr(const struct vcpu *v, uint32_t m= sr, uint64_t *val) return 1; } =20 - if ( !(cp->x86_vendor & X86_VENDOR_INTEL) ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) ) return 0; =20 if ( bank < GUEST_MC_BANK_NUM ) diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 0c1bfb691b..393bf8c787 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -45,7 +45,7 @@ void vmce_init_vcpu(struct vcpu *v) int i; =20 /* global MCA MSRs init */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( cpu_vendor() & X86_VENDOR_INTEL ) v->arch.vmce.mcg_cap =3D INTEL_GUEST_MCG_CAP; else v->arch.vmce.mcg_cap =3D AMD_GUEST_MCG_CAP; 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charset="utf-8" Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/amd.c | 6 +++--- xen/arch/x86/cpu/common.c | 2 +- xen/arch/x86/cpu/intel_cacheinfo.c | 5 ++--- xen/arch/x86/cpu/microcode/amd.c | 2 +- xen/arch/x86/cpu/microcode/core.c | 2 +- xen/arch/x86/cpu/mtrr/generic.c | 5 ++--- xen/arch/x86/cpu/mwait-idle.c | 5 ++--- xen/arch/x86/cpu/vpmu.c | 3 +-- 8 files changed, 13 insertions(+), 17 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index fc496dc43e..422d81472e 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -327,7 +327,7 @@ int cpu_has_amd_erratum(const struct cpuinfo_x86 *cpu, = int osvw_id, ...) u32 range; u32 ms; =09 - if (cpu->x86_vendor !=3D X86_VENDOR_AMD) + if (!(cpu_vendor() & X86_VENDOR_AMD)) return 0; =20 if (osvw_id >=3D 0 && cpu_has(cpu, X86_FEATURE_OSVW)) { @@ -418,8 +418,8 @@ static void check_syscfg_dram_mod_en(void) { uint64_t syscfg; =20 - if (!((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) && - (boot_cpu_data.x86 >=3D 0x0f))) + if (!((cpu_vendor() & X86_VENDOR_AMD) && + (boot_cpu_data.x86 >=3D 0x0f))) return; =20 rdmsrl(MSR_K8_SYSCFG, syscfg); diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 6f4e723172..9a6fb90fec 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -436,7 +436,7 @@ void __init early_cpu_init(bool verbose) paddr_bits -=3D (ebx >> 6) & 0x3f; } =20 - if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) + if (!(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) park_offline_cpus =3D opt_mce; =20 initialize_cpu_data(0); diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_ca= cheinfo.c index e88faa7545..f95ed90809 100644 --- a/xen/arch/x86/cpu/intel_cacheinfo.c +++ b/xen/arch/x86/cpu/intel_cacheinfo.c @@ -168,9 +168,8 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for * trace cache */ - if ((num_cache_leaves =3D=3D 0 || c->x86 =3D=3D 15) && c->cpuid_level > 1= && - c->x86_vendor !=3D X86_VENDOR_SHANGHAI) - { + if (((num_cache_leaves =3D=3D 0 || c->x86 =3D=3D 15) && c->cpuid_level > = 1) && + (!(cpu_vendor() & X86_VENDOR_SHANGHAI))) { /* supports eax=3D2 call */ unsigned int i, j, n, regs[4]; unsigned char *dp =3D (unsigned char *)regs; diff --git a/xen/arch/x86/cpu/microcode/amd.c b/xen/arch/x86/cpu/microcode/= amd.c index 90f10ac8be..b4c8264e27 100644 --- a/xen/arch/x86/cpu/microcode/amd.c +++ b/xen/arch/x86/cpu/microcode/amd.c @@ -616,7 +616,7 @@ void __init amd_check_entrysign(void) uint8_t fixed_rev; =20 if ( !IS_ENABLED(CONFIG_MICROCODE_LOADING) || - boot_cpu_data.vendor !=3D X86_VENDOR_AMD || + !(cpu_vendor() & X86_VENDOR_AMD) || boot_cpu_data.family < 0x17 || boot_cpu_data.family > 0x1a ) return; diff --git a/xen/arch/x86/cpu/microcode/core.c b/xen/arch/x86/cpu/microcode= /core.c index ea0b35c499..ebe4d21026 100644 --- a/xen/arch/x86/cpu/microcode/core.c +++ b/xen/arch/x86/cpu/microcode/core.c @@ -216,7 +216,7 @@ static struct patch_with_flags nmi_patch =3D /* Returns true if ucode should be loaded on a given cpu */ static bool is_cpu_primary(unsigned int cpu) { - if ( boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) /* Load ucode on every logical thread/core */ return true; =20 diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch/x86/cpu/mtrr/generi= c.c index c587e9140e..eab72dc103 100644 --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -218,9 +218,8 @@ static void __init print_mtrr_state(const char *level) printk("%s %u disabled\n", level, i); } =20 - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD && - boot_cpu_data.x86 >=3D 0xf) || - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_HYGON) { + if (((cpu_vendor() & X86_VENDOR_AMD) && boot_cpu_data.x86 >=3D 0xf) || + (cpu_vendor() & X86_VENDOR_HYGON)) { uint64_t syscfg, tom2; =20 rdmsrl(MSR_K8_SYSCFG, syscfg); diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index 5962ec1db9..8536bc97f6 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -1598,7 +1598,7 @@ static int __init mwait_idle_probe(void) const struct x86_cpu_id *id; const char *str; =20 - if (boot_cpu_data.vendor !=3D X86_VENDOR_INTEL) + if (!(cpu_vendor() & X86_VENDOR_INTEL)) return -ENODEV; =20 id =3D x86_match_cpu(intel_idle_ids); @@ -1816,8 +1816,7 @@ bool __init mwait_pc10_supported(void) { unsigned int ecx, edx, dummy; =20 - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - !cpu_has_monitor || + if (!(cpu_vendor() & X86_VENDOR_INTEL) || !cpu_has_monitor || boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) return false; =20 diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c index b1ad4ebcf6..b79d57d0ec 100644 --- a/xen/arch/x86/cpu/vpmu.c +++ b/xen/arch/x86/cpu/vpmu.c @@ -398,7 +398,6 @@ int vpmu_load(struct vcpu *v, bool from_guest) static int vpmu_arch_initialise(struct vcpu *v) { struct vpmu_struct *vpmu =3D vcpu_vpmu(v); - uint8_t vendor =3D current_cpu_data.x86_vendor; int ret; =20 BUILD_BUG_ON(sizeof(struct xen_pmu_intel_ctxt) > XENPMU_CTXT_PAD_SZ); @@ -418,7 +417,7 @@ static int vpmu_arch_initialise(struct vcpu *v) if ( vpmu_mode !=3D XENPMU_MODE_OFF ) { printk(XENLOG_G_WARNING "VPMU: Unknown CPU vendor %d. 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charset="utf-8" Not a functional change. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/apic.c | 2 +- xen/arch/x86/cpu-policy.c | 8 ++++---- xen/arch/x86/cpuid.c | 5 ++--- xen/arch/x86/dom0_build.c | 2 +- xen/arch/x86/domain.c | 12 +++++------- xen/arch/x86/e820.c | 2 +- xen/arch/x86/hvm/hvm.c | 3 +-- xen/arch/x86/hvm/ioreq.c | 3 +-- xen/arch/x86/hvm/vmx/vmx.c | 8 +++----- xen/arch/x86/i8259.c | 5 ++--- xen/arch/x86/include/asm/guest_pt.h | 3 +-- xen/arch/x86/irq.c | 3 +-- xen/arch/x86/setup.c | 7 +++---- 13 files changed, 26 insertions(+), 37 deletions(-) diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c index fb38be7ec3..fd3ac07aeb 100644 --- a/xen/arch/x86/apic.c +++ b/xen/arch/x86/apic.c @@ -406,7 +406,7 @@ void __init init_bsp_APIC(void) value |=3D APIC_SPIV_APIC_ENABLED; =20 /* This bit is reserved on P4/Xeon and should be cleared */ - if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL) && (boot_cpu_da= ta.x86 =3D=3D 15)) + if ((cpu_vendor() & X86_VENDOR_INTEL) && (boot_cpu_data.x86 =3D=3D 15)) value &=3D ~APIC_SPIV_FOCUS_DISABLED; else value |=3D APIC_SPIV_FOCUS_DISABLED; diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c index 62aff61d8c..055862b0b2 100644 --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -770,7 +770,7 @@ static void __init calculate_hvm_max_policy(void) * long mode (and init_amd() has cleared it out of host capabilities),= but * HVM guests are able if running in protected mode. */ - if ( (boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && + if ( (cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && raw_cpu_policy.basic.sep ) __set_bit(X86_FEATURE_SEP, fs); =20 @@ -963,8 +963,8 @@ void recalculate_cpuid_policy(struct domain *d) p->basic.max_leaf =3D min(p->basic.max_leaf, max->basic.max_leaf); p->feat.max_subleaf =3D min(p->feat.max_subleaf, max->feat.max_subleaf= ); p->extd.max_leaf =3D 0x80000000U | min(p->extd.max_leaf & 0xffff, - ((p->x86_vendor & (X86_VENDOR_= AMD | - X86_VENDOR_= HYGON)) + ((cpu_vendor() & (X86_VENDOR_A= MD | + X86_VENDOR_H= YGON)) ? CPUID_GUEST_NR_EXTD_AMD : CPUID_GUEST_NR_EXTD_INTEL) = - 1); =20 @@ -998,7 +998,7 @@ void recalculate_cpuid_policy(struct domain *d) if ( is_pv_32bit_domain(d) ) { __clear_bit(X86_FEATURE_LM, max_fs); - if ( !(boot_cpu_data.vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))= ) + if ( !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) __clear_bit(X86_FEATURE_SYSCALL, max_fs); } =20 diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 5decfad8cd..d64030bc09 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -437,8 +437,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, =20 case 0xa: /* TODO: Rework vPMU control in terms of toolstack choices. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - !vpmu_available(v) ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || !vpmu_available(v) ) *res =3D EMPTY_LEAF; else { @@ -483,7 +482,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf, =20 case 0x80000001U: /* SYSCALL is hidden outside of long mode on Intel. */ - if ( p->x86_vendor =3D=3D X86_VENDOR_INTEL && + if ( (cpu_vendor() & X86_VENDOR_INTEL) && is_hvm_domain(d) && !hvm_long_mode_active(v) ) res->d &=3D ~cpufeat_mask(X86_FEATURE_SYSCALL); =20 diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c index 0b467fd4a4..4b7f1bf034 100644 --- a/xen/arch/x86/dom0_build.c +++ b/xen/arch/x86/dom0_build.c @@ -572,7 +572,7 @@ int __init dom0_setup_permissions(struct domain *d) rc |=3D iomem_deny_access(d, mfn, mfn); } /* HyperTransport range. */ - if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) { mfn =3D paddr_to_pfn(1UL << (boot_cpu_data.x86 < 0x17 ? 40 : paddr_bits)); diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 10a558e515..fd9c7f0be5 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -372,7 +372,7 @@ void domain_cpu_policy_changed(struct domain *d) { uint64_t mask =3D cpuidmask_defaults._6c; =20 - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD ) + if ( cpu_vendor() & X86_VENDOR_AMD ) mask &=3D (~0ULL << 32) | p->basic.raw[6].c; =20 d->arch.pv.cpuidmasks->_6c =3D mask; @@ -387,8 +387,7 @@ void domain_cpu_policy_changed(struct domain *d) * wholesale from the policy, but clamp the features in 7[0].e= bx * per usual. */ - if ( boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) + if ( cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON) ) mask =3D (((uint64_t)p->feat.max_subleaf << 32) | ((uint32_t)mask & p->feat._7b0)); =20 @@ -400,7 +399,7 @@ void domain_cpu_policy_changed(struct domain *d) uint64_t mask =3D cpuidmask_defaults.Da1; uint32_t eax =3D p->xstate.Da1; =20 - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL ) + if ( cpu_vendor() & X86_VENDOR_INTEL ) mask &=3D (~0ULL << 32) | eax; =20 d->arch.pv.cpuidmasks->Da1 =3D mask; @@ -424,7 +423,7 @@ void domain_cpu_policy_changed(struct domain *d) * If not emulating AMD or Hygon, clear the duplicated features * in e1d. */ - if ( !(p->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) ) + if ( cpu_vendor() & ~(X86_VENDOR_AMD | X86_VENDOR_HYGON) ) edx &=3D ~CPUID_COMMON_1D_FEATURES; =20 switch( cpu_vendor() ) @@ -457,8 +456,7 @@ void domain_cpu_policy_changed(struct domain *d) cpu_policy_updated(v); =20 /* If PMU version is zero then the guest doesn't have VPMU */ - if ( boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && - p->basic.pmu_version =3D=3D 0 ) + if ( (cpu_vendor() & X86_VENDOR_INTEL) && p->basic.pmu_version =3D= =3D 0 ) vpmu_destroy(v); } } diff --git a/xen/arch/x86/e820.c b/xen/arch/x86/e820.c index ca577c0bde..0bf90f2283 100644 --- a/xen/arch/x86/e820.c +++ b/xen/arch/x86/e820.c @@ -426,7 +426,7 @@ static uint64_t __init mtrr_top_of_ram(void) =20 /* By default we check only Intel systems. */ if ( e820_mtrr_clip =3D=3D -1 ) - e820_mtrr_clip =3D boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTE= L; + e820_mtrr_clip =3D cpu_vendor() =3D=3D X86_VENDOR_INTEL; =20 if ( !e820_mtrr_clip ) return 0; diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4d37a93c57..52a6cc69e5 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -2681,8 +2681,7 @@ bool hvm_vcpu_virtual_to_linear( } else if ( last_byte > reg->limit ) goto out; /* last byte is beyond limit */ - else if ( last_byte < offset && - v->domain->arch.cpuid->x86_vendor =3D=3D X86_VENDOR_AMD ) + else if ( (cpu_vendor() & X86_VENDOR_AMD) && last_byte < offset ) goto out; /* access wraps */ } =20 diff --git a/xen/arch/x86/hvm/ioreq.c b/xen/arch/x86/hvm/ioreq.c index a5fa97e149..7a55b14f55 100644 --- a/xen/arch/x86/hvm/ioreq.c +++ b/xen/arch/x86/hvm/ioreq.c @@ -285,8 +285,7 @@ bool arch_ioreq_server_get_type_addr(const struct domai= n *d, *type =3D XEN_DMOP_IO_RANGE_PCI; *addr =3D ((uint64_t)sbdf.sbdf << 32) | reg; /* AMD extended configuration space access? */ - if ( CF8_ADDR_HI(cf8) && - d->arch.cpuid->x86_vendor =3D=3D X86_VENDOR_AMD && + if ( CF8_ADDR_HI(cf8) && (cpu_vendor() & X86_VENDOR_AMD) && (x86_fam =3D get_cpu_family( d->arch.cpuid->basic.raw_fms, NULL, NULL)) >=3D 0x10 && x86_fam < 0x17 ) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 82c55f49ae..5637ee15e7 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -3073,8 +3073,7 @@ static bool __init has_if_pschange_mc(void) * IF_PSCHANGE_MC is only known to affect Intel Family 6 processors at * this time. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.x86 !=3D 6 ) return false; =20 switch ( boot_cpu_data.x86_model ) @@ -3431,7 +3430,7 @@ static void __init lbr_tsx_fixup_check(void) * fixed up as well. */ if ( cpu_has_hle || cpu_has_rtm || - boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || + !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.x86 !=3D 6 ) return; =20 @@ -3476,8 +3475,7 @@ static void __init ler_to_fixup_check(void) * that are not equal to bit[47]. Attempting to context switch this v= alue * may cause a #GP. Software should sign extend the MSR. */ - if ( boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || - boot_cpu_data.x86 !=3D 6 ) + if ( !(cpu_vendor() & X86_VENDOR_INTEL) || boot_cpu_data.x86 !=3D 6 ) return; =20 switch ( boot_cpu_data.x86_model ) diff --git a/xen/arch/x86/i8259.c b/xen/arch/x86/i8259.c index 5c7e21a751..c19d2fe7b4 100644 --- a/xen/arch/x86/i8259.c +++ b/xen/arch/x86/i8259.c @@ -419,9 +419,8 @@ void __init init_IRQ(void) * the interrupt. */ cpumask_copy(desc->arch.cpu_mask, - (boot_cpu_data.x86_vendor & - (X86_VENDOR_AMD | X86_VENDOR_HYGON) ? &cpumask_all - : cpumask_of(cpu= ))); + ((cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) + ? &cpumask_all : cpumask_of(cpu))); desc->arch.vector =3D LEGACY_VECTOR(irq); } =20 diff --git a/xen/arch/x86/include/asm/guest_pt.h b/xen/arch/x86/include/asm= /guest_pt.h index 21473f9bbc..cc3e9b504c 100644 --- a/xen/arch/x86/include/asm/guest_pt.h +++ b/xen/arch/x86/include/asm/guest_pt.h @@ -314,8 +314,7 @@ static always_inline bool guest_l4e_rsvd_bits(const str= uct vcpu *v, guest_l4e_t l4e) { return l4e.l4 & (guest_rsvd_bits(v) | GUEST_L4_PAGETABLE_RSVD | - ((v->domain->arch.cpuid->x86_vendor =3D=3D X86_VENDOR= _AMD) - ? _PAGE_GLOBAL : 0)); + ((cpu_vendor() & X86_VENDOR_AMD) ? _PAGE_GLOBAL : 0)); } #endif /* GUEST_PAGING_LEVELS >=3D 4 */ #endif /* GUEST_PAGING_LEVELS >=3D 3 */ diff --git a/xen/arch/x86/irq.c b/xen/arch/x86/irq.c index cc2934bfca..8e3706fb98 100644 --- a/xen/arch/x86/irq.c +++ b/xen/arch/x86/irq.c @@ -2011,8 +2011,7 @@ void do_IRQ(struct cpu_user_regs *regs) * interrupts have been delivered to CPUs * different than the BSP. */ - (boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | - X86_VENDOR_HYGON))) && + cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) && bogus_8259A_irq(vector - FIRST_LEGACY_VECTOR)) ) { printk("CPU%u: No irq handler for vector %02x (IRQ %d%s)\n= ", diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 27c63d1d97..26b17aab8f 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1406,8 +1406,7 @@ void asmlinkage __init noreturn __start_xen(void) * CPUs with this addressed enumerate CET-SSS to indicate that * supervisor shadow stacks are now safe to use. */ - bool cpu_has_bug_shstk_fracture =3D - boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && + bool cpu_has_bug_shstk_fracture =3D (cpu_vendor() & X86_VENDOR_INT= EL) && !boot_cpu_has(X86_FEATURE_CET_SSS); =20 /* @@ -2038,10 +2037,10 @@ void asmlinkage __init noreturn __start_xen(void) =20 /* Do not enable SMEP/SMAP in PV shim on AMD and Hygon by default */ if ( opt_smep =3D=3D -1 ) - opt_smep =3D !pv_shim || !(boot_cpu_data.x86_vendor & + opt_smep =3D !pv_shim || !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)); if ( opt_smap =3D=3D -1 ) - opt_smap =3D !pv_shim || !(boot_cpu_data.x86_vendor & + opt_smap =3D !pv_shim || !(cpu_vendor() & (X86_VENDOR_AMD | X86_VENDOR_HYGON)); =20 if ( !opt_smep ) --=20 2.43.0