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charset="utf-8" While in principle it's possible to have a vendor virtualising another, this is fairly tricky in practice and comes with the world's supply of security issues. Reject any CPU policy with vendors not matching the host's. Signed-off-by: Alejandro Vallejo --- v2: * Reversed polarity of leaf0 check in policy compatibility helper. * Reworded changelog entry in terms of LM + save/restore. --- CHANGELOG.md | 5 +++++ xen/lib/x86/policy.c | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 18f3d10f20..426c0bce67 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -22,6 +22,11 @@ The format is based on [Keep a Changelog](https://keepac= hangelog.com/en/1.0.0/) - Xenoprofile support. Oprofile themselves removed support for Xen in = 2014 prior to the version 1.0 release, and there has been no development s= ince before then in Xen. + - Domains can no longer run on a CPU vendor if they were initially laun= ched + on a different CPU vendor. This affects live migrations and save/rest= ore + workflows accross mixed-vendor hosts. Cross-vendor emulation has alwa= ys + been unreliable, but since 2017 with the advent of speculation securi= ty it + became unsustainably so. =20 - Removed xenpm tool on non-x86 platforms as it doesn't actually provide anything useful outside of x86. diff --git a/xen/lib/x86/policy.c b/xen/lib/x86/policy.c index f033d22785..079c42a29b 100644 --- a/xen/lib/x86/policy.c +++ b/xen/lib/x86/policy.c @@ -15,7 +15,8 @@ int x86_cpu_policies_are_compatible(const struct cpu_poli= cy *host, #define FAIL_MSR(m) \ do { e.msr =3D (m); goto out; } while ( 0 ) =20 - if ( guest->basic.max_leaf > host->basic.max_leaf ) + if ( (guest->x86_vendor !=3D host->x86_vendor) || + (guest->basic.max_leaf > host->basic.max_leaf) ) FAIL_CPUID(0, NA); =20 if ( guest->feat.max_subleaf > host->feat.max_subleaf ) --=20 2.43.0 From nobody Sat Feb 7 06:54:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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charset="utf-8" Remove cross-vendor support now that VMs can no longer have a different vendor than the host. While at it, refactor the function to exit early and skip initialising the emulation context when FEP is not enabled. No functional change intended. Signed-off-by: Alejandro Vallejo --- The diff is annoying, but keeping prior logic is silly when it can be simplified and the emulation context initialisation removed on the overwhelming majority of cases. v2: * Fix bug introduced in v1: Don't emulate instructions when they shouldn't be emulated. * Refactor the function so it's simpler. --- xen/arch/x86/hvm/hvm.c | 77 +++++++++++++++----------------------- xen/arch/x86/hvm/svm/svm.c | 3 +- xen/arch/x86/hvm/vmx/vmx.c | 3 +- 3 files changed, 32 insertions(+), 51 deletions(-) diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 4d37a93c57..8708af9425 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3832,69 +3832,47 @@ int hvm_descriptor_access_intercept(uint64_t exit_i= nfo, return X86EMUL_OKAY; } =20 -static bool cf_check is_cross_vendor( - const struct x86_emulate_state *state, const struct x86_emulate_ctxt *= ctxt) -{ - switch ( ctxt->opcode ) - { - case X86EMUL_OPC(0x0f, 0x05): /* syscall */ - case X86EMUL_OPC(0x0f, 0x34): /* sysenter */ - case X86EMUL_OPC(0x0f, 0x35): /* sysexit */ - return true; - } - - return false; -} - void hvm_ud_intercept(struct cpu_user_regs *regs) { struct vcpu *cur =3D current; - bool should_emulate =3D - cur->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.x86_vendor; struct hvm_emulate_ctxt ctxt; + const struct segment_register *cs =3D &ctxt.seg_reg[x86_seg_cs]; + uint32_t walk =3D PFEC_insn_fetch; + unsigned long addr; + char sig[5]; /* ud2; .ascii "xen" */ =20 - hvm_emulate_init_once(&ctxt, opt_hvm_fep ? NULL : is_cross_vendor, reg= s); + if ( !opt_hvm_fep ) + goto reinject; =20 - if ( opt_hvm_fep ) - { - const struct segment_register *cs =3D &ctxt.seg_reg[x86_seg_cs]; - uint32_t walk =3D ((ctxt.seg_reg[x86_seg_ss].dpl =3D=3D 3) - ? PFEC_user_mode : 0) | PFEC_insn_fetch; - unsigned long addr; - char sig[5]; /* ud2; .ascii "xen" */ - - if ( hvm_virtual_to_linear_addr(x86_seg_cs, cs, regs->rip, - sizeof(sig), hvm_access_insn_fetch, - cs, &addr) && - (hvm_copy_from_guest_linear(sig, addr, sizeof(sig), - walk, NULL) =3D=3D HVMTRANS_okay)= && - (memcmp(sig, "\xf\xb" "xen", sizeof(sig)) =3D=3D 0) ) - { - regs->rip +=3D sizeof(sig); - regs->eflags &=3D ~X86_EFLAGS_RF; + hvm_emulate_init_once(&ctxt, NULL, regs); =20 - /* Zero the upper 32 bits of %rip if not in 64bit mode. */ - if ( !(hvm_long_mode_active(cur) && cs->l) ) - regs->rip =3D (uint32_t)regs->rip; + if ( ctxt.seg_reg[x86_seg_ss].dpl =3D=3D 3 ) + walk |=3D PFEC_user_mode; =20 - add_taint(TAINT_HVM_FEP); + if ( hvm_virtual_to_linear_addr(x86_seg_cs, cs, regs->rip, + sizeof(sig), hvm_access_insn_fetch, + cs, &addr) && + (hvm_copy_from_guest_linear(sig, addr, sizeof(sig), + walk, NULL) =3D=3D HVMTRANS_okay) && + (memcmp(sig, "\xf\xb" "xen", sizeof(sig)) =3D=3D 0) ) + { + regs->rip +=3D sizeof(sig); + regs->eflags &=3D ~X86_EFLAGS_RF; =20 - should_emulate =3D true; - } - } + /* Zero the upper 32 bits of %rip if not in 64bit mode. */ + if ( !(hvm_long_mode_active(cur) && cs->l) ) + regs->rip =3D (uint32_t)regs->rip; =20 - if ( !should_emulate ) - { - hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); - return; + add_taint(TAINT_HVM_FEP); } + else + goto reinject; =20 switch ( hvm_emulate_one(&ctxt, VIO_no_completion) ) { case X86EMUL_UNHANDLEABLE: case X86EMUL_UNIMPLEMENTED: - hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); - break; + goto reinject; case X86EMUL_EXCEPTION: hvm_inject_event(&ctxt.ctxt.event); /* fall through */ @@ -3902,6 +3880,11 @@ void hvm_ud_intercept(struct cpu_user_regs *regs) hvm_emulate_writeback(&ctxt); break; } + + return; + + reinject: + hvm_inject_hw_exception(X86_EXC_UD, X86_EVENT_NO_EC); } =20 enum hvm_intblk hvm_interrupt_blocked(struct vcpu *v, struct hvm_intack in= tack) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 18ba837738..10d1bf350c 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -589,8 +589,7 @@ static void cf_check svm_cpuid_policy_changed(struct vc= pu *v) const struct cpu_policy *cp =3D v->domain->arch.cpu_policy; u32 bitmap =3D vmcb_get_exception_intercepts(vmcb); =20 - if ( opt_hvm_fep || - (v->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.x86_vendor)= ) + if ( opt_hvm_fep ) bitmap |=3D (1U << X86_EXC_UD); else bitmap &=3D ~(1U << X86_EXC_UD); diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 82c55f49ae..eda99e268d 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -803,8 +803,7 @@ static void cf_check vmx_cpuid_policy_changed(struct vc= pu *v) const struct cpu_policy *cp =3D v->domain->arch.cpu_policy; int rc =3D 0; =20 - if ( opt_hvm_fep || - (v->domain->arch.cpuid->x86_vendor !=3D boot_cpu_data.x86_vendor)= ) + if ( opt_hvm_fep ) v->arch.hvm.vmx.exception_bitmap |=3D (1U << X86_EXC_UD); else v->arch.hvm.vmx.exception_bitmap &=3D ~(1U << X86_EXC_UD); --=20 2.43.0 From nobody Sat Feb 7 06:54:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; 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Signed-off-by: Alejandro Vallejo Reviewed-by: Teddy Astie --- v2: * Use boot_cpu_data rather than policy vendor. --- xen/arch/x86/msr.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index ad75a2e108..d10891dcfc 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -169,9 +169,9 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) break; =20 case MSR_IA32_PLATFORM_ID: - if ( !(cp->x86_vendor & X86_VENDOR_INTEL) || - !(boot_cpu_data.x86_vendor & X86_VENDOR_INTEL) ) + if ( boot_cpu_data.vendor !=3D X86_VENDOR_INTEL ) goto gp_fault; + rdmsrl(MSR_IA32_PLATFORM_ID, *val); break; =20 @@ -189,9 +189,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t = *val) * from Xen's last microcode load, which can be forwarded straight= to * the guest. */ - if ( !(cp->x86_vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || - !(boot_cpu_data.x86_vendor & - (X86_VENDOR_INTEL | X86_VENDOR_AMD)) || + if ( !(boot_cpu_data.vendor & (X86_VENDOR_INTEL | X86_VENDOR_AMD))= || rdmsr_safe(MSR_AMD_PATCHLEVEL, val) ) goto gp_fault; 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charset="utf-8" With cross-vendor support gone, it's no longer needed. AMD CPUs ignore the top 32 bits of the SYSENTER/SYSEXIT MSRs, which is not how this emulation worked due to the need for cross-vendor support. Any AMD VMs storing state in the top 32bits of the SEP MSRs will lose it. It's very unlikely to affect any production VM because having 64bit width just isn't how real AMD CPUs behave. Signed-off-by: Alejandro Vallejo Reviewed-by: Teddy Astie --- v2: * Reworded commit message to mention the loss of the top dword for any VM stupid enough to use it. --- xen/arch/x86/hvm/svm/svm.c | 42 +++++++++++------------- xen/arch/x86/hvm/svm/vmcb.c | 3 ++ xen/arch/x86/include/asm/hvm/svm-types.h | 10 ------ 3 files changed, 22 insertions(+), 33 deletions(-) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 10d1bf350c..329c4446e9 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -401,10 +401,6 @@ static int svm_vmcb_save(struct vcpu *v, struct hvm_hw= _cpu *c) { struct vmcb_struct *vmcb =3D v->arch.hvm.svm.vmcb; =20 - c->sysenter_cs =3D v->arch.hvm.svm.guest_sysenter_cs; - c->sysenter_esp =3D v->arch.hvm.svm.guest_sysenter_esp; - c->sysenter_eip =3D v->arch.hvm.svm.guest_sysenter_eip; - if ( vmcb->event_inj.v && hvm_event_needs_reinjection(vmcb->event_inj.type, vmcb->event_inj.vector) ) @@ -468,11 +464,6 @@ static int svm_vmcb_restore(struct vcpu *v, struct hvm= _hw_cpu *c) svm_update_guest_cr(v, 0, 0); svm_update_guest_cr(v, 4, 0); =20 - /* Load sysenter MSRs into both VMCB save area and VCPU fields. */ - vmcb->sysenter_cs =3D v->arch.hvm.svm.guest_sysenter_cs =3D c->sysente= r_cs; - vmcb->sysenter_esp =3D v->arch.hvm.svm.guest_sysenter_esp =3D c->sysen= ter_esp; - vmcb->sysenter_eip =3D v->arch.hvm.svm.guest_sysenter_eip =3D c->sysen= ter_eip; - if ( paging_mode_hap(v->domain) ) { vmcb_set_np(vmcb, true); @@ -501,6 +492,9 @@ static void svm_save_cpu_state(struct vcpu *v, struct h= vm_hw_cpu *data) { struct vmcb_struct *vmcb =3D v->arch.hvm.svm.vmcb; =20 + data->sysenter_cs =3D vmcb->sysenter_cs; + data->sysenter_esp =3D vmcb->sysenter_esp; + data->sysenter_eip =3D vmcb->sysenter_eip; data->shadow_gs =3D vmcb->kerngsbase; data->msr_lstar =3D vmcb->lstar; data->msr_star =3D vmcb->star; @@ -512,11 +506,14 @@ static void svm_load_cpu_state(struct vcpu *v, struct= hvm_hw_cpu *data) { struct vmcb_struct *vmcb =3D v->arch.hvm.svm.vmcb; =20 - vmcb->kerngsbase =3D data->shadow_gs; - vmcb->lstar =3D data->msr_lstar; - vmcb->star =3D data->msr_star; - vmcb->cstar =3D data->msr_cstar; - vmcb->sfmask =3D data->msr_syscall_mask; + vmcb->sysenter_cs =3D data->sysenter_cs; + vmcb->sysenter_esp =3D data->sysenter_esp; + vmcb->sysenter_eip =3D data->sysenter_eip; + vmcb->kerngsbase =3D data->shadow_gs; + vmcb->lstar =3D data->msr_lstar; + vmcb->star =3D data->msr_star; + vmcb->cstar =3D data->msr_cstar; + vmcb->sfmask =3D data->msr_syscall_mask; v->arch.hvm.guest_efer =3D data->msr_efer; svm_update_guest_efer(v); } @@ -1720,12 +1717,9 @@ static int cf_check svm_msr_read_intercept( =20 switch ( msr ) { - /* - * Sync not needed while the cross-vendor logic is in unilateral e= ffect. case MSR_IA32_SYSENTER_CS: case MSR_IA32_SYSENTER_ESP: case MSR_IA32_SYSENTER_EIP: - */ case MSR_STAR: case MSR_LSTAR: case MSR_CSTAR: @@ -1740,13 +1734,15 @@ static int cf_check svm_msr_read_intercept( switch ( msr ) { case MSR_IA32_SYSENTER_CS: - *msr_content =3D v->arch.hvm.svm.guest_sysenter_cs; + *msr_content =3D vmcb->sysenter_cs; break; + case MSR_IA32_SYSENTER_ESP: - *msr_content =3D v->arch.hvm.svm.guest_sysenter_esp; + *msr_content =3D vmcb->sysenter_esp; break; + case MSR_IA32_SYSENTER_EIP: - *msr_content =3D v->arch.hvm.svm.guest_sysenter_eip; + *msr_content =3D vmcb->sysenter_eip; break; =20 case MSR_STAR: @@ -1940,11 +1936,11 @@ static int cf_check svm_msr_write_intercept( switch ( msr ) { case MSR_IA32_SYSENTER_ESP: - vmcb->sysenter_esp =3D v->arch.hvm.svm.guest_sysenter_esp =3D = msr_content; + vmcb->sysenter_esp =3D msr_content; break; =20 case MSR_IA32_SYSENTER_EIP: - vmcb->sysenter_eip =3D v->arch.hvm.svm.guest_sysenter_eip =3D = msr_content; + vmcb->sysenter_eip =3D msr_content; break; =20 case MSR_LSTAR: @@ -1970,7 +1966,7 @@ static int cf_check svm_msr_write_intercept( break; =20 case MSR_IA32_SYSENTER_CS: - vmcb->sysenter_cs =3D v->arch.hvm.svm.guest_sysenter_cs =3D msr_co= ntent; + vmcb->sysenter_cs =3D msr_content; break; =20 case MSR_STAR: diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index e583ef8548..76fcaf15c2 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -97,6 +97,9 @@ static int construct_vmcb(struct vcpu *v) svm_disable_intercept_for_msr(v, MSR_LSTAR); svm_disable_intercept_for_msr(v, MSR_STAR); svm_disable_intercept_for_msr(v, MSR_SYSCALL_MASK); + svm_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_CS); + svm_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_EIP); + svm_disable_intercept_for_msr(v, MSR_IA32_SYSENTER_ESP); =20 vmcb->_msrpm_base_pa =3D virt_to_maddr(svm->msrpm); vmcb->_iopm_base_pa =3D __pa(v->domain->arch.hvm.io_bitmap); diff --git a/xen/arch/x86/include/asm/hvm/svm-types.h b/xen/arch/x86/includ= e/asm/hvm/svm-types.h index 051b235d8f..aaee91b4b6 100644 --- a/xen/arch/x86/include/asm/hvm/svm-types.h +++ b/xen/arch/x86/include/asm/hvm/svm-types.h @@ -27,16 +27,6 @@ struct svm_vcpu { =20 /* VMCB has a cached instruction from #PF/#NPF Decode Assist? */ uint8_t cached_insn_len; /* Zero if no cached instruction. */ - - /* - * Upper four bytes are undefined in the VMCB, therefore we can't use = the - * fields in the VMCB. Write a 64bit value and then read a 64bit value= is - * fine unless there's a VMRUN/VMEXIT in between which clears the upper - * four bytes. - */ - uint64_t guest_sysenter_cs; - uint64_t guest_sysenter_esp; - uint64_t guest_sysenter_eip; }; =20 struct nestedsvm { --=20 2.43.0