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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:50 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f9452f2f-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450031; x=1770054831; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zyRXQCzMht59KNrjuruuDRnKF4fVxlGPuMfpmypUDsw=; b=P0MOH0fmzKdVPVOgODqc0ejXooP6WD/ethCQC5LKp6eElyFAZQ0UI/EKzSsDW/2+6z eX8f8+q+o2bE1yuUPPwJkM3sZaLHTMEnAq6YHHo/0vtwGbmEGgkDOXUVx3HXIHvLOoUX FthmN8rXvAoCUC2yFAlTG0ZYLNJihJIDfHJiw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450031; x=1770054831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=zyRXQCzMht59KNrjuruuDRnKF4fVxlGPuMfpmypUDsw=; b=aapvZCnwpqhsrkEz8YU7ZSX7HHehnD6B6owZ+QANk9MAgUZ9FXgfxuIujdSBB9ysHY xyiSVH91bF6E6sY1RXd/SeKONsZgrnfFdyrwz+pyqOwyLvOySx9sPWzj278lqfplStJ9 y4V5rwDz69ECh1u3nIt0Rr8feQ7JnS/MnDUsWaqj6CDtfyL5L+W1SXtKHRPa1ASGHgKx aLIQo53c47N8iQzrTA/uXYGqYI48h7GtdNnirJZfqKkClXCgwKz17mWliw7PcNe2+ePp xNkZ7ZUnNyT1WaMI/gEJTrkppRfLEH16JKI/L7pxqRCLBgs0LLc3CnCqTBNyC2fUqx+y bZBA== X-Gm-Message-State: AOJu0YxYVhYi6WAAY8Rbo1X1xVDMpZP+hFrgYtJusYf8ulpoQH22fbgU dW8uQq6gOfzEeEkUgaiBBpCmOlIOSv5GnLFMsGuaZjRQGCR5W+s9/NjVire6AkyscUr8gEhc0/s Ww18+ X-Gm-Gg: AZuq6aKnv7W1HkceKpc6d547aoEy/qjLwlPrhVuxfSU2mUbT9Hze1XZW1mgcofTOsYQ DTkyr0zcqqpyL7n6838JbfmBJTq6be5TX/P4w8Z/7VxwIeDl9TYNrBF8vZmCX0DgbL5rr/S5t+n XZPbhP87cs2J3t435g2TX4BsUGhAYDIVuFTmcX7LtIw0xDuoft/YAYdrMeFHJE6j441IFRusj6D J3pm3AFCVHvP4CrRlaFvpEMupyt8kvaI4+j+uggyJ36oIPvH4kuZ0hV1lslpWwKe/TjOCyFpEN8 OUpzEl7pnig79VhVGMpDapm7ZgxAuntyyLCHJet3e6W6v7xM7QoDCtK2H2lKsa7AgcAyJi1YC2h 8jqoGvCklMETZr8bmuLFNoWxa7ysPF+yI1PFWjgIy6QTR8WIU0RxRgfcYhxrA32c9DJpG48TudU GCJziuGsKJhw+efB4EGnCRZyTG0I/hXLE4rbfhftio7nBOP7PGB+DKKf7W5bZ4RmaAAzWxjWqr X-Received: by 2002:a05:600c:1e2a:b0:471:14b1:da13 with SMTP id 5b1f17b1804b1-4805ce4dec1mr81666095e9.14.1769450030839; Mon, 26 Jan 2026 09:53:50 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie , Kevin Lampis Subject: [PATCH 03/16] x86/intel: Drop the paddr_bits workaround for P4 Nocona/Prescott CPUs Date: Mon, 26 Jan 2026 17:53:32 +0000 Message-Id: <20260126175345.2078371-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450072038154100 These are 32bit CPUs only. 64bit support started with model 4 (Prescott-25= 6). Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie CC: Kevin Lampis This ideally wants backporting to 4.20 along with the rest of the VFM clean= up in order to support DMR/NVL, which ends with removing the x86_ prefixed nam= es. --- xen/arch/x86/cpu/intel.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index d585161dd32f..eec6ee763040 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -335,11 +335,6 @@ static void cf_check early_init_intel(struct cpuinfo_x= 86 *c) bootsym(trampoline_misc_enable_off) & MSR_IA32_MISC_ENABLE_XD_DISABLE) printk(KERN_INFO "re-enabled NX (Execute Disable) protection\n"); =20 - /* CPUID workaround for Intel 0F33/0F34 CPU */ - if (boot_cpu_data.x86 =3D=3D 0xF && boot_cpu_data.x86_model =3D=3D 3 && - (boot_cpu_data.x86_mask =3D=3D 3 || boot_cpu_data.x86_mask =3D=3D 4)) - paddr_bits =3D 36; - if (c =3D=3D &boot_cpu_data) { uint64_t misc_enable; =20 --=20 2.39.5