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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:49 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f91711f2-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450030; x=1770054830; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0xq1gxDlmDZY+78ggsqSHcLd3bC7dQoTKGaHnAMx1Ws=; b=PfisyyokdKc3ZaO2tC/0omKdYFa2G0kjAUIgx1c76VumZt1OxLX/OlOJiqmIS+QFbb 6GuJvf3NSkaLz8kJXkY1JJOq7+qGing23xT4/8X8dKeBopp1LkqSwS/XJwctE0QcjXDj gKa4I4Rge1582jpjC6VEywT6bqgxnW6zYjS2Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450030; x=1770054830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0xq1gxDlmDZY+78ggsqSHcLd3bC7dQoTKGaHnAMx1Ws=; b=CDe30j+cAJ5ZhM9h/AwnmafSbCHPKDuyhW7LkF8+qSk25LMlGxwSdqxWpEK83TdNDu scpC5YMXYOmLIzns550sE0VRiiqqPeq9QQuZusxqZ0ciH5kxtWDznHjAB+VTUoNYxep3 KCPbEaA5QJ7UaQLdT+m/l1hZkAs91MehcGE1duUjwFijknjlYGgZCqkKWHFxTitw0Fdn kedq3itj7adE3NaocxfwIfhlocnmTvN76aIpqzaPSS5HA/M7BhTg+Q0cm3QzONocL86s 6JhmMeUT89DLqr6R6MOzOtuliGxbmTMymRYSbjV7o0rFKwnpjJTFJL3n69YREbkUGmg9 DAAw== X-Gm-Message-State: AOJu0YwtwcGsQwBf2IQyAesMrFxcKt1g+OP+M1HTJq8o5nUNZxS6Sx/m My2VoFEFSGLXvkbSKr7gFbPcgBjImNL8+of170bdvKvJUXsloYWUhU2ukgsgMaaTMWtCY5vzE9o ccgCF X-Gm-Gg: AZuq6aJoEWn49qyku+sHuOOok/XvSp+XzSvIHYWZ58Z6aXLIwQnChlYnrc6pYs6kfDM 2Np6sy4WT+lHGYOGNYzjIlMgQA30FEzlSTNRDI1rADQ/By13KxiP7F5inihMeydnA8daf5YKSJz SB5bW+4BSr0FD7Ck448BeruZKHaUxDcvb0muL6AxQ93UOjqaRdX3oo9ztrf3HyG32pxikH2ACcf uLkWd/bsigpUxTOUktkHJhsRR8GWyT+IRST/Q28ROnKJ5j5120qkhpkz1/YelvAZytX0tw7b2eV EkolpHzPs9r0Y2XKjpbsWAfp1jNK6q8yGE9DxgshsZjDm5xRNU0h1wBVWUhIMmpZ0TbfG6UJCKo Y3/0r1hlqWQM3ji1QOwL0ktK2cHYA5XMPZpbGC9cwPIOCjC55zq8I8sSXn4cT4yUYGGj+ehq/Z8 kVkNIgwb35tTLSUzSdkaPbpo/DiW3WtJyC6j5o3afy+GgxXrQdimAeTsMDakmgjQ== X-Received: by 2002:a05:600c:1993:b0:47e:e076:c7a2 with SMTP id 5b1f17b1804b1-4805ce4dd37mr88984935e9.15.1769450029713; Mon, 26 Jan 2026 09:53:49 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 01/16] x86/cpu: Fix boot time cache flushing Date: Mon, 26 Jan 2026 17:53:30 +0000 Message-Id: <20260126175345.2078371-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450068541158500 All 64-bit CPUs have CLFLUSH. AMD introduced it in the K8, Intel in the P4 Willamette core prior to 64-bit support, and VIA/Centaur in the Isaiah. Furthermore, the reported cacheline size is 64 on all CPUs to date. Arguably changeset 19435c10abf7 ("x86: consolidate/enhance TLB flushing interface", 2007) should have initialised c->x86_clflush_size earlier, but even at the time of changeset 3330013e6739 ("VT-d / x86: re-arrange cache syncing", 2022), early_cpu_init() had CLFLUSH-parsing logic but simply fail= ed to record the size. By removing get_cache_line_size() and assuming 16 bytes, the practical consequence for early IOMMU initialisation of SandyBridge era systems is to flush every cacheline 4 times (a pipeline stall too, as those CPUs could on= ly have one flush in flight at a single time). Record c->x86_clflush_size in early_cpu_init(), and panic() if CLFLUSH isn't found. Drop the redundant initialisation of c->x86_cache_alignment. Remove the fallback to 16 bytes in cache_{flush,writeback}(), opting instead for an ASSERT() to confirm that the logic hasn't been re-arranged too early. Fixes: 3330013e6739 ("VT-d / x86: re-arrange cache syncing") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/common.c | 7 ++++--- xen/arch/x86/flushtlb.c | 19 +++++++------------ 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index ebe2baf8b98a..f8c80db6eb1d 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -319,8 +319,6 @@ void __init early_cpu_init(bool verbose) uint64_t val; u32 eax, ebx, ecx, edx; =20 - c->x86_cache_alignment =3D 32; - /* Get vendor name */ cpuid(0x00000000, &c->cpuid_level, &ebx, &ecx, &edx); *(u32 *)&c->x86_vendor_id[0] =3D ebx; @@ -352,6 +350,7 @@ void __init early_cpu_init(bool verbose) if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH)) { unsigned int size =3D ((ebx >> 8) & 0xff) * 8; =20 + c->x86_clflush_size =3D size; c->x86_cache_alignment =3D size; =20 /* @@ -380,7 +379,9 @@ void __init early_cpu_init(bool verbose) } else setup_clear_cpu_cap(X86_FEATURE_CLZERO); - } + } else + panic("CLFLUSH information not available\n"); + /* Leaf 0x1 capabilities filled in early for Xen. */ c->x86_capability[FEATURESET_1d] =3D edx; c->x86_capability[FEATURESET_1c] =3D ecx; diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index 23721bb52c90..1f8877dcab23 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -234,8 +234,7 @@ unsigned int flush_area_local(const void *va, unsigned = int flags) =20 if ( (!(flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL)) || (flags & FLUSH_VA_VALID)) && - c->x86_clflush_size && c->x86_cache_size && sz && - ((sz >> 10) < c->x86_cache_size) ) + c->x86_cache_size && sz && ((sz >> 10) < c->x86_cache_size) ) { if ( flags & FLUSH_CACHE_EVICT ) cache_flush(va, sz); @@ -264,13 +263,11 @@ unsigned int flush_area_local(const void *va, unsigne= d int flags) */ void cache_flush(const void *addr, unsigned int size) { - /* - * This function may be called before current_cpu_data is established. - * Hence a fallback is needed to prevent the loop below becoming infin= ite. - */ - unsigned int clflush_size =3D current_cpu_data.x86_clflush_size ?: 16; + unsigned int clflush_size =3D current_cpu_data.x86_clflush_size; const void *end =3D addr + size; =20 + ASSERT(clflush_size); + alternative("", "mfence", X86_BUG_CLFLUSH_MFENCE); =20 addr -=3D (unsigned long)addr & (clflush_size - 1); @@ -301,11 +298,9 @@ void cache_writeback(const void *addr, unsigned int si= ze) if ( !boot_cpu_has(X86_FEATURE_CLWB) ) return cache_flush(addr, size); =20 - /* - * This function may be called before current_cpu_data is established. - * Hence a fallback is needed to prevent the loop below becoming infin= ite. - */ - clflush_size =3D current_cpu_data.x86_clflush_size ?: 16; + clflush_size =3D current_cpu_data.x86_clflush_size; + ASSERT(clflush_size); + addr -=3D (unsigned long)addr & (clflush_size - 1); for ( ; addr < end; addr +=3D clflush_size ) clwb(addr); --=20 2.39.5