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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:56 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fd21385e-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450037; x=1770054837; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DXHoMP2m1S668fp9KXBejADon30ms3RX1/2RyOl2CwM=; b=WuQQ57ZEGI+gtoEiAaalhftBAy7Ivd9p3IShdzs65a0YwgV4vZwM939Fkw8IDDyDKx RZB6zbkUqc94dB1hcu77FZo0gwAvGLTB/i8QHCJzT/xtI4I4Ni6KgKY2YDHCGZgzwSC2 EkAjB8jFEu4dBHzgAzxYwmh0/n8jvbYr685o4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450037; x=1770054837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=DXHoMP2m1S668fp9KXBejADon30ms3RX1/2RyOl2CwM=; b=ZVekbiz02nGMJca2TRH2nUfX+YKVDe227yVCzdPORt4tCEgYJh/06LI9yO0HtWsGkr tgLqe7nWcDBWUxM+X1b6YCzI+8Qd4b7w1cGJ5j/bwYQNzMOgwcYQkZV6DHfqWYeV52ng 869jsfVaB5ekASlUxutib6Lo1hh+lywKFEYkzDRPpQqPmuc0cePsY3w/TOiXUmnT8twe dzwRUP9kTAZP9xdAVjaRcTSr/jwghZEAa7AUCdp1gl+NHr1pL64qRsmlhJSbl1KZcJC6 Om5VhtoRvbRzS4I4A/RMA/w5BcPZhs90IoAkhhZ5nQbv1TxXkKN8mCRRhabveUX8imTk UsFg== X-Gm-Message-State: AOJu0Yy0DuIZhwfurOMA1NDSzK5bpXwrOgJdBfUSgf1BO74M2YUugnwU cRyUyE9O7/8xuzUHEHAAXW+MC1DXnzWsN0xsoz2PnBdj4MD4hUk1MaO1F/gJdL7dBPr/6Z7aWjw GJ+xG X-Gm-Gg: AZuq6aLIvFLlUER7duZOKDm5woiEijXcWUEYCeYlftby026ryEg6W+jpMo9Ux2G90+k ZmT6lrRFVaXoe8rv3n6IRViq1N9NGu8QwUa1ir0z0B3KuDgMNfE5zwS2yc8WoCAfSi5k9fjK6IM GRm/Aory82vL1lIGR3Mt+2lkT2A6Z9x4xP+dlQnFvzK7JfhH/GI7f1rPn2KRje587+trjkIVHjh G0u0jlbkbH14jemr3z7vmjTpTzEs1bguXNnoUaMUBGajR3zUUVPo2n3YSYy5Mrh8U7FnHUghlfo anOUt8n07rgjpc45CY6QsL5ptKA5TPTX73MOXoOBXoJ8BxnzD5XV3bdMEO1cVtbGyfT4vFLuHxR 6Kw7nPQRAzV6fd9UiZhAWHYCv0Bt2rHAZuZ1C4hyt9tc+WjJF0skZ37IMLGWtsXzq8FZ85nrQkK 3rrEbb1QC0CflF/h/Pn+87hZQujZ6XQcYN5pGXizX822Tv8RT4TN2pHPuHtmDi7A== X-Received: by 2002:a05:600c:c4a5:b0:477:9cdb:e32e with SMTP id 5b1f17b1804b1-4805ce4e578mr91498405e9.9.1769450036624; Mon, 26 Jan 2026 09:53:56 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 10/16] x86/amd: Always probe and configure the masking MSRs Date: Mon, 26 Jan 2026 17:53:39 +0000 Message-Id: <20260126175345.2078371-11-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450068416158500 This allows the infrastructure to reused for system-wide quirk/errata adjustments. Replace the call to ctxt_switch_levelling() with amd_ctxt_switch_masking() instead. The CPUID Faulting aspect is not interesting at this point in boo= t, and we want to explicitly propagate the masking MSR defaults into APs. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/amd.c | 15 +++++++++++---- xen/arch/x86/cpu/cpu.h | 1 + xen/arch/x86/cpu/hygon.c | 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 36fea2e0a299..e8daf7415bb0 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -162,7 +162,7 @@ static void __init noinline probe_masking_msrs(void) * parameter of NULL is used to context switch to the default host state (= by * the cpu bringup-code, crash path, etc). */ -static void cf_check amd_ctxt_switch_masking(const struct vcpu *next) +void cf_check amd_ctxt_switch_masking(const struct vcpu *next) { struct cpuidmasks *these_masks =3D &this_cpu(cpuidmasks); const struct domain *nextd =3D next ? next->domain : NULL; @@ -242,9 +242,12 @@ static void __init amd_init_levelling(void) boot_cpu_has(X86_FEATURE_CPUID_USER_DIS)) { expected_levelling_cap |=3D LCAP_faulting; levelling_caps |=3D LCAP_faulting; - return; } =20 + /* + * Always probe for the MSRs too. We reuse the infrastruture for + * quirks/errata/etc during boot. + */ probe_masking_msrs(); =20 if ((levelling_caps & LCAP_1cd) =3D=3D LCAP_1cd) { @@ -299,7 +302,7 @@ static void __init amd_init_levelling(void) (uint32_t)cpuidmask_defaults._6c); } =20 - if (levelling_caps) + if (levelling_caps && !(levelling_caps & LCAP_faulting)) ctxt_switch_masking =3D amd_ctxt_switch_masking; } =20 @@ -1015,7 +1018,11 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) u32 l, h; uint64_t value; =20 - ctxt_switch_levelling(NULL); + /* + * Reuse amd_ctxt_switch_masking() explicitly. This propagates + * quirk/errata adjustments made duing early_init_amd() into the APs. + */ + amd_ctxt_switch_masking(NULL); =20 amd_init_de_cfg(c); =20 diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h index d2d37d1d5eec..cd93e51755af 100644 --- a/xen/arch/x86/cpu/cpu.h +++ b/xen/arch/x86/cpu/cpu.h @@ -20,6 +20,7 @@ extern void detect_ht(struct cpuinfo_x86 *c); extern bool detect_extended_topology(struct cpuinfo_x86 *c); =20 void cf_check early_init_amd(void); +void cf_check amd_ctxt_switch_masking(const struct vcpu *next); void amd_log_freq(const struct cpuinfo_x86 *c); void amd_init_de_cfg(const struct cpuinfo_x86 *c); void amd_init_lfence_dispatch(void); diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c index bb1624882499..3a04efef5028 100644 --- a/xen/arch/x86/cpu/hygon.c +++ b/xen/arch/x86/cpu/hygon.c @@ -32,7 +32,7 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c) { unsigned long long value; =20 - ctxt_switch_levelling(NULL); + amd_ctxt_switch_masking(NULL); =20 amd_init_de_cfg(c); =20 --=20 2.39.5