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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:49 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f91711f2-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450030; x=1770054830; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0xq1gxDlmDZY+78ggsqSHcLd3bC7dQoTKGaHnAMx1Ws=; b=PfisyyokdKc3ZaO2tC/0omKdYFa2G0kjAUIgx1c76VumZt1OxLX/OlOJiqmIS+QFbb 6GuJvf3NSkaLz8kJXkY1JJOq7+qGing23xT4/8X8dKeBopp1LkqSwS/XJwctE0QcjXDj gKa4I4Rge1582jpjC6VEywT6bqgxnW6zYjS2Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450030; x=1770054830; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0xq1gxDlmDZY+78ggsqSHcLd3bC7dQoTKGaHnAMx1Ws=; b=CDe30j+cAJ5ZhM9h/AwnmafSbCHPKDuyhW7LkF8+qSk25LMlGxwSdqxWpEK83TdNDu scpC5YMXYOmLIzns550sE0VRiiqqPeq9QQuZusxqZ0ciH5kxtWDznHjAB+VTUoNYxep3 KCPbEaA5QJ7UaQLdT+m/l1hZkAs91MehcGE1duUjwFijknjlYGgZCqkKWHFxTitw0Fdn kedq3itj7adE3NaocxfwIfhlocnmTvN76aIpqzaPSS5HA/M7BhTg+Q0cm3QzONocL86s 6JhmMeUT89DLqr6R6MOzOtuliGxbmTMymRYSbjV7o0rFKwnpjJTFJL3n69YREbkUGmg9 DAAw== X-Gm-Message-State: AOJu0YwtwcGsQwBf2IQyAesMrFxcKt1g+OP+M1HTJq8o5nUNZxS6Sx/m My2VoFEFSGLXvkbSKr7gFbPcgBjImNL8+of170bdvKvJUXsloYWUhU2ukgsgMaaTMWtCY5vzE9o ccgCF X-Gm-Gg: AZuq6aJoEWn49qyku+sHuOOok/XvSp+XzSvIHYWZ58Z6aXLIwQnChlYnrc6pYs6kfDM 2Np6sy4WT+lHGYOGNYzjIlMgQA30FEzlSTNRDI1rADQ/By13KxiP7F5inihMeydnA8daf5YKSJz SB5bW+4BSr0FD7Ck448BeruZKHaUxDcvb0muL6AxQ93UOjqaRdX3oo9ztrf3HyG32pxikH2ACcf uLkWd/bsigpUxTOUktkHJhsRR8GWyT+IRST/Q28ROnKJ5j5120qkhpkz1/YelvAZytX0tw7b2eV EkolpHzPs9r0Y2XKjpbsWAfp1jNK6q8yGE9DxgshsZjDm5xRNU0h1wBVWUhIMmpZ0TbfG6UJCKo Y3/0r1hlqWQM3ji1QOwL0ktK2cHYA5XMPZpbGC9cwPIOCjC55zq8I8sSXn4cT4yUYGGj+ehq/Z8 kVkNIgwb35tTLSUzSdkaPbpo/DiW3WtJyC6j5o3afy+GgxXrQdimAeTsMDakmgjQ== X-Received: by 2002:a05:600c:1993:b0:47e:e076:c7a2 with SMTP id 5b1f17b1804b1-4805ce4dd37mr88984935e9.15.1769450029713; Mon, 26 Jan 2026 09:53:49 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 01/16] x86/cpu: Fix boot time cache flushing Date: Mon, 26 Jan 2026 17:53:30 +0000 Message-Id: <20260126175345.2078371-2-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450068541158500 All 64-bit CPUs have CLFLUSH. AMD introduced it in the K8, Intel in the P4 Willamette core prior to 64-bit support, and VIA/Centaur in the Isaiah. Furthermore, the reported cacheline size is 64 on all CPUs to date. Arguably changeset 19435c10abf7 ("x86: consolidate/enhance TLB flushing interface", 2007) should have initialised c->x86_clflush_size earlier, but even at the time of changeset 3330013e6739 ("VT-d / x86: re-arrange cache syncing", 2022), early_cpu_init() had CLFLUSH-parsing logic but simply fail= ed to record the size. By removing get_cache_line_size() and assuming 16 bytes, the practical consequence for early IOMMU initialisation of SandyBridge era systems is to flush every cacheline 4 times (a pipeline stall too, as those CPUs could on= ly have one flush in flight at a single time). Record c->x86_clflush_size in early_cpu_init(), and panic() if CLFLUSH isn't found. Drop the redundant initialisation of c->x86_cache_alignment. Remove the fallback to 16 bytes in cache_{flush,writeback}(), opting instead for an ASSERT() to confirm that the logic hasn't been re-arranged too early. Fixes: 3330013e6739 ("VT-d / x86: re-arrange cache syncing") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/common.c | 7 ++++--- xen/arch/x86/flushtlb.c | 19 +++++++------------ 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index ebe2baf8b98a..f8c80db6eb1d 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -319,8 +319,6 @@ void __init early_cpu_init(bool verbose) uint64_t val; u32 eax, ebx, ecx, edx; =20 - c->x86_cache_alignment =3D 32; - /* Get vendor name */ cpuid(0x00000000, &c->cpuid_level, &ebx, &ecx, &edx); *(u32 *)&c->x86_vendor_id[0] =3D ebx; @@ -352,6 +350,7 @@ void __init early_cpu_init(bool verbose) if (edx & cpufeat_mask(X86_FEATURE_CLFLUSH)) { unsigned int size =3D ((ebx >> 8) & 0xff) * 8; =20 + c->x86_clflush_size =3D size; c->x86_cache_alignment =3D size; =20 /* @@ -380,7 +379,9 @@ void __init early_cpu_init(bool verbose) } else setup_clear_cpu_cap(X86_FEATURE_CLZERO); - } + } else + panic("CLFLUSH information not available\n"); + /* Leaf 0x1 capabilities filled in early for Xen. */ c->x86_capability[FEATURESET_1d] =3D edx; c->x86_capability[FEATURESET_1c] =3D ecx; diff --git a/xen/arch/x86/flushtlb.c b/xen/arch/x86/flushtlb.c index 23721bb52c90..1f8877dcab23 100644 --- a/xen/arch/x86/flushtlb.c +++ b/xen/arch/x86/flushtlb.c @@ -234,8 +234,7 @@ unsigned int flush_area_local(const void *va, unsigned = int flags) =20 if ( (!(flags & (FLUSH_TLB|FLUSH_TLB_GLOBAL)) || (flags & FLUSH_VA_VALID)) && - c->x86_clflush_size && c->x86_cache_size && sz && - ((sz >> 10) < c->x86_cache_size) ) + c->x86_cache_size && sz && ((sz >> 10) < c->x86_cache_size) ) { if ( flags & FLUSH_CACHE_EVICT ) cache_flush(va, sz); @@ -264,13 +263,11 @@ unsigned int flush_area_local(const void *va, unsigne= d int flags) */ void cache_flush(const void *addr, unsigned int size) { - /* - * This function may be called before current_cpu_data is established. - * Hence a fallback is needed to prevent the loop below becoming infin= ite. - */ - unsigned int clflush_size =3D current_cpu_data.x86_clflush_size ?: 16; + unsigned int clflush_size =3D current_cpu_data.x86_clflush_size; const void *end =3D addr + size; =20 + ASSERT(clflush_size); + alternative("", "mfence", X86_BUG_CLFLUSH_MFENCE); =20 addr -=3D (unsigned long)addr & (clflush_size - 1); @@ -301,11 +298,9 @@ void cache_writeback(const void *addr, unsigned int si= ze) if ( !boot_cpu_has(X86_FEATURE_CLWB) ) return cache_flush(addr, size); =20 - /* - * This function may be called before current_cpu_data is established. - * Hence a fallback is needed to prevent the loop below becoming infin= ite. - */ - clflush_size =3D current_cpu_data.x86_clflush_size ?: 16; + clflush_size =3D current_cpu_data.x86_clflush_size; + ASSERT(clflush_size); + addr -=3D (unsigned long)addr & (clflush_size - 1); for ( ; addr < end; addr +=3D clflush_size ) clwb(addr); --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:50 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f95da1ba-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450031; x=1770054831; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FPbCiqCcqf0/NbE9zeJiJem+K34lkoRlbsFPYopIEac=; b=uKXW59LQ+j6pC//HqjWHvCbuP2qjKwXraAW7xOlMuOCZIJrrj3m3FEdcVN/3+o9YML BSRDecAih92Sf8W+IL0CHtXVK3sgxM69+eRPUn3wuIJM4r2nINEp+P8ez7dYUb9daqBz TYgXIPsXZyCbxYD+JkrJ9i+YCyjEKLgSx2RbU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450031; x=1770054831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=FPbCiqCcqf0/NbE9zeJiJem+K34lkoRlbsFPYopIEac=; b=Cqv2cQzygRi/xZdgCjteKk3385jSajPtRHYU+2mwrz1sYp/nzSYtPrrvx0CXhIEFet MgN7DDQjCXBzZmrn3tVvJpmwZjLPSMVTWstjyMDj2N5fr1F5vrEYLJo5a7P7HoJ2//BQ Fah1sLkza91nOUvs8v2K49Tl8Io/u9ebrY/8/awRaBPctC8JwWEhMRCn9WAWmYGktEMt 5T0Qn23mrpgdWIt+iW6kj3FFev2tSP0Q958cvbqdSNZ+ZF3e75aZl5LbIll9jkgn6B27 DCkML4t0CELVF++e65fyk3b9pTSILF4ftN40sgbbzaOOHiP63YQRbLrXp9Apc/6OU2Qq 6Z3Q== X-Gm-Message-State: AOJu0YwZ8tfzxiQ0uAaxY0qaN51Q3a+/Eq2Sg527MZu3T7lEMh6sAOfs +coc14dyxS7WxSVlzrvK095l1WwcRvKHauhVuzswCMkVsuNPHgVMMQR6flBtcc05UlmLraqJrBr urReF X-Gm-Gg: AZuq6aL3ohplvANNSvzSYoD8NdqTfJvrIw2RtPeonE+Z624sxeX7kIrHjQjCnpPd2v7 XUJgryDlnA0n+AuFj5leTYfCu2TBOVEowEgZrxkgCdUZP8j0boGQQEcrUJYLWh5gmjfTeOjaMpD p1EOgiAysmfZLxKRULWwPnW1XXwKkfQEAf4R4AK+yGvtybv6IrwZDyLgznYszTEvsQSEpz9uhZW wf2JEvUbywuqObmNx4zXBtmYBZ9yzwo74RHnwURUTzYQ41i6C5Gigluvyd0cy/pqkYXfI8JQ38x GdP/YbxseLeGndrVeASFYGehZponJgOpJChocO5iiMALq8d81merU2pOzYoLRtLk0+rbqzuc/on T/jZwxRhQPi9BrtWS5WBF3LnbkPfJGKz44IwRgF7hV0LRPkCK2ymAzFalde54zGHditCW34FI31 0mVBO4tF2YfV47VgSnGhxHujOkVBsBDOz4CePbwXE2o/0V5fRk/DZ/ZgQV3yq+rA== X-Received: by 2002:a05:600c:444c:b0:47e:e779:36e with SMTP id 5b1f17b1804b1-4805cf67274mr86300515e9.19.1769450030306; Mon, 26 Jan 2026 09:53:50 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 02/16] x86/cpu: Drop cpuid_level adjustment from generic_identify() Date: Mon, 26 Jan 2026 17:53:31 +0000 Message-Id: <20260126175345.2078371-3-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450072266154100 early_cpu_init() calls intel_unlock_cpuid_leaves(), which arranges for the boot trampoline to make the adjustment for all APs, meaning the call from early_init_intel() is a no-op. Drop it, allowing intel_unlock_cpuid_leaves= () to become __init code. In turn, the adjustments in generic_identify() were a no-op too. Nothing in the c_early_init() hooks modifies the 1c/1d features, so their values in c->x86_capability[] are still good from just above. The ebx variable used to calculate c->x86_clflush_size is still good too, b= ut move the logic earlier so it's more obviously correct. Fixes: fa4d026737a4 ("x86/Intel: unlock CPUID earlier for the BSP") Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/common.c | 10 +--------- xen/arch/x86/cpu/intel.c | 4 +--- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index f8c80db6eb1d..dda0d5d39c92 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -479,6 +479,7 @@ static void generic_identify(struct cpuinfo_x86 *c) cpuid(1, &eax, &ebx, &ecx, &edx); c->x86 =3D get_cpu_family(eax, &c->x86_model, &c->x86_mask); c->apicid =3D phys_pkg_id((ebx >> 24) & 0xFF, 0); + c->x86_clflush_size =3D ((ebx >> 8) & 0xff) * 8; c->phys_proc_id =3D c->apicid; =20 /* @@ -502,15 +503,6 @@ static void generic_identify(struct cpuinfo_x86 *c) if (actual_cpu.c_early_init) alternative_vcall(actual_cpu.c_early_init, c); =20 - /* c_early_init() may have adjusted cpuid levels/features. Reread. */ - c->cpuid_level =3D cpuid_eax(0); - cpuid(1, &eax, &ebx, - &c->x86_capability[FEATURESET_1c], - &c->x86_capability[FEATURESET_1d]); - - if ( cpu_has(c, X86_FEATURE_CLFLUSH) ) - c->x86_clflush_size =3D ((ebx >> 8) & 0xff) * 8; - /* AMD-defined flags: level 0x80000001 */ if (c->extended_cpuid_level >=3D 0x80000001) cpuid(0x80000001, &tmp, &tmp, diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 584588e406f2..d585161dd32f 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -310,7 +310,7 @@ static void __init noinline intel_init_levelling(void) } =20 /* Unmask CPUID levels if masked. */ -void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c) +void __init intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c) { uint64_t misc_enable, disable; =20 @@ -335,8 +335,6 @@ static void cf_check early_init_intel(struct cpuinfo_x8= 6 *c) bootsym(trampoline_misc_enable_off) & MSR_IA32_MISC_ENABLE_XD_DISABLE) printk(KERN_INFO "re-enabled NX (Execute Disable) protection\n"); =20 - intel_unlock_cpuid_leaves(c); - /* CPUID workaround for Intel 0F33/0F34 CPU */ if (boot_cpu_data.x86 =3D=3D 0xF && boot_cpu_data.x86_model =3D=3D 3 && (boot_cpu_data.x86_mask =3D=3D 3 || boot_cpu_data.x86_mask =3D=3D 4)) --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450071; cv=none; d=zohomail.com; s=zohoarc; b=Lt9L6cdcP4pDnar/tmt6+yBNr/jdXtWtpTRShAnEnFKlfpQFe/uWFCBqzMvO/1jhmB4tZrwp0bwwwqTI7A5kecyB4q04sSlbxBPk3+I4Y3IXaA/qhIf4PLSWHINpB5dssMGfkpjcZvS2Km3cmwuV54t8fnzjl20GqjJTBJz+9IU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769450071; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zyRXQCzMht59KNrjuruuDRnKF4fVxlGPuMfpmypUDsw=; b=Y5biQk7fOVw3hIS121f2fkuNaZU7vmdkn2LhI1KqXFqi3rKc1Hp7iaNhYp9pVKcb6ACFFU1NYukpQ7929Z0ZWTInBQR3hs1xI7jsHxW9QgNjMLtFI5/8OyxmmidQFa4DirOLHEUyZiuEGj5DWdYpYneOBgf3mWn0nBUa9j1du8k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769450071099827.5064330931913; Mon, 26 Jan 2026 09:54:31 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1213832.1524293 (Exim 4.92) (envelope-from ) id 1vkQmi-0004lT-6R; Mon, 26 Jan 2026 17:53:56 +0000 Received: by outflank-mailman (output) from mailman id 1213832.1524293; Mon, 26 Jan 2026 17:53:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmh-0004iV-Ub; Mon, 26 Jan 2026 17:53:55 +0000 Received: by outflank-mailman (input) for mailman id 1213832; Mon, 26 Jan 2026 17:53:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmg-0004HX-JQ for xen-devel@lists.xenproject.org; Mon, 26 Jan 2026 17:53:54 +0000 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [2a00:1450:4864:20::32f]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id f9452f2f-fadf-11f0-9ccf-f158ae23cfc8; Mon, 26 Jan 2026 18:53:51 +0100 (CET) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-47ee3a63300so54601965e9.2 for ; Mon, 26 Jan 2026 09:53:51 -0800 (PST) Received: from localhost.localdomain (host-92-26-102-188.as13285.net. [92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:50 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: f9452f2f-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450031; x=1770054831; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zyRXQCzMht59KNrjuruuDRnKF4fVxlGPuMfpmypUDsw=; b=P0MOH0fmzKdVPVOgODqc0ejXooP6WD/ethCQC5LKp6eElyFAZQ0UI/EKzSsDW/2+6z eX8f8+q+o2bE1yuUPPwJkM3sZaLHTMEnAq6YHHo/0vtwGbmEGgkDOXUVx3HXIHvLOoUX FthmN8rXvAoCUC2yFAlTG0ZYLNJihJIDfHJiw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450031; x=1770054831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=zyRXQCzMht59KNrjuruuDRnKF4fVxlGPuMfpmypUDsw=; b=aapvZCnwpqhsrkEz8YU7ZSX7HHehnD6B6owZ+QANk9MAgUZ9FXgfxuIujdSBB9ysHY xyiSVH91bF6E6sY1RXd/SeKONsZgrnfFdyrwz+pyqOwyLvOySx9sPWzj278lqfplStJ9 y4V5rwDz69ECh1u3nIt0Rr8feQ7JnS/MnDUsWaqj6CDtfyL5L+W1SXtKHRPa1ASGHgKx aLIQo53c47N8iQzrTA/uXYGqYI48h7GtdNnirJZfqKkClXCgwKz17mWliw7PcNe2+ePp xNkZ7ZUnNyT1WaMI/gEJTrkppRfLEH16JKI/L7pxqRCLBgs0LLc3CnCqTBNyC2fUqx+y bZBA== X-Gm-Message-State: AOJu0YxYVhYi6WAAY8Rbo1X1xVDMpZP+hFrgYtJusYf8ulpoQH22fbgU dW8uQq6gOfzEeEkUgaiBBpCmOlIOSv5GnLFMsGuaZjRQGCR5W+s9/NjVire6AkyscUr8gEhc0/s Ww18+ X-Gm-Gg: AZuq6aKnv7W1HkceKpc6d547aoEy/qjLwlPrhVuxfSU2mUbT9Hze1XZW1mgcofTOsYQ DTkyr0zcqqpyL7n6838JbfmBJTq6be5TX/P4w8Z/7VxwIeDl9TYNrBF8vZmCX0DgbL5rr/S5t+n XZPbhP87cs2J3t435g2TX4BsUGhAYDIVuFTmcX7LtIw0xDuoft/YAYdrMeFHJE6j441IFRusj6D J3pm3AFCVHvP4CrRlaFvpEMupyt8kvaI4+j+uggyJ36oIPvH4kuZ0hV1lslpWwKe/TjOCyFpEN8 OUpzEl7pnig79VhVGMpDapm7ZgxAuntyyLCHJet3e6W6v7xM7QoDCtK2H2lKsa7AgcAyJi1YC2h 8jqoGvCklMETZr8bmuLFNoWxa7ysPF+yI1PFWjgIy6QTR8WIU0RxRgfcYhxrA32c9DJpG48TudU GCJziuGsKJhw+efB4EGnCRZyTG0I/hXLE4rbfhftio7nBOP7PGB+DKKf7W5bZ4RmaAAzWxjWqr X-Received: by 2002:a05:600c:1e2a:b0:471:14b1:da13 with SMTP id 5b1f17b1804b1-4805ce4dec1mr81666095e9.14.1769450030839; Mon, 26 Jan 2026 09:53:50 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie , Kevin Lampis Subject: [PATCH 03/16] x86/intel: Drop the paddr_bits workaround for P4 Nocona/Prescott CPUs Date: Mon, 26 Jan 2026 17:53:32 +0000 Message-Id: <20260126175345.2078371-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450072038154100 These are 32bit CPUs only. 64bit support started with model 4 (Prescott-25= 6). Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie CC: Kevin Lampis This ideally wants backporting to 4.20 along with the rest of the VFM clean= up in order to support DMR/NVL, which ends with removing the x86_ prefixed nam= es. --- xen/arch/x86/cpu/intel.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index d585161dd32f..eec6ee763040 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -335,11 +335,6 @@ static void cf_check early_init_intel(struct cpuinfo_x= 86 *c) bootsym(trampoline_misc_enable_off) & MSR_IA32_MISC_ENABLE_XD_DISABLE) printk(KERN_INFO "re-enabled NX (Execute Disable) protection\n"); =20 - /* CPUID workaround for Intel 0F33/0F34 CPU */ - if (boot_cpu_data.x86 =3D=3D 0xF && boot_cpu_data.x86_model =3D=3D 3 && - (boot_cpu_data.x86_mask =3D=3D 3 || boot_cpu_data.x86_mask =3D=3D 4)) - paddr_bits =3D 36; - if (c =3D=3D &boot_cpu_data) { uint64_t misc_enable; =20 --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450071; cv=none; d=zohomail.com; s=zohoarc; b=DkMt7tJVwJ17GMP8MHI0QmQWKPOdWzjIavQC7w5fGPYYQM5+8wCxXT98KB1hm3MVvolS0IPhwvVHxD5rmwVR0iffC4oICfQeq6V32IIw5MJGbwq4I7RyCxRoXYrHOjfqcsoUKiPzTTtM4LfcejgBm27dvzKlkhkz6XCzB400pAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769450071; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=wsIV3GSMS2OCjsSf5BdBf2D2nbqVVoqe/FAvijXoOlA=; b=GIq/3Gtv58qLBNLjniHf4rNqiB/Dv+V80scUIRyW82Q0QNI1Ms1Yqrdvt0y5tb3QpdBCK+IOOS4L2MFFqgwd5GgQ3GD8c3ClaWSB00IMLxiD+wOLRKoMHcsE117zKyYpWBmEmOwOGet7nI3nl0TR5r4n9rfHA1UjXzUNuT1UbBQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769450071589102.59470358480257; Mon, 26 Jan 2026 09:54:31 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1213833.1524300 (Exim 4.92) (envelope-from ) id 1vkQmi-0004qw-Hq; Mon, 26 Jan 2026 17:53:56 +0000 Received: by outflank-mailman (output) from mailman id 1213833.1524300; Mon, 26 Jan 2026 17:53:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmi-0004pK-8k; Mon, 26 Jan 2026 17:53:56 +0000 Received: by outflank-mailman (input) for mailman id 1213833; Mon, 26 Jan 2026 17:53:55 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmh-0004HX-JX for xen-devel@lists.xenproject.org; Mon, 26 Jan 2026 17:53:55 +0000 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [2a00:1450:4864:20::32b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id fa3b9054-fadf-11f0-9ccf-f158ae23cfc8; Mon, 26 Jan 2026 18:53:53 +0100 (CET) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4801c1ad878so53447625e9.1 for ; Mon, 26 Jan 2026 09:53:53 -0800 (PST) Received: from localhost.localdomain (host-92-26-102-188.as13285.net. [92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:51 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fa3b9054-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450032; x=1770054832; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wsIV3GSMS2OCjsSf5BdBf2D2nbqVVoqe/FAvijXoOlA=; b=Dimz2o6IP30qbChwn9FSVKkJRXwqn6l5pEezSjPIhlB0rsHPYWtsKC9ZQbDfxD2RKr kAlviDslBgwal05Fl+4aVoCnhQRJv6D55PVh/Rxt2cDA/flOO59Suu5fbLwHI1JpRi4O 21U8llMdBZrWHBRI4ROphIbJhhHRUCquR+uFo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450032; x=1770054832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wsIV3GSMS2OCjsSf5BdBf2D2nbqVVoqe/FAvijXoOlA=; b=FxsPntkiUvKBqE+/2fWKst5GJYbeItDhTEAhMJoYODmqcC6GqrcXv9DyJ5GQD34dFX lUTRf1tT47c6m+5sBRhA9s9zf/QbL47DBXm3KUOSQ7IrGDccyUEGj6YxQ4x0AzRw9++u V25ictWw6Xb1NV7lgDka5qhRhvz0VsUksCoduPLAh8UAz2arR1Epp+1IwdLYXETD9I12 3acg1vTfS5TikGgH+jBfc0BnywRUIHpu9Lvu7Ohiu7tObn+2GPWLefzoNtknsf534EGC WQZoBxKe6q1FhHQGgvSaylZ75FXKLkbDqNcj+xM1WqCzAJ4d9hzUwiZR7hywEzSwmPOT KGeQ== X-Gm-Message-State: AOJu0YwK0/QhksK3FHwy0KBX3l4FG8Avgtska0sKWNAEn7FFf4TEDejl iQZ62507S1XEeWOQdgdVnYLuL3m2Z5Xlmg/JfE8idhZ/dn9uWRbhiraWwKwH6F9OMsd74S5Zx+F olb5y X-Gm-Gg: AZuq6aKr7K04PYbwrZJ9pnbunzAad3oWhlBZvathkl/wuxsh+AWOYku3mfnutgnwJyd Vp8CV59VQowAyYwdqy/HYz1uSdOwAj3Z75zG2M+u/AOpDiqIkTLZ0FvhJb5jE6oFnmD4Vbm/6qS 10oPhqUuDzt0vGZle7lPAtTHmjAYG9bowYfFO/dtFsUkhQs+Z+ynJneS/UKzVEXL5VPlRXHL05L ELQ/kSI+EAAl3nrtI7m9SXaK8u+Dfsxdt4ExPxHSupFbZIpODh/fWtO9VWaRMkJM49TxDQf0nvn Ie5Au6Afvi+VBAJ4UfssD8ZAhKyrra5UvJahPhPidjBoEQfJyCG1XFYuCtOfaqGWqYA6mYe7gXX a5BYwZHS8+n5TNk3B3Inj8ZZZ1Sd0gwV1AWIcXeYz/Oh+93yYc+fboG77gggHkmk0pQEKaukkGp nItEj7xfTFdy2a/O4tkNsHCr8ia4z68il065UfSElP4TDcDl0fM7JnJnSkPTW7Pw== X-Received: by 2002:a05:600c:b95:b0:477:58:7cf4 with SMTP id 5b1f17b1804b1-4805ce3fccamr78919025e9.4.1769450031770; Mon, 26 Jan 2026 09:53:51 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 04/16] x86/cpu: Fold generic_identify() into its single caller Date: Mon, 26 Jan 2026 17:53:33 +0000 Message-Id: <20260126175345.2078371-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450072523158500 This makes the correctness of future changes more obvious. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/common.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index dda0d5d39c92..89b58e6182b9 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -455,10 +455,13 @@ void reset_cpuinfo(struct cpuinfo_x86 *c, bool keep_b= asic) CPU_DATA_INIT((*c)); } =20 -static void generic_identify(struct cpuinfo_x86 *c) +void identify_cpu(struct cpuinfo_x86 *c) { uint64_t val; u32 eax, ebx, ecx, edx, tmp; + int i; + + reset_cpuinfo(c, false); =20 /* Get vendor name */ cpuid(0, &c->cpuid_level, &ebx, &ecx, &edx); @@ -550,17 +553,6 @@ static void generic_identify(struct cpuinfo_x86 *c) c->x86_capability[FEATURESET_m10Al] =3D val; c->x86_capability[FEATURESET_m10Ah] =3D val >> 32; } -} - -/* - * This does the hard work of actually picking apart the CPU stuff... - */ -void identify_cpu(struct cpuinfo_x86 *c) -{ - int i; - - reset_cpuinfo(c, false); - generic_identify(c); =20 #ifdef NOISY_CAPS printk(KERN_DEBUG "CPU: After vendor identify, caps:"); --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450072; cv=none; d=zohomail.com; s=zohoarc; b=kNdXfypueLn5Gn1gW6lrNdk4DloHkkHbtkC98sjOr4jBlM1i0epLFGKZrPmNIOT+qpjmhnIRshLk+tpcl7vIobpZJ1GCzjCDdW8RRIJi1E01F3fH/qFj1wc4Z1C1MfGrd727v3NZGcKEqhTrnRTb8IQ+j8h02WSKp0JTqVeQyPI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769450072; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SVFZKPX+rQ8GQmkwaOmVq1QfQ8v/dwJRo6+jPX9Dkm8=; b=FII/KPRm7HHp/upIreF67jieZdLGW0wiGDkljtKMyhtg0y63SLgWn59eayuM1bGdhkNihQDjT0DS4gq5xzNIo+upu6bn8Y+guM44kojgefQnuroqGuSdEBMtKPBqozu7VA2uE1+DIwnFKFaUu/q7tUc+cUN6aRPqN2aJVRFnHJk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769450072881789.4746417818212; Mon, 26 Jan 2026 09:54:32 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1213831.1524282 (Exim 4.92) (envelope-from ) id 1vkQmh-0004Xf-Ij; Mon, 26 Jan 2026 17:53:55 +0000 Received: by outflank-mailman (output) from mailman id 1213831.1524282; Mon, 26 Jan 2026 17:53:55 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmh-0004Tl-Bs; Mon, 26 Jan 2026 17:53:55 +0000 Received: by outflank-mailman (input) for mailman id 1213831; Mon, 26 Jan 2026 17:53:53 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmf-0004HW-Mq for xen-devel@lists.xenproject.org; Mon, 26 Jan 2026 17:53:53 +0000 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [2a00:1450:4864:20::32d]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fa6536aa-fadf-11f0-b15f-2bf370ae4941; Mon, 26 Jan 2026 18:53:53 +0100 (CET) Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-47ee301a06aso55313495e9.0 for ; Mon, 26 Jan 2026 09:53:53 -0800 (PST) Received: from localhost.localdomain (host-92-26-102-188.as13285.net. [92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:52 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fa6536aa-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450032; x=1770054832; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SVFZKPX+rQ8GQmkwaOmVq1QfQ8v/dwJRo6+jPX9Dkm8=; b=P5S1xDUJCNyQG6IbahEYbDcJgsxRGwxBQ6SKXjhtDSpPesxnWhaY4T00BJQtND38Mk E5uDTW5eDbo2BNhmyD7EvTdGrOHHdrKLITE+3UAH8mGCAVOCxSp/K8Ncf8JrRE1mJQ/H r2hCebZoFt88ndlyphl/ZNjPYFrkMDpRPRF7M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450032; x=1770054832; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=SVFZKPX+rQ8GQmkwaOmVq1QfQ8v/dwJRo6+jPX9Dkm8=; b=BOGTLRcph9WgxQqQk3o5MjcsVx8HIKWbdCOVfDf+0x50JkOr4CZuBO1LkLL+SfPz94 g3QG7yAFsfq992ShOd1AuVpjtxEJ6K7TT47ljFgDwnSfqTzGobYaOoTtjuIJ7sfSZG5b 8/he8eBfIYLeH9PjAGBSu8nnYz6op90cJ/A+QVrxf8xnYvwSw4EYPi0kzUSGrUChtkI6 ZPP5IvAeb2dBv5OtcIIIfiZXlZZpG70QUXr/rHqCPXh/3iXrvCjrMUGqI6SJIvqRfidX Jrly2E9hT5WDNRbLBKTYvmOZ1QErVv+jwn0yS0n9wxXPr7ZeQjsSxsBkd6ZB5jvzn4xr qOVw== X-Gm-Message-State: AOJu0Yw+QEvZy9w2bsrF4U/5vlXsAQE12I8p+Ln+FojK+E6oNJFsvWkK O37qipBNkCljwbpNlm26rJjWS3T+xZvXlTMLbWJj++ESSlS3OdHVJv9jtpVoTzFkHVa1+13K0w1 jR1Nq X-Gm-Gg: AZuq6aLImjM8Uae1dH94byu1ln6wTch/kOKuD+hR2ZK64fktNy7d3a3mXuxtzh2zJzE w1hc5ST+U0AzJfZse3VcAlAj+S3g3/ys2ZsyUTxoVe+d1TEqs97JN5NQUeiJDtPMOQxPiFJKhYf tcwh7Js2Pp5ezzNI+p4/zpXl56te1uWwAVWGtVvCerEa/BJewYNw+xc3GntnnyBTOXv2N6Fhrmt JNymRnmmj6wv4hR3GAztg/RushXEHYe4Rbjx6GpRfMT5Q3y/q+3AilHAfRX6wY5nb9h2VDLitS2 ALcHpgn4dBviFFUE2zkJTcXHQ6TlWo53BF1wuqtHxJGqymXtU08bK2G5UTeQJ9yJHVg1oHPmT8l MSxXWxlLDt9mSuqj7rSkhvTNpOrWUiKY5DDdFyi1u9L2WxvjWiXwlDOFlAkj4hYVLV9t9Xp+R69 z1x4g4fBa5Rb1FdfIQjPuYy4BW2EEJdYKRArk088Pood/KCoPp82Fv34YVrPtjfQ== X-Received: by 2002:a05:600c:35ce:b0:47d:3ead:7440 with SMTP id 5b1f17b1804b1-4805d06c428mr85483385e9.32.1769450032374; Mon, 26 Jan 2026 09:53:52 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 05/16] x86/cpu: Move per-CPU actions out of the vendor early_init() hook Date: Mon, 26 Jan 2026 17:53:34 +0000 Message-Id: <20260126175345.2078371-6-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450074557158500 cpu_dev.c_early_init() and .c_init() is a spilt we inherited from Linux. In Xen, these are called moments apart in identify_cpu(). The only logic between the two calls is filling part of c->x86_capability[] and collecting the the long model name. We are going to want to repurpose .c_early_init() somewhat, so move the log= ic wanting running on all CPUs to the .c_init() hook, which is only marginally later. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/amd.c | 4 ++-- xen/arch/x86/cpu/hygon.c | 2 ++ xen/arch/x86/cpu/intel.c | 12 ++++++------ 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index fc496dc43e08..970cb42e9e0b 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -621,8 +621,6 @@ void cf_check early_init_amd(struct cpuinfo_x86 *c) { if (c =3D=3D &boot_cpu_data) amd_init_levelling(); - - ctxt_switch_levelling(NULL); } =20 void amd_log_freq(const struct cpuinfo_x86 *c) @@ -1018,6 +1016,8 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) u32 l, h; uint64_t value; =20 + ctxt_switch_levelling(NULL); + amd_init_de_cfg(c); =20 if (c =3D=3D &boot_cpu_data) diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c index b99d83ed4d75..bb1624882499 100644 --- a/xen/arch/x86/cpu/hygon.c +++ b/xen/arch/x86/cpu/hygon.c @@ -32,6 +32,8 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c) { unsigned long long value; =20 + ctxt_switch_levelling(NULL); + amd_init_de_cfg(c); =20 if (c =3D=3D &boot_cpu_data) diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index eec6ee763040..141dc2368143 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -327,10 +327,6 @@ void __init intel_unlock_cpuid_leaves(struct cpuinfo_x= 86 *c) =20 static void cf_check early_init_intel(struct cpuinfo_x86 *c) { - /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ - if (c->x86 =3D=3D 15 && c->x86_cache_alignment =3D=3D 64) - c->x86_cache_alignment =3D 128; - if (c =3D=3D &boot_cpu_data && bootsym(trampoline_misc_enable_off) & MSR_IA32_MISC_ENABLE_XD_DISABLE) printk(KERN_INFO "re-enabled NX (Execute Disable) protection\n"); @@ -350,8 +346,6 @@ static void cf_check early_init_intel(struct cpuinfo_x8= 6 *c) =20 intel_init_levelling(); } - - ctxt_switch_levelling(NULL); } =20 /* @@ -615,6 +609,12 @@ static void init_intel_perf(struct cpuinfo_x86 *c) =20 static void cf_check init_intel(struct cpuinfo_x86 *c) { + /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */ + if (c->x86 =3D=3D 15 && c->x86_cache_alignment =3D=3D 64) + c->x86_cache_alignment =3D 128; + + ctxt_switch_levelling(NULL); + /* Detect the extended topology information if available */ detect_extended_topology(c); =20 --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450072; cv=none; d=zohomail.com; s=zohoarc; b=Cv9tqA8rJFuXrYjpc0SS8OpbaVNhNCxe6of414TtLV6Rtouz83/SksLOrZPJKQdTO/zGkexcZfTQpd39Vcq3+H83Z+Fl9ONTeBvP39zTWdTb7Ah9I5UNInIvUbSptaaIeAbJe7R2axcikwigKv+EiVLnaIRaa+wb08eUpwBzXvo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:52 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fada5a50-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450033; x=1770054833; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t6MpUKLCLKO3nERYaHJXRPiOdgAVGABSBDex8VMPnrc=; b=n+em5QK2h2wfDH+FC5a1Nfxh5YXfsF6upNPqqPXfCiculxY0HY7ZkJW5kfpOHNeecp QMv8RFxBCu4jcd6T14gt+5Oild1shHzTGBszYW28PWIsCLoI/VYtQ6USxIwMAq67I6Fb /5yOs6xmWOl8NGmban23vGZ0MmJBkcpEza7Xg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450033; x=1770054833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=t6MpUKLCLKO3nERYaHJXRPiOdgAVGABSBDex8VMPnrc=; b=HNG+/xsMCg8QCR2RWAZaFWEVUgCfQl1fApPfWJmOts31ld1pPfOL2Gvtr5U2diMV73 AjmkTrmXrJpC5PbGbqUzT1/HY5I1G0LdZykCC5Ae7YUN2eiy64Ks9rlBSaTSJXK0+Ko+ XrrGri50CWYSBurNZnMDDc05ZncQtu2qJaBPwtSpyXD6aKEi2JxRFyJif81uUqbapqzi 7foDANcv9ylKPT/ggFP1XZljpdab+xpCEfzPoIiKUPT7DAbhdvVZDz9d6kj85d6anFKC MbPmrLBDxVQZAUJpn/WwbtvdGZ+K5n5KTjezqMH5m+Cl13VF2WvlKweC+5fY6KUpn2Xq gSig== X-Gm-Message-State: AOJu0Yz1DLzH92NhP3FKYDmkhHr4TJ4VZPXrjM1dPbYggVWLQsoZ98XJ Y4JmkqnAjRPhodrld0AwPOckmQ8T/TDO9FFt7p+YadgIIM5i/Xm3h9gUW9OAQ2bQZB+BpPvCyE+ 8wJAu X-Gm-Gg: AZuq6aLwAEzn6DySUzm17FzeMdD09MPBlb1bBl3sKpOokZvr//yRUoOoEH+7bWdb/ah WPeI7igxPgQwY9q4sJPbuj9rbh8c721JFlj5a8czPEZqX+LxpYI8feSTtbr268raVkQ2bWBUA4y u960h5pasSnmBbHvDEXBT+IyMh8YS0wkwjAl7G2ZxRc1FoRajbFdu2o7SK/TXFbSirAQ+7dSxVg 9y8jJDKstidXfrUNrjfamW83LNwuKTgAsGmxIhtr8q5AAdQDp2e11/4LteKtWGNtOnUd/X+mdPf uhma9opxuiajaTxDXNjz2yB/GBK851lKBPxVWkccfGiMlSMlQrZyGYuY9KnUiAXi0j6gvlW+W6v 9N5pwyFT+EyhiORK26ajnYfXlJ6GojEoUjuwd2reFNBvEfFwNeBpfZE1Ojh+FGXKtUHVkGZ2sqh eqIwQ6m8KM7Y/RtA7M8TP+x8x9JiXVXIr52F3Ic4V7cHGF2jy/kI0o8HdwqHgyLQ== X-Received: by 2002:a05:600c:681b:b0:47b:deb9:163d with SMTP id 5b1f17b1804b1-4805dd41a1cmr77379775e9.7.1769450033429; Mon, 26 Jan 2026 09:53:53 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 06/16] x86/cpu: Rework the vendor early_init() hooks to be __init Date: Mon, 26 Jan 2026 17:53:35 +0000 Message-Id: <20260126175345.2078371-7-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450074122154100 All interior actions are now conditional on c =3D=3D &boot_cpu_data, so rea= rrange it to the caller in identify_cpu() and drop the hook parameter. This allows early_init_$VENDOR() to become __init, which in turn allows $VENDOR_init_levelling() to cease being noinline. Reposition the early_init_intel() function simply to make diff legible. No functional change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/amd.c | 7 +++---- xen/arch/x86/cpu/common.c | 4 ++-- xen/arch/x86/cpu/cpu.h | 4 ++-- xen/arch/x86/cpu/intel.c | 42 +++++++++++++++++---------------------- 4 files changed, 25 insertions(+), 32 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 970cb42e9e0b..36fea2e0a299 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -224,7 +224,7 @@ static const typeof(ctxt_switch_masking) __initconst_cf= _clobber __used csm =3D * avoid this, as the accidentally-advertised features will not actually * function. */ -static void __init noinline amd_init_levelling(void) +static void __init amd_init_levelling(void) { /* * If there's support for CpuidUserDis or CPUID faulting then @@ -617,10 +617,9 @@ void amd_process_freq(const struct cpuinfo_x86 *c, *low_mhz =3D amd_parse_freq(c->x86, lo); } =20 -void cf_check early_init_amd(struct cpuinfo_x86 *c) +void __init cf_check early_init_amd(void) { - if (c =3D=3D &boot_cpu_data) - amd_init_levelling(); + amd_init_levelling(); } =20 void amd_log_freq(const struct cpuinfo_x86 *c) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 89b58e6182b9..39e64f3a5f88 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -503,8 +503,8 @@ void identify_cpu(struct cpuinfo_x86 *c) if (c->extended_cpuid_level >=3D 0x80000021) c->x86_capability[FEATURESET_e21a] =3D cpuid_eax(0x80000021); =20 - if (actual_cpu.c_early_init) - alternative_vcall(actual_cpu.c_early_init, c); + if (c =3D=3D &boot_cpu_data && actual_cpu.c_early_init) + alternative_vcall(actual_cpu.c_early_init); =20 /* AMD-defined flags: level 0x80000001 */ if (c->extended_cpuid_level >=3D 0x80000001) diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h index bbede57ab00d..0fc6370edb13 100644 --- a/xen/arch/x86/cpu/cpu.h +++ b/xen/arch/x86/cpu/cpu.h @@ -4,7 +4,7 @@ #define X86_CPU_H =20 struct cpu_dev { - void (*c_early_init)(struct cpuinfo_x86 *c); + void (*c_early_init)(void); void (*c_init)(struct cpuinfo_x86 * c); }; =20 @@ -19,7 +19,7 @@ extern void display_cacheinfo(struct cpuinfo_x86 *c); extern void detect_ht(struct cpuinfo_x86 *c); extern bool detect_extended_topology(struct cpuinfo_x86 *c); =20 -void cf_check early_init_amd(struct cpuinfo_x86 *c); +void cf_check early_init_amd(void); void amd_log_freq(const struct cpuinfo_x86 *c); void amd_init_de_cfg(const struct cpuinfo_x86 *c); void amd_init_lfence_dispatch(void); diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 141dc2368143..2aeeb2f5bf55 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -251,7 +251,7 @@ static const typeof(ctxt_switch_masking) __initconst_cf= _clobber __used csm =3D intel_ctxt_switch_masking; #endif =20 -static void __init noinline intel_init_levelling(void) +static void __init intel_init_levelling(void) { uint32_t eax, ecx, edx, tmp; =20 @@ -325,29 +325,6 @@ void __init intel_unlock_cpuid_leaves(struct cpuinfo_x= 86 *c) } } =20 -static void cf_check early_init_intel(struct cpuinfo_x86 *c) -{ - if (c =3D=3D &boot_cpu_data && - bootsym(trampoline_misc_enable_off) & MSR_IA32_MISC_ENABLE_XD_DISABLE) - printk(KERN_INFO "re-enabled NX (Execute Disable) protection\n"); - - if (c =3D=3D &boot_cpu_data) { - uint64_t misc_enable; - - check_memory_type_self_snoop_errata(); - - /* - * If fast string is not enabled in IA32_MISC_ENABLE for any reason, - * clear the enhanced fast string CPU capability. - */ - rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); - if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) - setup_clear_cpu_cap(X86_FEATURE_ERMS); - - intel_init_levelling(); - } -} - /* * Errata BA80, AAK120, AAM108, AAO67, BD59, AAY54: Rapid Core C3/C6 Trans= ition * May Cause Unpredictable System Behavior @@ -413,6 +390,23 @@ static void __init probe_mwait_errata(void) } } =20 +static void __init cf_check early_init_intel(void) +{ + if ( bootsym(trampoline_misc_enable_off) & MSR_IA32_MISC_ENABLE_XD_DIS= ABLE ) + printk(KERN_INFO "re-enabled NX (Execute Disable) protection\n"); + + check_memory_type_self_snoop_errata(); + + /* + * If fast string is not enabled in IA32_MISC_ENABLE for any reason, + * clear the enhanced fast string CPU capability. + */ + if ( !(rdmsr(MSR_IA32_MISC_ENABLE) & MSR_IA32_MISC_ENABLE_FAST_STRING)= ) + setup_clear_cpu_cap(X86_FEATURE_ERMS); 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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:53 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fbb7a6fe-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450035; x=1770054835; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+wd9T6LoaSruhHAOhpkCe8Gt28xOELGHhuvCSdvapew=; b=Us8fo0QRFyEldxIlsunrIgIR5nFIxed7o3TXza1Ty80L982vmxOA6dLxSgtNbNLpv5 i/YwqVGueNFMnxdpDY5O7rfTX62tln7fhHvLU54fh5qm4fTInJWiAEmGwI5pGgwcAHaF zjaNu47wwWWGt86EN/rEFB548h/6JNGWfc5h0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450035; x=1770054835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=+wd9T6LoaSruhHAOhpkCe8Gt28xOELGHhuvCSdvapew=; b=ihAVghvFLcYQnNOi6G+2ret7I4IdLEU0NwjAuIP4R67/5umZFgGd2LYAhnIgElxp7j 5nJ3iDssTdqjBumPCnhdx3hdFJIBATswD7WdTiSk4PC+CV6L0CE1VOQxO5TGBu/CZOzt WIWxjN05BgxK2IzKI9igttKaMnQ3FuTh2eoaemPfpkaDwb0+vRznVLFHuEjrc+2lHfo0 NtW30bvCeF7MtuvLG6zkVWZYNGBdGM7u5qu8na7wMgs1tRVx1pPhEAbto6j7HgogVn0f v5dOzPO2D6ZwaPGUnQzjZBv08mncGK+3i/OQtM6AVUieKrcsjWx/hIxVetLXmI5Ry2qm wy5g== X-Gm-Message-State: AOJu0Yx+wnOg1t6zlNHur4r0hIQaQmd5glCZlWBZ+Jb1n5QPej61ETf7 loweWQAu7i8Qg7RKb/O5WMaR2l4rNVk2lvUwyXO5B7Gu5TL8/ynDlIqiLBeKdqmcvZ064+L5wba 74hF6 X-Gm-Gg: AZuq6aKEe/SluhXSwPuJxVORUZY6RIc8f4kOrCFNF4LreG9hZD5F3wrOZxrAN30zX6I uux+ZNI6oU0K8alOKol8Yw7QcxteYJ43uhpY+D/Q+IGQVot9Fwm2nk3OswLPbpd97qGFrp5b+RF 0eTLv6+PiB/D+pZCpNPflYGXkwc3DyQamFHwuCwKPOF6udu0+sZIY2S0rUwTDOkS47G7AbgXln8 DVTT++EcfAYAldSEybAAb2+wIDfAZrATlmOPzcVLQMGFsvgfAnVhUiDC+vBTuexDQD1fhhH0sc0 YD2CkfIivDbByoFOA5HL4QksNMysxSY7q8KBtjznS8K6sAFMjWIN1qvxK2Qn5AICDPs6XBiEmEj Czp3LwZwleGZ/TQfRtkeZv8oP9vZx8KBDWwzkBLR2Wu5gbhgB+61ICyPWaAniJkJUuhe8Msq8Eq Eyy1EBtp4M+r1wE/d7f86z51/aaBfMKUL6oH6kItQRLswf7rvAUwrhTtrltvFuo7IBHZzFGBAf X-Received: by 2002:a05:600c:4684:b0:477:63b5:7148 with SMTP id 5b1f17b1804b1-4805cd40fc4mr89474625e9.6.1769450034271; Mon, 26 Jan 2026 09:53:54 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 07/16] x86/cpu: Call the vendor early_init() hook in early_cpu_init() Date: Mon, 26 Jan 2026 17:53:36 +0000 Message-Id: <20260126175345.2078371-8-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450068510158500 ... which is in practice much earlier on boot. Currently, beyond basic vendor family and model information, the Intel hook needs the SELF_SNOOP CPUID bit which is collected by early_cpu_init() alrea= dy. The AMD hook needs CPUID_USER_DIS, so the collection of leaf e21a needs to move too. (identify_cpu() has a second collection of this leaf, which remains.) In order to facilitate this, have early_cpu_init() calculate c->extended_cpuid_level in the usual way. No practical change. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/common.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 39e64f3a5f88..d70f9cf87dc8 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -413,8 +413,12 @@ void __init early_cpu_init(bool verbose) } =20 eax =3D cpuid_eax(0x80000000); - if ((eax >> 16) =3D=3D 0x8000 && eax >=3D 0x80000008) { - ebx =3D eax >=3D 0x8000001f ? cpuid_ebx(0x8000001f) : 0; + if ((eax >> 16) =3D=3D 0x8000) + c->extended_cpuid_level =3D eax; + + if (c->extended_cpuid_level >=3D 0x80000008) { + ebx =3D c->extended_cpuid_level >=3D 0x8000001f + ? cpuid_ebx(0x8000001f) : 0; eax =3D cpuid_eax(0x80000008); =20 paddr_bits =3D eax & 0xff; @@ -433,6 +437,19 @@ void __init early_cpu_init(bool verbose) paddr_bits -=3D (ebx >> 6) & 0x3f; } =20 + if (c->extended_cpuid_level >=3D 0x80000021) + c->x86_capability[FEATURESET_e21a] =3D cpuid_eax(0x80000021); + + /* + * Abuse 'verbose' to signal the first pass thought this function. + * + * Besides basic vendor, family and model information, the hooks need + * certain words of x86_capability[] already scanned, as they may take + * action to cause features to reappear. + */ + if (verbose && actual_cpu.c_early_init) + actual_cpu.c_early_init(); + if (!(c->x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON))) park_offline_cpus =3D opt_mce; =20 @@ -485,10 +502,6 @@ void identify_cpu(struct cpuinfo_x86 *c) c->x86_clflush_size =3D ((ebx >> 8) & 0xff) * 8; c->phys_proc_id =3D c->apicid; =20 - /* - * Early init of Self Snoop support requires 0x1.edx, while there also - * set 0x1.ecx as the value is in context. - */ c->x86_capability[FEATURESET_1c] =3D ecx; c->x86_capability[FEATURESET_1d] =3D edx; =20 @@ -496,16 +509,6 @@ void identify_cpu(struct cpuinfo_x86 *c) if ((eax >> 16) =3D=3D 0x8000) c->extended_cpuid_level =3D eax; =20 - /* - * These AMD-defined flags are out of place, but we need - * them early for the CPUID faulting probe code - */ - if (c->extended_cpuid_level >=3D 0x80000021) - c->x86_capability[FEATURESET_e21a] =3D cpuid_eax(0x80000021); - - if (c =3D=3D &boot_cpu_data && actual_cpu.c_early_init) - alternative_vcall(actual_cpu.c_early_init); - /* AMD-defined flags: level 0x80000001 */ if (c->extended_cpuid_level >=3D 0x80000001) cpuid(0x80000001, &tmp, &tmp, --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450068; cv=none; d=zohomail.com; s=zohoarc; b=FoXI6RGPLA6qXVajCTrU/Dh3m3akxWzq+jE/MzgaW3Sp6imPlU3MhBjBX80mG1Hh7+/tLyUwUG99mF9bnDsXKV/cfOvka3qavGin5NCW0WjHC7Of70PBjI52ulySHl0h1B9eTSRMBbAGqFGpFjz2Ye9hmXLuVXqtj6wcop9pEfM= ARC-Message-Signature: i=1; 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Smith" Subject: [PATCH 08/16] xen/sysctl: Drop XEN_SYSCTL_get_cpu_levelling_caps Date: Mon, 26 Jan 2026 17:53:37 +0000 Message-Id: <20260126175345.2078371-9-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450068633158501 This hypercall is an addition of mine from commit 67528a3f0649 ("x86/cpu: Sysctl and common infrastructure for levelling context switching", 2016), b= ut it never got wired into any toolstacks. In the meantime, how we handle CPU= ID for guests has evolved substantially. In order to reuse the AMD levelling infrasturcture for boot time quirks, levelling_caps is going to have to change. While it's probably safe to exp= ose this difference, it's safer still to make it an internal detail. When re-plummbing the LCAP_* constants, turn them all into single bits. Signed-off-by: Andrew Cooper Acked-by: Daniel P. Smith Reviewed-by: Jan Beulich # hypervisor & ~xsm --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie CC: Oleksii Kurochko CC: Daniel P. Smith --- CHANGELOG.md | 2 ++ tools/flask/policy/modules/dom0.te | 1 - tools/include/xenguest.h | 1 - tools/libs/guest/xg_cpuid_x86.c | 14 -------------- xen/arch/x86/include/asm/cpuid.h | 15 ++++++--------- xen/arch/x86/sysctl.c | 6 ------ xen/include/public/sysctl.h | 22 +--------------------- xen/xsm/flask/hooks.c | 4 ---- xen/xsm/flask/policy/access_vectors | 2 -- 9 files changed, 9 insertions(+), 58 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 18f3d10f20d2..425118bc9ae9 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,6 +19,8 @@ The format is based on [Keep a Changelog](https://keepach= angelog.com/en/1.0.0/) - The cpuid_mask_* command line options for legacy CPUs. These were deprecated in Xen 4.7 and noted not to work correctly with AMD CPUs f= rom 2011 onwards, nor work at all with Intel CPUs from 2012. + - The SYSCTL_get_cpu_levelling_caps sysctl. This is not known to have = been + used by any toolstack. - Xenoprofile support. Oprofile themselves removed support for Xen in = 2014 prior to the version 1.0 release, and there has been no development s= ince before then in Xen. diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/module= s/dom0.te index d30edf8be1fb..aae69041a966 100644 --- a/tools/flask/policy/modules/dom0.te +++ b/tools/flask/policy/modules/dom0.te @@ -43,7 +43,6 @@ allow dom0_t xen_t:xen2 { psr_alloc pmu_ctrl get_symbol - get_cpu_levelling_caps get_cpu_featureset livepatch_op coverage_op diff --git a/tools/include/xenguest.h b/tools/include/xenguest.h index 7c3b8b098352..2a277cb7cd61 100644 --- a/tools/include/xenguest.h +++ b/tools/include/xenguest.h @@ -822,7 +822,6 @@ int xc_cpu_policy_update_msrs(xc_interface *xch, xc_cpu= _policy_t *policy, bool xc_cpu_policy_is_compatible(xc_interface *xch, xc_cpu_policy_t *host, xc_cpu_policy_t *guest); =20 -int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps); int xc_get_cpu_featureset(xc_interface *xch, uint32_t index, uint32_t *nr_features, uint32_t *featureset); =20 diff --git a/tools/libs/guest/xg_cpuid_x86.c b/tools/libs/guest/xg_cpuid_x8= 6.c index 263a9d4787b6..0db6d77cd801 100644 --- a/tools/libs/guest/xg_cpuid_x86.c +++ b/tools/libs/guest/xg_cpuid_x86.c @@ -36,20 +36,6 @@ enum { #define bitmaskof(idx) (1u << ((idx) & 31)) #define featureword_of(idx) ((idx) >> 5) =20 -int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps) -{ - struct xen_sysctl sysctl =3D {}; - int ret; - - sysctl.cmd =3D XEN_SYSCTL_get_cpu_levelling_caps; - ret =3D do_sysctl(xch, &sysctl); - - if ( !ret ) - *caps =3D sysctl.u.cpu_levelling_caps.caps; - - return ret; -} - int xc_get_cpu_featureset(xc_interface *xch, uint32_t index, uint32_t *nr_features, uint32_t *featureset) { diff --git a/xen/arch/x86/include/asm/cpuid.h b/xen/arch/x86/include/asm/cp= uid.h index f1b9e37a42ca..c7ee1d54bc7e 100644 --- a/xen/arch/x86/include/asm/cpuid.h +++ b/xen/arch/x86/include/asm/cpuid.h @@ -15,15 +15,12 @@ extern const uint32_t known_features[FSCAPINTS]; * Expected levelling capabilities (given cpuid vendor/family information), * and levelling capabilities actually available (given MSR probing). */ -#define LCAP_faulting XEN_SYSCTL_CPU_LEVELCAP_faulting -#define LCAP_1cd (XEN_SYSCTL_CPU_LEVELCAP_ecx | \ - XEN_SYSCTL_CPU_LEVELCAP_edx) -#define LCAP_e1cd (XEN_SYSCTL_CPU_LEVELCAP_extd_ecx | \ - XEN_SYSCTL_CPU_LEVELCAP_extd_edx) -#define LCAP_Da1 XEN_SYSCTL_CPU_LEVELCAP_xsave_eax -#define LCAP_6c XEN_SYSCTL_CPU_LEVELCAP_thermal_ecx -#define LCAP_7ab0 (XEN_SYSCTL_CPU_LEVELCAP_l7s0_eax | \ - XEN_SYSCTL_CPU_LEVELCAP_l7s0_ebx) +#define LCAP_faulting (1U << 0) /* CPUID Faulting */ +#define LCAP_1cd (1U << 1) /* 0x00000001.ecx/edx */ +#define LCAP_e1cd (1U << 2) /* 0x80000001.ecx/edx */ +#define LCAP_Da1 (1U << 3) /* 0x0000000D:1.eax */ +#define LCAP_6c (1U << 4) /* 0x00000006.ecx */ +#define LCAP_7ab0 (1U << 5) /* 0x00000007:0.eax/ebx */ extern unsigned int expected_levelling_cap, levelling_caps; =20 struct cpuidmasks diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c index 1b04947516bb..0fbbdd8b280d 100644 --- a/xen/arch/x86/sysctl.c +++ b/xen/arch/x86/sysctl.c @@ -289,12 +289,6 @@ long arch_do_sysctl( break; } =20 - case XEN_SYSCTL_get_cpu_levelling_caps: - sysctl->u.cpu_levelling_caps.caps =3D levelling_caps; - if ( __copy_field_to_guest(u_sysctl, sysctl, u.cpu_levelling_caps.= caps) ) - ret =3D -EFAULT; - break; - case XEN_SYSCTL_get_cpu_featureset: { static const struct cpu_policy *const policy_table[6] =3D { diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h index 66c9b65465cc..6b4ec5f7f765 100644 --- a/xen/include/public/sysctl.h +++ b/xen/include/public/sysctl.h @@ -932,25 +932,6 @@ struct xen_sysctl_psr_alloc { } u; }; =20 -/* - * XEN_SYSCTL_get_cpu_levelling_caps (x86 specific) - * - * Return hardware capabilities concerning masking or faulting of the cpuid - * instruction for PV guests. - */ -struct xen_sysctl_cpu_levelling_caps { -#define XEN_SYSCTL_CPU_LEVELCAP_faulting (1UL << 0) /* CPUID faulting = */ -#define XEN_SYSCTL_CPU_LEVELCAP_ecx (1UL << 1) /* 0x00000001.ecx = */ -#define XEN_SYSCTL_CPU_LEVELCAP_edx (1UL << 2) /* 0x00000001.edx = */ -#define XEN_SYSCTL_CPU_LEVELCAP_extd_ecx (1UL << 3) /* 0x80000001.ecx = */ -#define XEN_SYSCTL_CPU_LEVELCAP_extd_edx (1UL << 4) /* 0x80000001.edx = */ -#define XEN_SYSCTL_CPU_LEVELCAP_xsave_eax (1UL << 5) /* 0x0000000D:1.ea= x */ -#define XEN_SYSCTL_CPU_LEVELCAP_thermal_ecx (1UL << 6) /* 0x00000006.ecx = */ -#define XEN_SYSCTL_CPU_LEVELCAP_l7s0_eax (1UL << 7) /* 0x00000007:0.ea= x */ -#define XEN_SYSCTL_CPU_LEVELCAP_l7s0_ebx (1UL << 8) /* 0x00000007:0.eb= x */ - uint32_t caps; -}; - /* * XEN_SYSCTL_get_cpu_featureset (x86 specific) * @@ -1270,7 +1251,7 @@ struct xen_sysctl { #define XEN_SYSCTL_pcitopoinfo 22 #define XEN_SYSCTL_psr_alloc 23 /* #define XEN_SYSCTL_tmem_op 24 */ -#define XEN_SYSCTL_get_cpu_levelling_caps 25 +/* #define XEN_SYSCTL_get_cpu_levelling_caps 25 */ #define XEN_SYSCTL_get_cpu_featureset 26 #define XEN_SYSCTL_livepatch_op 27 /* #define XEN_SYSCTL_set_parameter 28 */ @@ -1300,7 +1281,6 @@ struct xen_sysctl { struct xen_sysctl_coverage_op coverage_op; struct xen_sysctl_psr_cmt_op psr_cmt_op; struct xen_sysctl_psr_alloc psr_alloc; - struct xen_sysctl_cpu_levelling_caps cpu_levelling_caps; struct xen_sysctl_cpu_featureset cpu_featureset; struct xen_sysctl_livepatch_op livepatch; #if defined(__i386__) || defined(__x86_64__) diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c index b250b2706535..28522dcbd271 100644 --- a/xen/xsm/flask/hooks.c +++ b/xen/xsm/flask/hooks.c @@ -884,10 +884,6 @@ static int cf_check flask_sysctl(int cmd) return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2, XEN2__PSR_ALLOC, NULL); =20 - case XEN_SYSCTL_get_cpu_levelling_caps: - return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2, - XEN2__GET_CPU_LEVELLING_CAPS, NULL); - case XEN_SYSCTL_get_cpu_featureset: return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2, XEN2__GET_CPU_FEATURESET, NULL); diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/acc= ess_vectors index ce907d50a45e..bbb9c117ec4a 100644 --- a/xen/xsm/flask/policy/access_vectors +++ b/xen/xsm/flask/policy/access_vectors @@ -87,8 +87,6 @@ class xen2 pmu_ctrl # PMU use (domains, including unprivileged ones, will be using this operat= ion) pmu_use -# XEN_SYSCTL_get_cpu_levelling_caps - get_cpu_levelling_caps # XEN_SYSCTL_get_cpu_featureset get_cpu_featureset # XEN_SYSCTL_livepatch_op --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; 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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:55 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fca4bec7-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450036; x=1770054836; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RD+FwnuL4ppUz8uo27Is5O2Ip6Cil9yXt9VnPw3KiRc=; b=h7SiuRzmtZ9Vs7j62Bb6eY7ASK6ZT4/X1HAL7DNQrjbf7hWfeGATHcNHfIrVNUXzjr pysAKjj+SuyQu6K6sMM3/Ec3ZCTEgjeouWMa8uslrFS2KeCLxNfPx8vDZdU86MUp0OBH wQ8XuW0wbk7t0eLf/riqTHzZ/PB7Vb7wcWXMg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450036; x=1770054836; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=RD+FwnuL4ppUz8uo27Is5O2Ip6Cil9yXt9VnPw3KiRc=; b=CwJZ1UQ+IOdC7/8eA1I/vjMLwY2PactN9dQgbbcnbiYU2ytzXp50NUh/gBmEjqTfna 0enRpuqLBKLu9+VtHzYQgCZvagqdEOuR2ztAe9nVEY0BCBqWCVGtuYHvxMpbI8icLdgW PXy9MguL7Jlzyg8Gjn+7a9d2vKSeh+R6rZ23Fqk1hX246go/71r6WY6XsPJdqStDG6NC y9dXIdLbLo9VJxEQ6OozUyAHK4KG8nFS8zRFQchcVBKgE+D908MiwlYrMaf2jAYeZPii NP811SS2Q6WeI8CeSyGtvSj4Ye/0658D8o7c/lNVfhzasoT8JGKbFQp/RSjgEnvdYLov +7bg== X-Gm-Message-State: AOJu0YzkiWi2q7X7Ng9kjeRW9BVnEcwpQBbm6vdUi3uJ3SHsZSeA+tYW VV8yKvTe5mSU61kqVVQG2YaZ9N39xhTirHIovqC/Swk5qeXZmC5oGTlZCLe53+ZaQmABbmxcFzL bI8A0 X-Gm-Gg: AZuq6aLzFdCcbAP85XxgZfBZMZhHuGOuj7/4k/EqxljhiTutOHBmobJMsl2o7VzTSwm sNaSwQuPf+dbnwYwAEV7BONXQFbk/GSPmmbLjArfEXWwe6j3MPQNjDACzIc8GMudN+//Y4+xSvX XdrmfMyUFYT6HCEqT7zr6MRZ0olwT2x/4VWxcz8kjaDvW/kkbOn2OQpJQkLLLi8WXHsaH5bWwt2 tAV3Wckv8HDvPZIq3CJLQWMVN8t+nrKTteHfgYjaC5TBvm8SdkCGardPc+Mr6m4V45wWNUL3GtS GGBm8YdS3Gx00sylXh7tYBg67Ul7+jVlo5MSEQb1DD1jn31EYVuwz8EfGH2ZpZD8Mh1GwkvmB2b YyfKUybEd0gslR0XIlVYfhGG75KoPR/lscCASQeCcy5i7XIPlsyx57N7gflQ3GFmflK33FwDEjs +KbARgCdrtP5EzmWuzm/whzSrrGF4FzM+yh9TK7mo5H7BWNXUZcpDg0vGKv9frDw== X-Received: by 2002:a05:600c:4fd6:b0:480:1d0b:2d15 with SMTP id 5b1f17b1804b1-4805cf63e02mr86010055e9.27.1769450035873; Mon, 26 Jan 2026 09:53:55 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 09/16] x86/intel: Always check MSR_MISC_ENABLE on all CPUs Date: Mon, 26 Jan 2026 17:53:38 +0000 Message-Id: <20260126175345.2078371-10-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450081440154100 Currently, the BSP only leaves instructions for the APs to adjust MSR_MISC_ENABLE if the BSP is found to need adjustments. Particularly if XD_DISABLE is needed on an AP but not the BSP, the system will triple fault with no information provided to the user. Rework the BSP and trampoline logic to always read MISC_ENABLE, and clear CPUID_LIMIT and XD_DISABLE if either are set. Repurpose intel_unlock_cpuid_leaves() to be intel_check_misc_enable() and m= ake it static in common.c. Replace trampoline_misc_enable_off with the smaller trampoline_check_misc_enable. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie This temporarily removes the printk() noting the reactivation of XD because the earlier BSP code has already done it, but that logic is about to be removed. --- xen/arch/x86/boot/head.S | 1 - xen/arch/x86/boot/trampoline.S | 29 ++++++++++-------- xen/arch/x86/boot/wakeup.S | 27 ++++++++++------- xen/arch/x86/cpu/common.c | 43 ++++++++++++++++++++++++++- xen/arch/x86/cpu/cpu.h | 2 -- xen/arch/x86/cpu/intel.c | 19 ------------ xen/arch/x86/include/asm/trampoline.h | 7 +++-- 7 files changed, 79 insertions(+), 49 deletions(-) diff --git a/xen/arch/x86/boot/head.S b/xen/arch/x86/boot/head.S index 77bb7a9e2191..4022f8639478 100644 --- a/xen/arch/x86/boot/head.S +++ b/xen/arch/x86/boot/head.S @@ -582,7 +582,6 @@ trampoline_setup: btr $2, %edx jnc .Lno_nx wrmsr - orb $MSR_IA32_MISC_ENABLE_XD_DISABLE >> 32, 4 + sym_esi(trampo= line_misc_enable_off) =20 /* Check again for NX */ mov $0x80000001, %eax diff --git a/xen/arch/x86/boot/trampoline.S b/xen/arch/x86/boot/trampoline.S index a92e399fbe0e..2b4552096fd7 100644 --- a/xen/arch/x86/boot/trampoline.S +++ b/xen/arch/x86/boot/trampoline.S @@ -77,17 +77,22 @@ trampoline_protmode_entry: mov %eax,%cr3 =20 /* Adjust IA32_MISC_ENABLE if needed (for NX enabling below). */ - mov bootsym_rel(trampoline_misc_enable_off,4,%esi) - mov bootsym_rel(trampoline_misc_enable_off+4,4,%edi) - mov %esi,%eax - or %edi,%eax - jz 1f + cmpb $1, bootsym_rel(trampoline_check_misc_enable, 5) + jne 1f + mov $MSR_IA32_MISC_ENABLE,%ecx rdmsr - not %esi - not %edi - and %esi,%eax - and %edi,%edx + + xor %edi, %edi + btr $22 /* ilog2(MSR_IA32_MISC_ENABLE_LIMIT_CPUID) */, %eax + adc %edi, %edi + + btr $34 /* ilog2(MSR_IA32_MISC_ENABLE_XD_DISABLE) */ - 32, %edx + adc %edi, %edi + + /* No bits need clearing? Nothing to do */ + jz 1f + wrmsr 1: /* Set up PAT before enabling paging. */ @@ -141,9 +146,6 @@ gdt_48: .long trampoline_gdt + BOOT_PSEUDORM_DS + 2 - . .popsection =20 -GLOBAL(trampoline_misc_enable_off) - .quad 0 - /* EFER OR-mask for boot paths. SCE conditional on PV support, NX added w= hen available. */ GLOBAL(trampoline_efer) .long EFER_LME | (EFER_SCE * IS_ENABLED(CONFIG_PV)) | \ @@ -155,6 +157,9 @@ GLOBAL(trampoline_xen_phys_start) GLOBAL(trampoline_cpu_started) .byte 0 =20 +GLOBAL(trampoline_check_misc_enable) + .byte 0 + LABEL(trampoline_perm_end, 0) =20 /* From here on early boot only. */ diff --git a/xen/arch/x86/boot/wakeup.S b/xen/arch/x86/boot/wakeup.S index 654e97005ff4..aced8153bafa 100644 --- a/xen/arch/x86/boot/wakeup.S +++ b/xen/arch/x86/boot/wakeup.S @@ -126,18 +126,23 @@ wakeup_32: add bootsym_rel(trampoline_xen_phys_start,4,%eax) mov %eax,%cr3 =20 - /* Reapply IA32_MISC_ENABLE modifications from early_init_intel().= */ - mov bootsym_rel(trampoline_misc_enable_off, 4, %esi) - mov bootsym_rel(trampoline_misc_enable_off + 4, 4, %edi) - mov %esi, %eax - or %edi, %eax - jz 1f - mov $MSR_IA32_MISC_ENABLE, %ecx + /* Adjust IA32_MISC_ENABLE if needed (for NX enabling below). */ + cmpb $1, bootsym_rel(trampoline_check_misc_enable, 5) + jne 1f + + mov $MSR_IA32_MISC_ENABLE,%ecx rdmsr - not %esi - not %edi - and %esi, %eax - and %edi, %edx + + xor %edi, %edi + btr $22 /* ilog2(MSR_IA32_MISC_ENABLE_LIMIT_CPUID) */, %eax + adc %edi, %edi + + btr $34 /* ilog2(MSR_IA32_MISC_ENABLE_XD_DISABLE) */ - 32, %edx + adc %edi, %edi + + /* No bits need clearing? Nothing to do */ + jz 1f + wrmsr 1: /* Set up PAT before enabling paging. */ diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index d70f9cf87dc8..0249bb4bf2dc 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 #include @@ -307,6 +308,46 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int inde= x_msb) return _phys_pkg_id(get_apic_id(), index_msb); } =20 +/* + * Disable restrictions in MSR_MISC_ENABLE. These are often available as + * firmware settings for backwards compatibility. Called prior to cpuid_l= evel + * being acted upon, as it may need unlimiting. + */ +static void __init intel_check_misc_enable(struct cpuinfo_x86 *c) +{ + uint64_t misc_enable, disable =3D (MSR_IA32_MISC_ENABLE_LIMIT_CPUID | + MSR_IA32_MISC_ENABLE_XD_DISABLE); + + /* Instruct the trampoline to perform the same check too. */ + bootsym(trampoline_check_misc_enable) =3D true; + + misc_enable =3D rdmsr(MSR_IA32_MISC_ENABLE); + + if ( (misc_enable & disable) =3D=3D 0 ) + return; /* Nothing to do */ + + wrmsr(MSR_IA32_MISC_ENABLE, misc_enable & ~disable); + + /* + * When the P4 Nocona introduced the Structured Cache information, it = was + * discovered that WinNT crashed on encountering a CPUID Leaf 4. Intel + * worked around this by introducing an ability to limit the maximum + * reported leaf to 2 (PSN, leaf 3 had already been removed by this ti= me). + */ + if ( misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID ) + { + c->cpuid_level =3D cpuid_eax(0); + printk(XENLOG_INFO "revised cpuid level: %u\n", c->cpuid_level); + } + + /* + * When Intel added XD support originally, it was recommended to be of= f by + * default because of stability problems in WinXP SP2. + */ + if ( misc_enable & MSR_IA32_MISC_ENABLE_XD_DISABLE ) + printk(XENLOG_INFO "re-enabled NX (Execute Disable) protection\n"); +} + /* Do minimum CPU detection early. Fields really needed: vendor, cpuid_level, family, model, mask, cache a= lignment. The others are not touched to avoid unwanted side effects. @@ -327,7 +368,7 @@ void __init early_cpu_init(bool verbose) =20 c->x86_vendor =3D x86_cpuid_lookup_vendor(ebx, ecx, edx); switch (c->x86_vendor) { - case X86_VENDOR_INTEL: intel_unlock_cpuid_leaves(c); + case X86_VENDOR_INTEL: intel_check_misc_enable(c); actual_cpu =3D intel_cpu_dev; break; case X86_VENDOR_AMD: actual_cpu =3D amd_cpu_dev; break; case X86_VENDOR_CENTAUR: actual_cpu =3D centaur_cpu_dev; break; diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h index 0fc6370edb13..d2d37d1d5eec 100644 --- a/xen/arch/x86/cpu/cpu.h +++ b/xen/arch/x86/cpu/cpu.h @@ -27,6 +27,4 @@ void amd_init_ssbd(const struct cpuinfo_x86 *c); void amd_init_spectral_chicken(void); void detect_zen2_null_seg_behaviour(void); =20 -void intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c); - #endif /* X86_CPU_H */ diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 2aeeb2f5bf55..b1dd06d92f60 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -309,22 +309,6 @@ static void __init intel_init_levelling(void) ctxt_switch_masking =3D intel_ctxt_switch_masking; } =20 -/* Unmask CPUID levels if masked. */ -void __init intel_unlock_cpuid_leaves(struct cpuinfo_x86 *c) -{ - uint64_t misc_enable, disable; - - rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); - - disable =3D misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID; - if (disable) { - wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable & ~disable); - bootsym(trampoline_misc_enable_off) |=3D disable; - c->cpuid_level =3D cpuid_eax(0); - printk(KERN_INFO "revised cpuid level: %u\n", c->cpuid_level); - } -} - /* * Errata BA80, AAK120, AAM108, AAO67, BD59, AAY54: Rapid Core C3/C6 Trans= ition * May Cause Unpredictable System Behavior @@ -392,9 +376,6 @@ static void __init probe_mwait_errata(void) =20 static void __init cf_check early_init_intel(void) { - if ( bootsym(trampoline_misc_enable_off) & MSR_IA32_MISC_ENABLE_XD_DIS= ABLE ) - printk(KERN_INFO "re-enabled NX (Execute Disable) protection\n"); - check_memory_type_self_snoop_errata(); =20 /* diff --git a/xen/arch/x86/include/asm/trampoline.h b/xen/arch/x86/include/a= sm/trampoline.h index deed2679d9d5..893bbe54f325 100644 --- a/xen/arch/x86/include/asm/trampoline.h +++ b/xen/arch/x86/include/asm/trampoline.h @@ -153,10 +153,11 @@ extern uint8_t trampoline_cpu_started; extern uint32_t trampoline_efer; =20 /* - * When nonzero, clear the specified bits in MSR_MISC_ENABLE. This is - * necessary to clobber XD_DISABLE before trying to set MSR_EFER.NXE. + * Instruction from the BSP to APs that MSR_MISC_ENABLE is available and + * should be checked to remove limitations. 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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:56 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fd21385e-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450037; x=1770054837; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DXHoMP2m1S668fp9KXBejADon30ms3RX1/2RyOl2CwM=; b=WuQQ57ZEGI+gtoEiAaalhftBAy7Ivd9p3IShdzs65a0YwgV4vZwM939Fkw8IDDyDKx RZB6zbkUqc94dB1hcu77FZo0gwAvGLTB/i8QHCJzT/xtI4I4Ni6KgKY2YDHCGZgzwSC2 EkAjB8jFEu4dBHzgAzxYwmh0/n8jvbYr685o4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450037; x=1770054837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=DXHoMP2m1S668fp9KXBejADon30ms3RX1/2RyOl2CwM=; b=ZVekbiz02nGMJca2TRH2nUfX+YKVDe227yVCzdPORt4tCEgYJh/06LI9yO0HtWsGkr tgLqe7nWcDBWUxM+X1b6YCzI+8Qd4b7w1cGJ5j/bwYQNzMOgwcYQkZV6DHfqWYeV52ng 869jsfVaB5ekASlUxutib6Lo1hh+lywKFEYkzDRPpQqPmuc0cePsY3w/TOiXUmnT8twe dzwRUP9kTAZP9xdAVjaRcTSr/jwghZEAa7AUCdp1gl+NHr1pL64qRsmlhJSbl1KZcJC6 Om5VhtoRvbRzS4I4A/RMA/w5BcPZhs90IoAkhhZ5nQbv1TxXkKN8mCRRhabveUX8imTk UsFg== X-Gm-Message-State: AOJu0Yy0DuIZhwfurOMA1NDSzK5bpXwrOgJdBfUSgf1BO74M2YUugnwU cRyUyE9O7/8xuzUHEHAAXW+MC1DXnzWsN0xsoz2PnBdj4MD4hUk1MaO1F/gJdL7dBPr/6Z7aWjw GJ+xG X-Gm-Gg: AZuq6aLIvFLlUER7duZOKDm5woiEijXcWUEYCeYlftby026ryEg6W+jpMo9Ux2G90+k ZmT6lrRFVaXoe8rv3n6IRViq1N9NGu8QwUa1ir0z0B3KuDgMNfE5zwS2yc8WoCAfSi5k9fjK6IM GRm/Aory82vL1lIGR3Mt+2lkT2A6Z9x4xP+dlQnFvzK7JfhH/GI7f1rPn2KRje587+trjkIVHjh G0u0jlbkbH14jemr3z7vmjTpTzEs1bguXNnoUaMUBGajR3zUUVPo2n3YSYy5Mrh8U7FnHUghlfo anOUt8n07rgjpc45CY6QsL5ptKA5TPTX73MOXoOBXoJ8BxnzD5XV3bdMEO1cVtbGyfT4vFLuHxR 6Kw7nPQRAzV6fd9UiZhAWHYCv0Bt2rHAZuZ1C4hyt9tc+WjJF0skZ37IMLGWtsXzq8FZ85nrQkK 3rrEbb1QC0CflF/h/Pn+87hZQujZ6XQcYN5pGXizX822Tv8RT4TN2pHPuHtmDi7A== X-Received: by 2002:a05:600c:c4a5:b0:477:9cdb:e32e with SMTP id 5b1f17b1804b1-4805ce4e578mr91498405e9.9.1769450036624; Mon, 26 Jan 2026 09:53:56 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 10/16] x86/amd: Always probe and configure the masking MSRs Date: Mon, 26 Jan 2026 17:53:39 +0000 Message-Id: <20260126175345.2078371-11-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450068416158500 This allows the infrastructure to reused for system-wide quirk/errata adjustments. Replace the call to ctxt_switch_levelling() with amd_ctxt_switch_masking() instead. The CPUID Faulting aspect is not interesting at this point in boo= t, and we want to explicitly propagate the masking MSR defaults into APs. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/amd.c | 15 +++++++++++---- xen/arch/x86/cpu/cpu.h | 1 + xen/arch/x86/cpu/hygon.c | 2 +- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 36fea2e0a299..e8daf7415bb0 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -162,7 +162,7 @@ static void __init noinline probe_masking_msrs(void) * parameter of NULL is used to context switch to the default host state (= by * the cpu bringup-code, crash path, etc). */ -static void cf_check amd_ctxt_switch_masking(const struct vcpu *next) +void cf_check amd_ctxt_switch_masking(const struct vcpu *next) { struct cpuidmasks *these_masks =3D &this_cpu(cpuidmasks); const struct domain *nextd =3D next ? next->domain : NULL; @@ -242,9 +242,12 @@ static void __init amd_init_levelling(void) boot_cpu_has(X86_FEATURE_CPUID_USER_DIS)) { expected_levelling_cap |=3D LCAP_faulting; levelling_caps |=3D LCAP_faulting; - return; } =20 + /* + * Always probe for the MSRs too. We reuse the infrastruture for + * quirks/errata/etc during boot. + */ probe_masking_msrs(); =20 if ((levelling_caps & LCAP_1cd) =3D=3D LCAP_1cd) { @@ -299,7 +302,7 @@ static void __init amd_init_levelling(void) (uint32_t)cpuidmask_defaults._6c); } =20 - if (levelling_caps) + if (levelling_caps && !(levelling_caps & LCAP_faulting)) ctxt_switch_masking =3D amd_ctxt_switch_masking; } =20 @@ -1015,7 +1018,11 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) u32 l, h; uint64_t value; =20 - ctxt_switch_levelling(NULL); + /* + * Reuse amd_ctxt_switch_masking() explicitly. This propagates + * quirk/errata adjustments made duing early_init_amd() into the APs. + */ + amd_ctxt_switch_masking(NULL); =20 amd_init_de_cfg(c); =20 diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h index d2d37d1d5eec..cd93e51755af 100644 --- a/xen/arch/x86/cpu/cpu.h +++ b/xen/arch/x86/cpu/cpu.h @@ -20,6 +20,7 @@ extern void detect_ht(struct cpuinfo_x86 *c); extern bool detect_extended_topology(struct cpuinfo_x86 *c); =20 void cf_check early_init_amd(void); +void cf_check amd_ctxt_switch_masking(const struct vcpu *next); void amd_log_freq(const struct cpuinfo_x86 *c); void amd_init_de_cfg(const struct cpuinfo_x86 *c); void amd_init_lfence_dispatch(void); diff --git a/xen/arch/x86/cpu/hygon.c b/xen/arch/x86/cpu/hygon.c index bb1624882499..3a04efef5028 100644 --- a/xen/arch/x86/cpu/hygon.c +++ b/xen/arch/x86/cpu/hygon.c @@ -32,7 +32,7 @@ static void cf_check init_hygon(struct cpuinfo_x86 *c) { unsigned long long value; =20 - ctxt_switch_levelling(NULL); + amd_ctxt_switch_masking(NULL); =20 amd_init_de_cfg(c); =20 --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450072; cv=none; d=zohomail.com; s=zohoarc; b=hCFw59itM4a/9NML6dvrUqZNoqarEB4WAxZaaGixEnYIVSEIbAoI4y0zlOCWn6mmgy3iExw1HSJ7DX5mqNEbLXtjJHYBzFLuzopx3vCoQ3xwZUixcdQtyTTroRV10g2D/0QlfZvnd6sUL42j4xpgS7WuTzr4CZHBwt5gapgA6Fc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769450072; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Try1cZQOOfQY5RdnyC25WW3N+d8l3jQHbsgtA/sxQ94=; b=FA0/FIvl2cE6OUCyYRPcoU2/bZJdAOTBZERzNCXnl2+GWvx80pAbs1JKr3G70ooZVjrxXcfjiH7vfWBUSbDFpjsd0B6q9FxInGZl9gHoduUMWX0bRBGgT48OF29D2+qFUbfYuV6EGe/bUI+Wd1vDpHkSReKZ+NU7+uhtTKXIKow= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769450072040513.8484834009445; Mon, 26 Jan 2026 09:54:32 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1213838.1524361 (Exim 4.92) (envelope-from ) id 1vkQmn-0006SW-M3; Mon, 26 Jan 2026 17:54:01 +0000 Received: by outflank-mailman (output) from mailman id 1213838.1524361; Mon, 26 Jan 2026 17:54:01 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmn-0006RK-Aw; Mon, 26 Jan 2026 17:54:01 +0000 Received: by outflank-mailman (input) for mailman id 1213838; Mon, 26 Jan 2026 17:53:59 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQml-0004HW-Je for xen-devel@lists.xenproject.org; Mon, 26 Jan 2026 17:53:59 +0000 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [2a00:1450:4864:20::32c]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fd1c4f0e-fadf-11f0-b15f-2bf370ae4941; Mon, 26 Jan 2026 18:53:58 +0100 (CET) Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-47f5c2283b6so36405185e9.1 for ; Mon, 26 Jan 2026 09:53:57 -0800 (PST) Received: from localhost.localdomain (host-92-26-102-188.as13285.net. [92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:56 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fd1c4f0e-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450037; x=1770054837; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Try1cZQOOfQY5RdnyC25WW3N+d8l3jQHbsgtA/sxQ94=; b=HVQtNFLMzT3MI1HTrdXNhNxM93FlCY3vWD4OHRGyCzMPCOYLu+cNMZ9P5ZjMPS5pPx 9ALF4sC9wDw73TNafQkX8tIIrQlfMfsJ2tBR2qVl9PlPXYwQXl+Bp76BsuGt/W3bqpNq 3zKSw9xPArmfRDI2LYV0acQcZRtpf/3G8RUjg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450037; x=1770054837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Try1cZQOOfQY5RdnyC25WW3N+d8l3jQHbsgtA/sxQ94=; b=GFkc8i4eGlP+oCd+yYIGnTxABKTO7CKnAqJFcK9sko5Z+XxUXoBuy0K2uJrw9+Bc2w LxQmT01k+rzXlFj+DM3xIITXEyRwRy2Z2aVy7xv1rUaBChtIwFNwJUa6coXoXXf46A+J uZpKa/wTvH/+GbDA7O2mABdmV+imuE18xMwLHKbKetrilHEmCIOtvNcOXV6DxEs43TUg 5UUsC3c4VPOqeOsF44+k4ANAFX5tpx//e91vHWgE0l6Mm1FUsA+qQ/C8mq86N5yl5AdL U8zmoz+gj111sz/yfpKpDAqFyqGdi9YtAEo5zWsYIchwuvc3SZC8yDjyIt5lNMfYEUGE 2N5g== X-Gm-Message-State: AOJu0YwaMqzyQ1K1uYlBevcjeJpM+JgwHcQpOVmxKpqWZzvJoGMO0klj ghiQM4AdcoEz4sV2X/03BARN4qZ9wLLMKz+g8hdPeXwO0+p88dMXXMpYdupF9XEL5BCT6y7AwVB RCVW9 X-Gm-Gg: AZuq6aL25VX8sRYzQSuvtOCrR6bsdqqGC8+5ms5Z3GF+f5QCzkh65sN4mAbNU/qtNQj J+R4bUMB3mXXbhoZq7ele5129HZc95xXn2Om9gGINrI3xnKW2M4I9Yk0UMhsJq0QwB7gcZ+fsCl 5kN8i9JqFUzi7WvsRE+oErOghd1ygNvOnQiv4Nc5DuD9VgGGGOl22fygPKhwnTXuLWAU8NUKeYM ndnvL4kVnJ3rziyL8QcrDTKbatqRtRJL4i94dvJXacfakYYgt1xm5hRmE686VuFfVj55Ou1L042 RZG9peTrV73UD+1PNAmX3zss2ywNg9YCklneYOVDuHUP0qCB3giBpAD67ADY8x36w/3LFNFY8un GM+nA/O9UAnoggWkaypowhxkPnjsJ6RmoZ5fZE3SC7ahOIjejBRjjsb0V/4Nf7OkqL8g9xRW7Jf tJhdoL/ZTS1YkFNPczURjRHC7LisLNRrAtJMZj6juutvYIoD/XAJHCF9OGTZ3fKA== X-Received: by 2002:a05:600c:c087:b0:477:6374:6347 with SMTP id 5b1f17b1804b1-4805d95d3e1mr64802295e9.22.1769450037164; Mon, 26 Jan 2026 09:53:57 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 11/16] x86/amd: Fix re-activation of TopoExt on Fam15h CPUs Date: Mon, 26 Jan 2026 17:53:40 +0000 Message-Id: <20260126175345.2078371-12-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450074073154100 init_amd() tries to re-activate TOPOEXT on certain systems, but only after amd_init_levelling() has calculated the levelling defaults, meaning that the re-activation will be lost on the next context switch. Move the logic into early_init_amd() so it takes effect before calculating = the levelling defaults. Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/amd.c | 40 ++++++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index e8daf7415bb0..a14a12fb1d60 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -620,9 +620,32 @@ void amd_process_freq(const struct cpuinfo_x86 *c, *low_mhz =3D amd_parse_freq(c->x86, lo); } =20 +static void amd_early_adjust_cpuid_extd(void) +{ + struct cpuinfo_x86 *c =3D &boot_cpu_data; + uint64_t val; + + /* Re-enable TopologyExtensions if switched off by BIOS */ + if ( c->family =3D=3D 0x15 && c->model >=3D 0x10 && c->model <=3D 0x1f= && + !boot_cpu_has(X86_FEATURE_TOPOEXT) && + !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, &val) ) + { + val |=3D 1ULL << 54; + wrmsr_safe(MSR_K8_EXT_FEATURE_MASK, val); + val =3D rdmsr(MSR_K8_EXT_FEATURE_MASK); + if ( val & (1ULL << 54) ) + { + __set_bit(X86_FEATURE_TOPOEXT, c->x86_capability); + printk(XENLOG_INFO "CPU: Re-enabling disabled Topology Extensi= ons Support\n"); + } + } +} + void __init cf_check early_init_amd(void) { - amd_init_levelling(); + amd_early_adjust_cpuid_extd(); + + amd_init_levelling(); /* Capture defaults after early CPUID adjustment= s */ } =20 void amd_log_freq(const struct cpuinfo_x86 *c) @@ -1145,21 +1168,6 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) } } =20 - /* re-enable TopologyExtensions if switched off by BIOS */ - if ((c->x86 =3D=3D 0x15) && - (c->x86_model >=3D 0x10) && (c->x86_model <=3D 0x1f) && - !cpu_has(c, X86_FEATURE_TOPOEXT) && - !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, &value)) { - value |=3D 1ULL << 54; - wrmsr_safe(MSR_K8_EXT_FEATURE_MASK, value); - rdmsrl(MSR_K8_EXT_FEATURE_MASK, value); - if (value & (1ULL << 54)) { - __set_bit(X86_FEATURE_TOPOEXT, c->x86_capability); - printk(KERN_INFO "CPU: Re-enabling disabled " - "Topology Extensions Support\n"); - } - } - /* * The way access filter has a performance penalty on some workloads. * Disable it on the affected CPUs. --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:57 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fdb13772-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450038; x=1770054838; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vQsr194qP7u179I9/onbBLntD3BMN8iVc8+MjUid8Kk=; b=UeTu1bgLfMuHVfScFR4BoTAufg0+dynixuDGwoqQ83Ch4D9sYSg/MXDQpHhG7DxjdR jIjia8oTgYzxiZSMHvgdW4XBJB9VfjcbcBeMLFfT+Oy5fCh9p0OQm+VY21KQqXsVhGeZ WQAcoBoBFXjK/QnNKBBQdBH6c32p5Ezasv0gY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450038; x=1770054838; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=vQsr194qP7u179I9/onbBLntD3BMN8iVc8+MjUid8Kk=; b=WuykrlqS3YFXsA/bh5ee92SLQRtA5ysvzs76bA7wzaf4W7yKFJsin9QCDePiUql6uL TaWulqY1+hrCoJyDT3HRnQoZ9PGRAOEaA610GUa0EZf9+Ro/dcD+BfHDf5F7oFkNEbef TDJdd8/ewpSJyDTpD/sDSdcN19DapXCGrRF1x/cNF+q0+6f1ez+OtP4vaMJ+8p3YgBOI gZ3zzFNyttvmdxH99+u1U2JsYkl/IzKsGwAS9vzelA3zu7zAValcjS4KEZN8HRcS8KXy e1K6ZvANIFfGIq+KG6hDl2aiEZ2nN7Tg0ti3djG4UJzpng7IVsADiqiF41LzAaZrkX02 XKgQ== X-Gm-Message-State: AOJu0Yyha93gNc1u1dNXohdZByIP5DrWNHyuaCwn3V+1/YxGZOP31QrV V1zwR9U8l+b27dtJXp8MRNa/XecQOhsiSqgK+4iZ/TU1BIpbEI9efpUlggOyt1FHgJzRAwAEUFl uGd5/ X-Gm-Gg: AZuq6aKSofk1fzTXpUSbTNSOm1u3Ddsk6BwztvWqd5r566YfsQnsLPuJwSKZ2XtKtyU Q5AsQobgOwgAy4jPJZhGSspgMKU+grteQtLEQwuHqGwVHEGsIRw+QBODrgmqhL3oLheDj8VEe4h qTh8/NY+gKebW2sHRyCkNWSniwp1Ij3bb3asylggb/zfiyk8I7cq9EkV7reVuUW869sd6bfLTNw qoj0HAySBnxBn3FnW8BZjOqB71YeGTDwznevIXjhZHvQtWWqrtRKRbuv2NbRvME+vyOLAOI1DZQ AAy1YIxRKRZ5JI7Y1nG/bfD2EjhrtlPZYjO5LrS33OqJYSyFAz53jG5d3YBISIQJShYqf+gZMXL 9DqcHU4QoKhgA9ezKRETOLnByxL2xoxEKGDzcO1jVczGIkkyiQ1FNU6WHzK40ro7U1SFSFInDx9 o4e4ZqBMXmhW0Kd/Z46skOtT9hE2qjNiPhvAWXkOXWrbUqS0YgvejiGPFEtIyJuq4whAnr0lTA X-Received: by 2002:a05:600c:528a:b0:480:4a8f:2d5c with SMTP id 5b1f17b1804b1-4805cf6c405mr81861005e9.29.1769450038094; Mon, 26 Jan 2026 09:53:58 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 12/16] x86/amd: Probe for NX support and re-activate if possible Date: Mon, 26 Jan 2026 17:53:41 +0000 Message-Id: <20260126175345.2078371-13-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450064201154100 An AMD Ryzen system has been found with a firmware option to disable NX. L= ike we do on Intel systems, try to detect and undo this stupidity. Link: https://xcp-ng.org/forum/post/80714 Signed-off-by: Andrew Cooper --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie Somewhat RFC. I don't particularly like the double handling of MSR_K8_EXT_FEATURE_MASK in this function, but I can't find any way of making the logic legible while trying to dedup the MSR accesses. --- xen/arch/x86/cpu/amd.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index a14a12fb1d60..06646fc1af93 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 #include "cpu.h" =20 @@ -639,6 +640,40 @@ static void amd_early_adjust_cpuid_extd(void) printk(XENLOG_INFO "CPU: Re-enabling disabled Topology Extensi= ons Support\n"); } } + + /* + * Probe for NX support if it appears to be unavailable. All 64-bit + * capable AMD CPUs support it, but some firmwares have an option to h= ide + * it in CPUID, apparently for "feature parity" with Intel platforms. + * + * Unlike Intel, there's no active indication that this has been done.= A + * conversation with AMD suggests that if we can set EFER.NXE, then NX + * will work. Use this as a heuristic to probe for support, coping wi= th + * the fact that a hypervisor might have really disabled and blocked N= X, + * and not emulate the mask MSRs either. + */ + if ( !boot_cpu_has(X86_FEATURE_NX) ) + { + uint64_t *this_efer =3D &this_cpu(efer); + + if ( wrmsr_safe(MSR_EFER, *this_efer | EFER_NXE) =3D=3D 0 ) + { + *this_efer |=3D EFER_NXE; + + if ( !rdmsr_safe(MSR_K8_EXT_FEATURE_MASK, &val) ) + { + val |=3D 1ULL << cpufeat_bit(X86_FEATURE_NX); + wrmsr_safe(MSR_K8_EXT_FEATURE_MASK, val); + val =3D rdmsr(MSR_K8_EXT_FEATURE_MASK); + if ( val & (1ULL << cpufeat_bit(X86_FEATURE_NX)) ) + { + __set_bit(X86_FEATURE_NX, c->x86_capability); + printk(XENLOG_INFO "re-enabled NX protection\n"); + bootsym(trampoline_efer) |=3D EFER_NXE; + } + } + } + } } =20 void __init cf_check early_init_amd(void) --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450072; cv=none; d=zohomail.com; s=zohoarc; b=B3Vq6miLFDf1QKz15zppDBS72xrm+N9o1uUDwK4KdiQC1gWUdozjN2HdJHb9DLP+sZ3mmIgouxIPHn42saYT3Qucpq7NT+3Se6nt1FrBLPJFJuEDJseT23VGngVDIXF++2N7Nw/V6C52uNmb1fdvZMo1dN4CW6/+2EGTXzTeNsQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769450072; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=l9ikuESfoJcCbCA9QaHk2aoC+EFlVlVQjy3heIMiHxU=; b=CME77UtRLspLQiV4wqAAfIQTPW9yPO2F4YRafNxZLTfN9LMcU0jrtZhJeggKdHD5ur2WTIVmvFLEmgOl2HgIGrEk2Y13PQCjyoYs6U2j7SppNYy2ybKeJlt6wJ4Ie4p73o6eOIgrEFik1cLEBe9E6JojLochmVQazlRbN+svOyw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769450072745410.4895970818436; Mon, 26 Jan 2026 09:54:32 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1213841.1524381 (Exim 4.92) (envelope-from ) id 1vkQmp-0006sd-Lq; Mon, 26 Jan 2026 17:54:03 +0000 Received: by outflank-mailman (output) from mailman id 1213841.1524381; Mon, 26 Jan 2026 17:54:03 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmp-0006ps-7m; Mon, 26 Jan 2026 17:54:03 +0000 Received: by outflank-mailman (input) for mailman id 1213841; Mon, 26 Jan 2026 17:54:01 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmn-0004HX-BR for xen-devel@lists.xenproject.org; Mon, 26 Jan 2026 17:54:01 +0000 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [2a00:1450:4864:20::32b]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id fe2434e2-fadf-11f0-9ccf-f158ae23cfc8; Mon, 26 Jan 2026 18:53:59 +0100 (CET) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-47ee4539adfso52102525e9.3 for ; Mon, 26 Jan 2026 09:53:59 -0800 (PST) Received: from localhost.localdomain (host-92-26-102-188.as13285.net. [92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:58 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fe2434e2-fadf-11f0-9ccf-f158ae23cfc8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450039; x=1770054839; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l9ikuESfoJcCbCA9QaHk2aoC+EFlVlVQjy3heIMiHxU=; b=cALF6zl3kNzFlDLkSd9pc7xG6FPIyrwSQjRlfPgY9YCNz/m3JgEIPKtOI/Arw6+/lz YsXq7aqN4kPUQ97Oj8FGjFiRb1pedE6slgcFJViDAIiBcaRRhLn3kRMI0SuDWkksHfc6 kthTXxPMy2lB8dzi5cJFtLSHJOPXVF2JSzBZU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450039; x=1770054839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=l9ikuESfoJcCbCA9QaHk2aoC+EFlVlVQjy3heIMiHxU=; b=ox4gDOe691eSC/9QjUtzRf4B+Mt/7GplsKqWRceZKZZBT+MVPeEAWLQFMpUAS+r6Qk KGRTUbbOEmMP6g0JWEWN8M4t3SimmdlxP1jIMhnWF27Z6eBE2Qn8RbePhInTzWlnxX5y kZfmIrSsO+9x3MQHYHFb19cwBurNINfzoNIK4ZFHIpLvzHZqhbY5dSJzmjeePcc5VVL7 V4Io8ZJE7oNBSVbFMO0hyzStUBERmrNQ6JdNNCy9KXv9DGFTx6fuRobH1tWgwm7v6l2e 166OUhYzR0mdZLuSwGiFlDl37pz5arx/iGzzrwjyY15VhIJxqcSoDszjqZi6a6HGlT9i 4xXw== X-Gm-Message-State: AOJu0YxqRGbKiEPiPfP7JVVBKG3v5cqPW3yJVUlgHPs62JG+sd49zh/U zMflVpoFTSzFqjjP/ysdtunYlnb/zSTPSPh3nnV1HeV9f3sAEgw7viIA+RgqmqHMS5X//eivREw IK4aV X-Gm-Gg: AZuq6aJ69eRTkwFjxT6rGO6ShigR8OLot53Kggr0JYEaECGHnW4kSdzkvs+eg1lm/Fo lKWLhJLNPaoYwfNyoURQOGmqLAECq/xgDVBBC/OAmEQB+PuDLAkAAwkDRM5ffRvwoz4dgZJGG3r xSJcs3dXmubN3xrUlZ6NnhaCnQYRfz+5i9QrbQ5ornkBXh5eTJ+ADsDz++gGGvlaamb4kWDhuXY 9MDNK4ciN52SHSrm6RSPyGq64mPpHpjpRAVNWpzMUOqGbwKlWK/fo9JwP02NX7ghX2b/8ju9V3q Gns7BO1w6Bx8q9cNEr2tzaP7mh466YX1Ftwko0pjJuU2V6DulCHoQLp4wOI+QzOsNb5q8BhCIZ3 MRD3RL6PrlZrf6LngfBxdmHOzvNk7649tvtVAKhaIJHM7w8+HfOxF3sJqy3MWgpjbG75mJuNcSq 0RoXxM1SUFuACKVGd18rKMI4POuargEFNqpiPMtAdw1EWQU25uJ2R4dpXGHPaqXQ== X-Received: by 2002:a05:600c:528d:b0:477:54cd:200e with SMTP id 5b1f17b1804b1-4805ce3f893mr82672025e9.1.1769450038902; Mon, 26 Jan 2026 09:53:58 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 13/16] x86/cpu: Drop NOISY_CAPS Date: Mon, 26 Jan 2026 17:53:42 +0000 Message-Id: <20260126175345.2078371-14-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450074535158500 These were plausibly useful for debugging when there were 4 words in x86_capability[], but it's currently 22 words and growing. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie Even I can't read it in hex any more. --- xen/arch/x86/cpu/common.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 0249bb4bf2dc..7674cca1ba93 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -598,13 +598,6 @@ void identify_cpu(struct cpuinfo_x86 *c) c->x86_capability[FEATURESET_m10Ah] =3D val >> 32; } =20 -#ifdef NOISY_CAPS - printk(KERN_DEBUG "CPU: After vendor identify, caps:"); - for (i =3D 0; i < NCAPINTS; i++) - printk(" %08x", c->x86_capability[i]); - printk("\n"); -#endif - /* * Vendor-specific initialization. In this section we * canonicalize the feature flags, meaning if there are @@ -641,13 +634,6 @@ void identify_cpu(struct cpuinfo_x86 *c) =20 xstate_init(c); =20 -#ifdef NOISY_CAPS - printk(KERN_DEBUG "CPU: After all inits, caps:"); - for (i =3D 0; i < NCAPINTS; i++) - printk(" %08x", c->x86_capability[i]); - printk("\n"); -#endif - /* * If RDRAND is available, make an attempt to check that it actually * (still) works. --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450066; cv=none; d=zohomail.com; s=zohoarc; b=kmQcd0491vAcD4vJCvUa0cJhil8HB7HUPmLcbOAFc0r2EYy02JoETeq9Hf+sMRq8Qo/+z4wlkua9XHeTem+vSJrjvBQkWXBV0mgLi3C14K9vewS8vjMxMZtoGyfpehcSpIi957XtXJTKR2qb5CbZVS+UtnO4237rqC7hH3BxmSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769450066; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=c1ONjoPKEWiY2hmWsIYX5khT8mAnFR/6SGFmL+oGZ7U=; b=awubIeqsNfRPVlazYFUe6lcV806zrW+LcI1QwqsLexfm34t/r/nx/+y4CfSppH4pScYvadsCKboHnHw9El64Z15bmLyi3TYx81OtkQjuatcdgAcfhIt26UOwx/S0nEmbBbnRULJXXujgUWzR9EjijX+5zWXgSGLEDjlUobYhT8Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769450066153563.439757921951; Mon, 26 Jan 2026 09:54:26 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1213842.1524389 (Exim 4.92) (envelope-from ) id 1vkQmr-0007Dj-2m; Mon, 26 Jan 2026 17:54:05 +0000 Received: by outflank-mailman (output) from mailman id 1213842.1524389; Mon, 26 Jan 2026 17:54:04 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmq-0007BU-Lw; Mon, 26 Jan 2026 17:54:04 +0000 Received: by outflank-mailman (input) for mailman id 1213842; Mon, 26 Jan 2026 17:54:01 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmn-0004HW-KA for xen-devel@lists.xenproject.org; Mon, 26 Jan 2026 17:54:01 +0000 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [2a00:1450:4864:20::32a]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fe79a932-fadf-11f0-b15f-2bf370ae4941; Mon, 26 Jan 2026 18:54:00 +0100 (CET) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-47ee937ecf2so40779595e9.0 for ; Mon, 26 Jan 2026 09:54:00 -0800 (PST) Received: from localhost.localdomain (host-92-26-102-188.as13285.net. [92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:59 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fe79a932-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450039; x=1770054839; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c1ONjoPKEWiY2hmWsIYX5khT8mAnFR/6SGFmL+oGZ7U=; b=k6N3qPTTsWg85Hzq1f4mG5dmYFyb9igbxl6SpLLIXkiQCs9KWqjUa/C7mJdrFwTHCM yCs+VTc4Mo6Ln0J7C6Vs+l6xJhFc9YSkJ+7bMYMUwaDMLplktd0SfUSGkYwrGDqRiaPQ Qq1+cJhF2pzD+YQkJ1hwHoHSuNG7HIGo08U9k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450039; x=1770054839; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=c1ONjoPKEWiY2hmWsIYX5khT8mAnFR/6SGFmL+oGZ7U=; b=CdlBNAJL/JbURbn1qVHdAB/CL7vXbDvdJ/PBMMXIRRe7eh07NBJzZwr6r4rMri4/D+ VzwGlbnMLiKVjq6z+ehsZL8fxcKtcMJsCjHK1jD7XuNacGRHRset3H+xiiEhYzhSH+Jf Ejxso6l60Su8/T5hkDiSIa8qf1+TvFBkKkBV5wcRgsYG8x4Omk7n09cuoYhRu/OV0fYp LnMvhTVV0QimzYGa6+fTavRKLFoixTttPbDn4rrzRG6P//cHw6Y6H0b3UEWq8K4u6smc 21+g1GT6ScIJTB+w72D6/ArSsm8CY2Qkrf9iBlVjUgz95OY2yo5omk348Qa2euQfeDIO evOA== X-Gm-Message-State: AOJu0YwA3tgUSuuGJWKzD/Ac2LhngBGK9NYaETSq94bEGS67FhT+1N3+ oMklAFEI6xQvI9zGhynmThzgcI475vZRSF/DYmKYHT1d/D4jCfOYkGBK13M84zVXL5GH2boSNlg /aM8J X-Gm-Gg: AZuq6aIRqpuijwD0bf/qvENC9XdTyFB/ZE+Q0Ak3xo9K4GIAvOXcuXjMhLU6XHTmx4/ H0sRaHozAlvbo2zMB9Ba3F6SNU0jP4LZ3JPNiLm9yZW+WwmmxWXaujCcbebuUzB5L+/lsXBTdql UIsg4f16JVxKlFyrhSpzXLjMBW73J4JHp/XoqBEBfFcpmn8GbnOVgsbgLNxn+P8PyH5GIDf8F6H ri1zqEnTdCHshmZ1zjBfP1lSsEcA56F5EIQqbyc3gdMX8wyOgXs99QY/TACS/SDlejNbpcpp4EW ZxFwOqMd3VmwH+PwEAh47enK/vwR+6oc8ClvmFCBve5AaNejE6VC0rLPAdTyTmNXmQRwsOrGEwO li7jwlENQe/XoJPNwHJbEbpssP3pxI5LLcG54B+S1YOupc8R0Xr71NHTqjekurKa6V8Q7InVGn+ Y2J0V//OmqViNCZgGRdaF/rYzecXX2zHSf8jIcXLu3loVGtazGdK8zQhKhpz+1+T60m4W6wnPR X-Received: by 2002:a05:600c:5297:b0:477:a289:d854 with SMTP id 5b1f17b1804b1-4805cd2026amr94916305e9.5.1769450039455; Mon, 26 Jan 2026 09:53:59 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 14/16] x86/cpu: Drop default_init() and default_cpu Date: Mon, 26 Jan 2026 17:53:43 +0000 Message-Id: <20260126175345.2078371-15-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450068440158500 While the comment is reasonable, clearing SEP as the only action for an unknown CPU is useless. Drop the infrastructure. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/common.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index 7674cca1ba93..bab2193e9ba3 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -100,15 +100,6 @@ bool __init is_forced_cpu_cap(unsigned int cap) return test_bit(cap, forced_caps) || test_bit(cap, cleared_caps); } =20 -static void cf_check default_init(struct cpuinfo_x86 * c) -{ - /* Not much we can do here... */ - __clear_bit(X86_FEATURE_SEP, c->x86_capability); -} - -static const struct cpu_dev __initconst_cf_clobber __used default_cpu =3D { - .c_init =3D default_init, -}; static struct cpu_dev __ro_after_init actual_cpu; =20 static DEFINE_PER_CPU(uint64_t, msr_misc_features); @@ -375,7 +366,6 @@ void __init early_cpu_init(bool verbose) case X86_VENDOR_SHANGHAI: actual_cpu =3D shanghai_cpu_dev; break; case X86_VENDOR_HYGON: actual_cpu =3D hygon_cpu_dev; break; default: - actual_cpu =3D default_cpu; if (!verbose) break; printk(XENLOG_ERR --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; a=rsa-sha256; t=1769450074; cv=none; d=zohomail.com; s=zohoarc; b=ETyb6p7Xn6Ucn5IP0KVIm5cN5rC3pLMUnfFhPExuUUSUmjFiNmBQZb+HuLYbsz2jltmUurwvcRMEcHH5AfJb3+U9RgKV/1O3paKoBpwMghP2oqH1lgvjiloWRiJisThk2i2G8rgvx74ajqif8eLmEkGo0z7HJ8nOURROOEchCl4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1769450074; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=oCtWZ5jsIOSUx1eQSxD4nCRKX4JQJ1b+ozb5fk5XF6E=; b=WXbVPyFcYzmmfItpYEoKBhgBBzoKznaZ5ng7tHQ64vE7wHAU38FPYT3M0fu5/sETxOVNHZQBA7q4IaOgOSZkNslU1egWkqy3UFJR94JzJTXJb8mEy8InLd8BcJaaexEFJLxX9mUMbn3226h7DrIwKyicNqlCNq63IPrPLiB5GPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1769450074293550.9773545089932; Mon, 26 Jan 2026 09:54:34 -0800 (PST) Received: from list by lists.xenproject.org with outflank-mailman.1213843.1524398 (Exim 4.92) (envelope-from ) id 1vkQms-0007Sj-JT; Mon, 26 Jan 2026 17:54:06 +0000 Received: by outflank-mailman (output) from mailman id 1213843.1524398; Mon, 26 Jan 2026 17:54:06 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmr-0007OB-OR; Mon, 26 Jan 2026 17:54:05 +0000 Received: by outflank-mailman (input) for mailman id 1213843; Mon, 26 Jan 2026 17:54:02 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1vkQmo-0004HW-KW for xen-devel@lists.xenproject.org; Mon, 26 Jan 2026 17:54:02 +0000 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [2a00:1450:4864:20::336]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id fec40fdb-fadf-11f0-b15f-2bf370ae4941; Mon, 26 Jan 2026 18:54:00 +0100 (CET) Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-4805ef35864so11603905e9.0 for ; Mon, 26 Jan 2026 09:54:00 -0800 (PST) Received: from localhost.localdomain (host-92-26-102-188.as13285.net. [92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.53.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:53:59 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: fec40fdb-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450040; x=1770054840; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oCtWZ5jsIOSUx1eQSxD4nCRKX4JQJ1b+ozb5fk5XF6E=; b=Hxh1cCQHWBqWBiwzUbkftqMBtcyLrl0t8N/iMtZQYEKDxP1e5biIgvFMoxCU6uu0R/ TiRYZzV9qOl1xEszYskDPdn4F0X8cDIdVbZi9VMcaeJZ4PNUjNdNOWOg42Vt5kM0XSG+ raSdmamK8Vv/XgnBpEwCPeenP7PuaL60CGRlM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450040; x=1770054840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=oCtWZ5jsIOSUx1eQSxD4nCRKX4JQJ1b+ozb5fk5XF6E=; b=a0IYXUnbTdaczKnhuzBZ+/vW2uJhSsw95UnDZ3MJ7aAcWgI99J9oHVZz/EJU7rGkCs 4o3OKRdn6X4EA/GrPwIY7exEHR8cCrhnCavTV45wKQOP098zF6KZqGmJet9ulOFNMRdB IVZP7EWQgvbpaWklpWSY143KNS6pooKHcdOKp1+f3myW0xUitgvUFEWkaed3WFaiQ7j2 hi+fxTaWHPz9e6xHGx2H8iAXfQIibaWk2loRcXIZKVqAvnXvp1nHm1soyv18LilokZfj hwnNBL+pJC7lGFeLzn1DC+L8x9heArEoGS93oPKXW1FYcfNIYvLJbbEoZM+sksI0yJZH RmiA== X-Gm-Message-State: AOJu0YyO7D2CfSk88BlTjTIajfKNNauREt71mQtNJvJDgQl6lhHxKedQ dN5TOVkBrrFgiOLc1N2zMO3/laMtLOZuAcjE1fKylU3z3h7BuPTDWptStspca37aYe7Qo11GknB Z4VAb X-Gm-Gg: AZuq6aK85J3u/zTw2d4XrPg9pMahaPUojx2hhWFpGgMMP1IDQjPdmKs7DKOjTSgFEwQ h9E9L5vWkdHgU1nDxY7NSXDw3DlZKdyaDxIo1r7Ztj/isOvcDUy2Ii2XDfQg9nNpDtSE7Wd43ma L4nypfBAM1DamRLDTq7WTDCbmpwF1DbmtuaXAOQkyaCaT5JTMCt/Bry8vgCq1iG6cEvRUQt7lYb CYvtUqGK2qiciY8t51gwdANkwi7uwkVEvLDGAeG5/GkqPjSDUgYESwiolbsMPcl/JXWnfqOaTsC 5k1JArskuWdVescYuRB2yLpXzQsUcZTHRtiH9n/BAqaRljYj9EEEfJ5eObbxITnzR4YGUJSVRQg qbnkg4SIiY038lFwrQ07KmvHNDUMlGPFr3720HaUKAuxUxIpILgoIhhnX5LBP+KpvrZkodycFMY 7KsljQOTEpoh3Q73EhK8HdNkcIz0qYa03saF5klaXCYEn+zuUVfahCe54hRzslcw== X-Received: by 2002:a05:600c:b96:b0:480:1e8f:d15f with SMTP id 5b1f17b1804b1-4805cd40a06mr82761325e9.2.1769450039908; Mon, 26 Jan 2026 09:53:59 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 15/16] x86/cpu: Clean up use of LCAP_* constants Date: Mon, 26 Jan 2026 17:53:44 +0000 Message-Id: <20260126175345.2078371-16-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450074590158500 Now that the LCAP_* constants are single bits, we can simplify the expressi= ons using them. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/cpu/amd.c | 12 ++++++------ xen/arch/x86/domain.c | 10 +++++----- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index 06646fc1af93..f259a2112a16 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -171,7 +171,7 @@ void cf_check amd_ctxt_switch_masking(const struct vcpu= *next) (nextd && is_pv_domain(nextd) && nextd->arch.pv.cpuidmasks) ? nextd->arch.pv.cpuidmasks : &cpuidmask_defaults; =20 - if ((levelling_caps & LCAP_1cd) =3D=3D LCAP_1cd) { + if (levelling_caps & LCAP_1cd) { uint64_t val =3D masks->_1cd; =20 /* @@ -192,7 +192,7 @@ void cf_check amd_ctxt_switch_masking(const struct vcpu= *next) #define LAZY(cap, msr, field) \ ({ \ if (unlikely(these_masks->field !=3D masks->field) && \ - ((levelling_caps & cap) =3D=3D cap)) \ + (levelling_caps & cap)) \ { \ wrmsr_amd(msr, masks->field); \ these_masks->field =3D masks->field; \ @@ -251,7 +251,7 @@ static void __init amd_init_levelling(void) */ probe_masking_msrs(); =20 - if ((levelling_caps & LCAP_1cd) =3D=3D LCAP_1cd) { + if (levelling_caps & LCAP_1cd) { uint32_t ecx, edx, tmp; =20 cpuid(0x00000001, &tmp, &tmp, &ecx, &edx); @@ -264,7 +264,7 @@ static void __init amd_init_levelling(void) cpuidmask_defaults._1cd =3D ((uint64_t)ecx << 32) | edx; } =20 - if ((levelling_caps & LCAP_e1cd) =3D=3D LCAP_e1cd) { + if (levelling_caps & LCAP_e1cd) { uint32_t ecx, edx, tmp; =20 cpuid(0x80000001, &tmp, &tmp, &ecx, &edx); @@ -275,7 +275,7 @@ static void __init amd_init_levelling(void) cpuidmask_defaults.e1cd =3D ((uint64_t)ecx << 32) | edx; } =20 - if ((levelling_caps & LCAP_7ab0) =3D=3D LCAP_7ab0) { + if (levelling_caps & LCAP_7ab0) { uint32_t eax, ebx, tmp; =20 cpuid(0x00000007, &eax, &ebx, &tmp, &tmp); @@ -283,7 +283,7 @@ static void __init amd_init_levelling(void) cpuidmask_defaults._7ab0 &=3D ((uint64_t)eax << 32) | ebx; } =20 - if ((levelling_caps & LCAP_6c) =3D=3D LCAP_6c) { + if (levelling_caps & LCAP_6c) { uint32_t ecx =3D cpuid_ecx(6); =20 cpuidmask_defaults._6c &=3D (~0ULL << 32) | ecx; diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index c29a6b0decee..441f99e92088 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -303,7 +303,7 @@ void domain_cpu_policy_changed(struct domain *d) =20 if ( is_pv_domain(d) ) { - if ( ((levelling_caps & LCAP_1cd) =3D=3D LCAP_1cd) ) + if ( levelling_caps & LCAP_1cd ) { uint64_t mask =3D cpuidmask_defaults._1cd; uint32_t ecx =3D p->basic._1c; @@ -368,7 +368,7 @@ void domain_cpu_policy_changed(struct domain *d) d->arch.pv.cpuidmasks->_1cd =3D mask; } =20 - if ( ((levelling_caps & LCAP_6c) =3D=3D LCAP_6c) ) + if ( levelling_caps & LCAP_6c ) { uint64_t mask =3D cpuidmask_defaults._6c; =20 @@ -378,7 +378,7 @@ void domain_cpu_policy_changed(struct domain *d) d->arch.pv.cpuidmasks->_6c =3D mask; } =20 - if ( ((levelling_caps & LCAP_7ab0) =3D=3D LCAP_7ab0) ) + if ( levelling_caps & LCAP_7ab0 ) { uint64_t mask =3D cpuidmask_defaults._7ab0; =20 @@ -395,7 +395,7 @@ void domain_cpu_policy_changed(struct domain *d) d->arch.pv.cpuidmasks->_7ab0 =3D mask; } =20 - if ( ((levelling_caps & LCAP_Da1) =3D=3D LCAP_Da1) ) + if ( levelling_caps & LCAP_Da1 ) { uint64_t mask =3D cpuidmask_defaults.Da1; uint32_t eax =3D p->xstate.Da1; @@ -406,7 +406,7 @@ void domain_cpu_policy_changed(struct domain *d) d->arch.pv.cpuidmasks->Da1 =3D mask; } =20 - if ( ((levelling_caps & LCAP_e1cd) =3D=3D LCAP_e1cd) ) + if ( levelling_caps & LCAP_e1cd ) { uint64_t mask =3D cpuidmask_defaults.e1cd; uint32_t ecx =3D p->extd.e1c; --=20 2.39.5 From nobody Sat Feb 7 06:55:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=reject dis=none) header.from=citrix.com ARC-Seal: i=1; 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[92.26.102.188]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48066c10dbasm3896455e9.15.2026.01.26.09.54.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jan 2026 09:54:00 -0800 (PST) X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: ff44c60d-fadf-11f0-b15f-2bf370ae4941 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1769450041; x=1770054841; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AM0AV4MNuYAd316Xwda7bgSZwEFUvVU+olFepXiLw+U=; b=NdKv04Phlgl8+qr4D8xRyxT6YieLWJuAXAXkzoeysG5z/fVBjJ8mkbQRR0UbZ1qpmb c1baY6rfChBrqO5zB3qMpHj+kr/7nsApgDRGTvcWw9XUl2AsE2YTEU76AGp35Ut/8U+f G0cmrqPklJajSZYsubPRVJXUNyHbfQwRWlIvw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1769450041; x=1770054841; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=AM0AV4MNuYAd316Xwda7bgSZwEFUvVU+olFepXiLw+U=; b=f7CxMO1MFJJnSWwqB8qoI9rrnzfMa6CYbnKnLXn+gCfvgBaUiJhBsjYvj/RZvAwoeo dWyLP/RZpl/o8607qtbE4YxScsToJlHmMWywHZEryo2RYX1SdTTxoe3yzomESrtuW1E5 2OT1cs89kRKRwKYKfKsy2Bj1oyNtOUICo6fjtdoizxaNfupMtVZVeUSoua6l421BE/Cs MV2PY4gnhT1JC8u1uJmE4H+4B2YbOFipJy/yg9Ri25THbyGB6gwsfeQlnpkQB8PR562z VaY1tEhtt3Nqb/ufr3z/Ffb6kLGDbnZ+SbLGV6ueV/8C1A75Zh1gQ9rbVohlSXXSVhs/ vTrA== X-Gm-Message-State: AOJu0YxQeIo2GoOteneGq/RmJOg2R52f/ufMTm10re3Q9n9K9NylDA6z iNWfX6sMU50pGt1sco24xEDsXUOlO5N8hEJ0IOLbR2nZDhkc1vt825EOnRdpK7ZF58tFYmD8HEs wRcas X-Gm-Gg: AZuq6aL6hvXCSY8QncMB3AQ1c3kzsfnUZIUEzVeWgMXHxA/0PUcOKFAMuDJtxcEjjxJ V5ZdS//a0s8O2S2fwAlb6hi9o3rCx176vZRqnJwDAL8l1CZbFE9/zAGkUOzIq07DXtts4VIBKeT gS5sLL63Am69xJCM/bjK8qgJpgdj+aMkvrG2m6u0eD3SrwBxapPCRi+UXufGssfsg0raTclod20 3HoeqgYluLIRrmrAIfg9OKz1A/h+WF+8Y+4UoSSEic9ZS3I9O6HtjdtpoysDgFHpfB2wVOiwA7G FQHkiqqtwclQREA8XBuuyKd/7JlFfyAFAvm9xreK3AUY0I7oQttHN3m2KnPys/2+h15MBZN73pt jIhkhCjuAZaH4oMD7qGNyXDlM/wuVojhNlcT354DNZyYthpUZzeghlZZf2PVQYWHix+kp9+MH5N b++wl58JfnS7/wwVQHSxi6yJyoNin6oMJhOmIUPRqmhAKLeFyUteurIJBbjysVAw== X-Received: by 2002:a05:600c:358d:b0:47e:e61d:b8d2 with SMTP id 5b1f17b1804b1-4805d0645fcmr91718615e9.27.1769450040383; Mon, 26 Jan 2026 09:54:00 -0800 (PST) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?UTF-8?q?Roger=20Pau=20Monn=C3=A9?= , Julian Vetter , Teddy Astie Subject: [PATCH 16/16] x86/cpuid: Drop the include of public/sysctl.h Date: Mon, 26 Jan 2026 17:53:45 +0000 Message-Id: <20260126175345.2078371-17-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260126175345.2078371-1-andrew.cooper3@citrix.com> References: <20260126175345.2078371-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @citrix.com) X-ZM-MESSAGEID: 1769450072056154100 Following the removal of XEN_SYSCTL_get_cpu_levelling_caps, asm/cpuid.h doesn't need to include public/sysctl.h, but several other header files were picking up their includes transitively through asm/cpuid.h. Untangle them. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monn=C3=A9 CC: Julian Vetter CC: Teddy Astie --- xen/arch/x86/include/asm/cpuid.h | 2 -- xen/arch/x86/include/asm/hvm/hvm.h | 2 ++ xen/arch/x86/include/asm/hvm/vlapic.h | 2 ++ xen/arch/x86/include/asm/hvm/vpt.h | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/include/asm/cpuid.h b/xen/arch/x86/include/asm/cp= uid.h index c7ee1d54bc7e..774cfdf86894 100644 --- a/xen/arch/x86/include/asm/cpuid.h +++ b/xen/arch/x86/include/asm/cpuid.h @@ -7,8 +7,6 @@ #include #include =20 -#include - extern const uint32_t known_features[FSCAPINTS]; =20 /* diff --git a/xen/arch/x86/include/asm/hvm/hvm.h b/xen/arch/x86/include/asm/= hvm/hvm.h index af042ae858af..ede685d030bd 100644 --- a/xen/arch/x86/include/asm/hvm/hvm.h +++ b/xen/arch/x86/include/asm/hvm/hvm.h @@ -19,6 +19,8 @@ #include =20 struct pirq; /* needed by pi_update_irte */ +struct hvm_hw_cpu; +struct xen_domctl_createdomain; =20 #ifdef CONFIG_HVM_FEP /* Permit use of the Forced Emulation Prefix in HVM guests */ diff --git a/xen/arch/x86/include/asm/hvm/vlapic.h b/xen/arch/x86/include/a= sm/hvm/vlapic.h index c38855119836..f442dec3d975 100644 --- a/xen/arch/x86/include/asm/hvm/vlapic.h +++ b/xen/arch/x86/include/asm/hvm/vlapic.h @@ -12,6 +12,8 @@ #include #include =20 +#include + #define vcpu_vlapic(x) (&(x)->arch.hvm.vlapic) #define vlapic_vcpu(x) (container_of((x), struct vcpu, arch.hvm.vlapic)) #define const_vlapic_vcpu(x) (container_of((x), const struct vcpu, \ diff --git a/xen/arch/x86/include/asm/hvm/vpt.h b/xen/arch/x86/include/asm/= hvm/vpt.h index 0b92b286252d..24f0918280cd 100644 --- a/xen/arch/x86/include/asm/hvm/vpt.h +++ b/xen/arch/x86/include/asm/hvm/vpt.h @@ -12,6 +12,8 @@ #include #include =20 +#include + /* * Abstract layer of periodic time, one short time. */ --=20 2.39.5