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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jan 2026 14:30:05.4981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c03ed46-9e11-4612-ca8c-08de58f99228 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7545 X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1769005858789158500 Content-Type: text/plain; charset="utf-8" Configure the Bus Lock intercept when supported by the host. The VMCB counter is initialised to zero so it fires upon the first instruction that locks the bus. On the #VMEXIT handler that counter is set to 1 because it has fault behaviour and the offending instruction needs to re-execute. Signed-off-by: Alejandro Vallejo --- v2: * Moved the P() call to this patch. We don't want to print until the feature is fully supported. * Removed the initialisation of the counter to 1 in vmcb.c, so it's implicitly zero-initialised. --- xen/arch/x86/hvm/svm/svm.c | 6 ++++++ xen/arch/x86/hvm/svm/vmcb.c | 3 +++ xen/arch/x86/hvm/svm/vmcb.h | 4 ++-- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 5d23603fc1..abda5a9063 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -2524,6 +2524,7 @@ const struct hvm_function_table * __init start_svm(vo= id) P(cpu_has_tsc_ratio, "TSC Rate MSR"); P(cpu_has_svm_sss, "NPT Supervisor Shadow Stack"); P(cpu_has_svm_spec_ctrl, "MSR_SPEC_CTRL virtualisation"); + P(cpu_has_svm_bus_lock, "BusLock-Intercept Filter"); #undef P =20 if ( !printed ) @@ -3087,6 +3088,11 @@ void asmlinkage svm_vmexit_handler(void) break; } =20 + case VMEXIT_BUS_LOCK: + perfc_incr(buslock); + vmcb->bus_lock_count =3D 1; + break; + default: unexpected_exit_type: gprintk(XENLOG_ERR, "Unexpected vmexit: reason %#"PRIx64", " diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c index cbee10d046..15223a693e 100644 --- a/xen/arch/x86/hvm/svm/vmcb.c +++ b/xen/arch/x86/hvm/svm/vmcb.c @@ -66,6 +66,9 @@ static int construct_vmcb(struct vcpu *v) GENERAL2_INTERCEPT_XSETBV | GENERAL2_INTERCEPT_ICEBP | GENERAL2_INTERCEPT_RDPRU; =20 + if ( cpu_has_svm_bus_lock ) + vmcb->_general3_intercepts |=3D GENERAL3_INTERCEPT_BUS_LOCK; + /* Intercept all debug-register writes. */ vmcb->_dr_intercepts =3D ~0u; =20 diff --git a/xen/arch/x86/hvm/svm/vmcb.h b/xen/arch/x86/hvm/svm/vmcb.h index 231f9b1b06..68cf5eaf0b 100644 --- a/xen/arch/x86/hvm/svm/vmcb.h +++ b/xen/arch/x86/hvm/svm/vmcb.h @@ -68,7 +68,7 @@ enum GenericIntercept2bits /* general 3 intercepts */ enum GenericIntercept3bits { - GENERAL3_INTERCEPT_BUS_LOCK_THRESH =3D 1 << 5, + GENERAL3_INTERCEPT_BUS_LOCK =3D 1 << 5, }; =20 /* control register intercepts */ @@ -497,7 +497,7 @@ struct vmcb_struct { u8 guest_ins_len; /* offset 0xD0 */ u8 guest_ins[15]; /* offset 0xD1 */ u64 res10a[8]; /* offset 0xE0 */ - u16 bus_lock_thresh; /* offset 0x120 */ + u16 bus_lock_count; /* offset 0x120 */ u16 res10b[3]; /* offset 0x122 */ u64 res10c[91]; /* offset 0x128 pad to save area */ =20 --=20 2.43.0