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Fri, 26 Dec 2025 14:54:19 -0800 (PST) Received: from barry-desktop.hub ([47.72.129.29]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34e772ac1acsm9981428a91.9.2025.12.26.14.54.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Dec 2025 14:54:18 -0800 (PST) From: Barry Song <21cnbao@gmail.com> To: catalin.marinas@arm.com, m.szyprowski@samsung.com, robin.murphy@arm.com, will@kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, xen-devel@lists.xenproject.org, Barry Song , Leon Romanovsky , Ada Couprie Diaz , Ard Biesheuvel , Marc Zyngier , Anshuman Khandual , Ryan Roberts , Suren Baghdasaryan , Joerg Roedel , Tangquan Zheng Subject: [PATCH RFC v2 8/8] dma-iommu: Support DMA sync batch mode for iommu_dma_sync_sg_for_{cpu, device} Date: Sat, 27 Dec 2025 11:52:48 +1300 Message-ID: <20251226225254.46197-9-21cnbao@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20251226225254.46197-1-21cnbao@gmail.com> References: <20251226225254.46197-1-21cnbao@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Barry Song Apply batched DMA synchronization to iommu_dma_sync_sg_for_cpu() and iommu_dma_sync_sg_for_device(). For all buffers in an SG list, only a single flush operation is needed. I do not have the hardware to test this, so the patch is marked as RFC. I would greatly appreciate any testing feedback. Cc: Leon Romanovsky Cc: Marek Szyprowski Cc: Catalin Marinas Cc: Will Deacon Cc: Ada Couprie Diaz Cc: Ard Biesheuvel Cc: Marc Zyngier Cc: Anshuman Khandual Cc: Ryan Roberts Cc: Suren Baghdasaryan Cc: Robin Murphy Cc: Joerg Roedel Cc: Tangquan Zheng Signed-off-by: Barry Song --- drivers/iommu/dma-iommu.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index ffa940bdbbaf..b68dbfcb7846 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -1131,10 +1131,9 @@ void iommu_dma_sync_sg_for_cpu(struct device *dev, s= truct scatterlist *sgl, iommu_dma_sync_single_for_cpu(dev, sg_dma_address(sg), sg->length, dir); } else if (!dev_is_dma_coherent(dev)) { - for_each_sg(sgl, sg, nelems, i) { + for_each_sg(sgl, sg, nelems, i) arch_sync_dma_for_cpu(sg_phys(sg), sg->length, dir); - arch_sync_dma_flush(); - } + arch_sync_dma_flush(); } } =20 @@ -1144,16 +1143,16 @@ void iommu_dma_sync_sg_for_device(struct device *de= v, struct scatterlist *sgl, struct scatterlist *sg; int i; =20 - if (sg_dma_is_swiotlb(sgl)) + if (sg_dma_is_swiotlb(sgl)) { for_each_sg(sgl, sg, nelems, i) iommu_dma_sync_single_for_device(dev, sg_dma_address(sg), sg->length, dir); - else if (!dev_is_dma_coherent(dev)) - for_each_sg(sgl, sg, nelems, i) { + } else if (!dev_is_dma_coherent(dev)) { + for_each_sg(sgl, sg, nelems, i) arch_sync_dma_for_device(sg_phys(sg), sg->length, dir); - arch_sync_dma_flush(); - } + arch_sync_dma_flush(); + } } =20 static phys_addr_t iommu_dma_map_swiotlb(struct device *dev, phys_addr_t p= hys, --=20 2.43.0